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* MLK-12416-7 imx: skip ahb clock setting for i.MX6ULPeng Fan2016-03-25-7/+9
| | | | | | | No need to set ahb clock for i.MX6UL, since rom code already configured the clock at the freq 396M/132M Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-10546-2 imx: mx7 implement reset_miscPeng Fan2016-03-25-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | On mx7d 12x12 lpddr3 arm2 board, POR_B reset in uboot will fail stress reset test, and hangs in rom code. Rom log buffer show thats wrong hab_image_entry and runs into serial download mode. Also there is no time delay reset circuit for this board. We found when disable CONFIG_VIDEO, all seems fine. Actually, only the following piece of code can make stress reset ok, " writel(LCDIF_CTRL1_VSYNC_EDGE_IRQ, &regs->hw_lcdif_ctrl1_clr); while (--timeout) { if (readl(&regs->hw_lcdif_ctrl1) & LCDIF_CTRL1_VSYNC_EDGE_IRQ) break; udelay(1); } " Here we use lcdif_power_down API which is better to shutdown lcdif same as the way used in arch_preboot_os. Implement reset_misc for mx7, since it does not hurt for others boards. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit cd1bd6ee94e720af911a2ce7db697af0df59c0a9)
* MLK-10708 imx:mx6qp Update Saturation THR for PRExPeng Fan2016-03-25-4/+4
| | | | | | | | | Update settings for PRE. Value for Saturation THR of PREx, changed from 0x20 to 0x10 to make system more stable. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit 02e7090604e55d9690532294b02b499609d46e63) (cherry picked from commit f7c5cf580fcc2c8ab95a8d835f5874d26216910f)
* MLK-12563: imx: mx6ul evk: fix LCD_nPWREN settingPeng Fan2016-03-25-1/+1
| | | | | | | Q901 is PMOS, LCD_nPWREN should be at low voltage then output is 3V3. If LCD_nPWREN is high, output is 2.4V which is not correct. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12551: imx6ul evk: fix 74LV OE usagePeng Fan2016-03-25-7/+1
| | | | | | | | | | | Fix 74LV OE gpio index. pinmux is correct, but gpio index is wrong, so gpio output will not have effect, since we use wrong GPIO5_IO18, but not correct GPIO5_IO8. And at the end of the initialization of 74lv init, should keep OE voltage level at LOW, but not high. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12488 mx6sl/ul/sx: Fix incorrect clear mmdc_ch0 handshake maskYe Li2016-03-25-1/+4
| | | | | | | | | Since the MX6UL/SL/SX only has one DDR channel, in CCM_CCDR register the bit[17] for mmdc_ch0 is reserved and its proper state should be 1. When clear this bit, the periph_clk_sel cannot be set and that CDHIPR[periph_clk_sel_busy] handshake never clears. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12483-5 mx6ul: Enable module fuse check EVK board and DDR3 ARM2 boardYe Li2016-03-25-2/+64
| | | | | | | Enable the configurations CONFIG_MODULE_FUSE and CONFIG_OF_SYSTEM_SETUP for module fuse check. And modify board level codes for SD, FEC and EIM. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12483-4 mx6: Modify drivers to disable fused modulesYe Li2016-03-25-10/+103
| | | | | | | | | | Add the fuse checking in drivers, when the module is disabled in fuse, the driver will not work. Changed drivers: BEE, GPMI, APBH-DMA, ESDHC, FEC, QSPI, ECSPI, I2C, USB-EHCI, GIS, LCDIF. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12483-3 mx6: Add a module fuse checkingYe Li2016-03-25-1/+393
| | | | | | | | | | | | | | | Implement a functionality to read the soc fuses and check if any module is fused. For fused module, we have to disable it in u-boot dynamically, and change the its node in FDT to "disabled" status before starting the kernel. In this patch, we implement the ft_system_setup for FDT fixup. This function will be called during boot process or by "fdt systemsetup" command. To enable the module fuse checking, two configurations must be defined: CONFIG_MODULE_FUSE CONFIG_OF_SYSTEM_SETUP Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12483-1 common: Fix fdt command systemsetup issueYe Li2016-03-25-1/+1
| | | | | | | | | The fdt command "fdt systemsetup" can't work because the do_fdt check the start char 's' for command "fdt set". So the fdt systemsetup will also go into the "fdt set" in fault. Fix this problem by checking the whole word "set" for "fdt set" command. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12442: imx: mx6qarm2: lpddr2 set dram 2 channel fixed modeAdrian Alonso2016-03-25-4/+26
| | | | | | | | | | | | | Setup MMDC in two channel fixed mode Initialize dram banks for two channel fixed mode DRAM bank = 0x00000000 -> start = 0x10000000 -> size = 0x20000000 DRAM bank = 0x00000001 -> start = 0x80000000 -> size = 0x20000000 Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
* MLK-12371-2: imx: mx7dsabresd: fix POR reset failed after DDR enter retentionRobin Gong2016-03-25-0/+9
| | | | | | | Since DDR enter retention mode after kernel enter DSM mode, we have to exit DDR retention mode before uboot boot, so add this in DCD and plugin code. Signed-off-by: Robin Gong <yibin.gong@nxp.com> (cherry picked from commit 62248ef80dabbd7601ff4e2969368d7bf54896d9)
* MLK-12562 mx6: HAB: Add support for i.MX6SOLOYe Li2016-03-25-6/+11
| | | | | | Need to check cpu type for i.MX6SOLO for the HAB functions addresses. Signed-off-by: Ye Li <ye.li@nxp.com>
* ENGR00315894-55 iMX6SX: add debug monitor supportYe.Li2016-03-25-0/+14
| | | | | | | | | | | | | Debug monitor will print out last failed AXI access info when system reboot is caused by AXI access failure, only works when debug monitor is enabled. Enable this module on i.MX6SX. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit df6ac8531d498021ed379c74fc1847bd2cec7179) Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10674-2 imx: mx6qp settings for PREPeng Fan2016-03-25-2/+32
| | | | | | | | | | | | | | | | | | | | | | Since the following piece settings can not be in DCD table, we add them in enable_ipu_clock. " setmem /32 0x00bb048c = 0x00000002 ## Bypass IPU1 QoS generator setmem /32 0x00bb050c = 0x00000002 ## Bypass IPU2 QoS generator setmem /32 0x00bb0690 = 0x00000200 ## Bandwidth THR for of PRE0 setmem /32 0x00bb0710 = 0x00000200 ## Bandwidth THR for of PRE1 setmem /32 0x00bb0790 = 0x00000200 ## Bandwidth THR for of PRE2 setmem /32 0x00bb0810 = 0x00000200 ## Bandwidth THR for of PRE3 setmem /32 0x00bb0694 = 0x00000020 ## Saturation THR for of PRE0 setmem /32 0x00bb0714 = 0x00000020 ## Saturation THR for of PRE1 setmem /32 0x00bb0794 = 0x00000020 ## Saturation THR for of PRE2 setmem /32 0x00bb0814 = 0x00000020 ## Saturation THR for of PRE " CONFIG_VIDEO_IPUV3 is always defined in mx6sabre_common.h, the settings sure will effect. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit 61cec88a59ebf450dd1352d81e03b5aa842e1d71)
* MLK-10496: Check the PL310 version for applying errataNitin Garg2016-03-25-9/+18
| | | | | | | | | | | | Apply errata based on PL310 version instead of compile time. Also set Prefetch offset to 15, since it improves memcpy performance by 35%. Don't enable Incr double Linefill enable since it adversely affects memcpy performance by about 32MB/s and reads by 90MB/s. Tested with 4K to 16MB sized src and dst aligned buffer. Signed-off-by: Nitin Garg <nitin.garg@freescale.com> (cherry picked from commit 31751fa9cf29ef4056f49fe06a54700a89c9bdc5)
* MLK-10176-6 imx: mx7: Modify GPT timer driver for mx7Peng Fan2016-03-25-1/+8
| | | | | | | | | | | | Modify the GPT common platform driver for mx7 which only use 24Mhz OSC as clock source. Note: at default, the mx7d will use system counter as timer. The GPT is disabled. Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 6e250796d6a07d84093eeae96e5a6e4c593cdb0b) Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* ENGR00328312 i2c: imx: Optimize the i2c device recovery solutionFugang Duan2016-03-25-2/+26
| | | | | | | | | | | | | | | | | | From i2c spec, if device pull down the SDA line that causes i2c bus dead, host can send out 9 clock to let device release SDA. But for some special device like pfuze100, it pull down SDA line and the solution cannot take effort. The patch just add NACK and STOP signal after 8 dummy clock, and pmic can release SDA line after the recovery. Test case catch 375 times of i2c hang, and all are recovered. Signed-off-by: Fugang Duan <B38611@freescale.com> (cherry picked from commit 53118db42d201d36ca9067b4bb0e2702399e100b) Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit b8dcb812401026cb2189b24a4f6058830151c85a)
* MLK-12560 mx6: Enable eMMC boot support for all mx6Ye Li2016-03-25-6/+1
| | | | | | | | Set the CONFIG_SUPPORT_EMMC_BOOT in mx6_common.h to enable the eMMC boot support for all mx6 platforms. Remove the duplicated definition in board's header file. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12559 mx6: Enable memory test commandYe Li2016-03-25-0/+5
| | | | | | | Set the CONFIG_CMD_MEMTEST on all mx6 platforms for enabling the u-boot memory test. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12558 mx6qarm2: Modify the ENV_OFFSET to 512KB on SD/MMCYe Li2016-03-25-1/+1
| | | | | | | To align the ENV_OFFSET with other boards, set it to 512Kbytes for mx6qarm2 boards when booting from SD/MMC card. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-10576 ARM: i.MX6: exclude the ARM errata from i.MX6 UP systemNitin Garg2016-03-25-0/+3
| | | | | | | | | | | | | | | | The ARM errata 751472, 794072, 761320, 845369 only applied to the following configuration: This erratum affects configurations with either: - One processor if the ACP is present - Two or more processors i.MX6 family does not have the ACP and thus only the MPCore system will be impacted, which are the i.MX6DQ, i.MX6DL, and i.MX6QP. Signed-off-by: Nitin Garg <nitin.garg@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com> (cherry picked from commit 0db960784ba4f631ee5c0321b5d25f3b1ac55640)
* MLK-10524: iMX6x: Implement workaround for Cortex-A9 errata 845369Nitin Garg2016-03-25-0/+8
| | | | | | | | | | Under very rare timing circumstances, transitioning into streaming mode might create a data corruption. Present on Two or more processors or 1 core with ACP, all revisions. This erratum can be worked round by setting bit[22] of the undocumented Diagnostic Control Register to 1. Signed-off-by: Nitin Garg <nitin.garg@freescale.com> (cherry picked from commit 70ad44e523680de67dd8b7a7505d7f27799980ee)
* MLK-12557 mx6ul: Enable syscounter as default timerYe Li2016-03-25-3/+11
| | | | | | Use syscounter for i.MX6UL platform as default timer, not use gpt Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12555-3 mx7dsabresd: Remove the SRS setting for wdogYe Li2016-03-25-6/+0
| | | | | | | Since the WDOG driver has updated to clear SRS at software assertion of WDOG. We don't need this in board level. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12555-2 mx6ulevk: Enable the Watchdog WDOG_B signal outputYe Li2016-03-25-0/+2
| | | | | | | | When using watchdog timeout in kernel, the reset does not output the WDOG_B signal, so the power supply won't be reset. To solve the problem, we enable it in u-boot. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12555 mx6sxsabreauto: Enable the Watchdog WDOG_B signal outputYe Li2016-03-25-0/+3
| | | | | | | | When using watchdog timeout in kernel, the reset does not output the WDOG_B signal, so the power supply won't be reset. To solve the problem, we enable it in u-boot. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12553 mx6sabresd: Add RGMII supportYe Li2016-03-25-0/+33
| | | | | | | Need to configure the phy AR8031 to output 125Mhz clock for ENET reference clock. And introduce a TX clock delay. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-11230 imx6: USB: Modify OTG ID pin pad setting to pull upYe.Li2016-03-25-6/+31
| | | | | | | | | | Set the ID pin pad to pull up not the pull down at default, otherwise we can't enter the device mode, but always detect as host. After this change we have to use portA cable to play as host, and use portB cable for device. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00325255 pcie:enable pcie support on imx6sx sdYe Li2016-03-25-6/+106
| | | | | | | | | | | | | | | | Enable pcie support in uboot on imx6sx sd boards - enable_pcie_clock should be call before ssp_en is set, since that ssp_en control the phy_ref clk gate, turn on it after the source of the pcie clks are stable. - add debug info - add rx_eq of gpr12 on imx6sx - there are random link down issue on imx6sx. It's pcie ep reset issue. solution:reset ep, then retry link can fix it. (cherry picked from commit ec78595a24b5ff1020baa97b6d6e79a3a3326307) Signed-off-by: Richard Zhu <r65037@freescale.com> Signed-off-by: Ye Li <ye.li@nxp.com>
* ENGR00319965 pcie: mask the imx6sl outRichard Zhu2016-03-25-15/+19
| | | | | | | | | imx6sl doesn't have the pcie module, mask the pcie related codes from imx6sl. Signed-off-by: Richard Zhu <r65037@freescale.com> (cherry picked from commit acaff11da33f8f0cb1521d3c48e64e7ed9a87bec) Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* ENGR00319415 pcie: random link down issue after warm-rstRichard Zhu2016-03-25-0/+18
| | | | | | | | | | | | | | | | | | | | There are about 0.02% percentage on some imx6q/dl/solo hw boards, random pcie link down when warm-reset is used. Make sure to clear the ref_ssp_en bit16 of gpr1 before warm-rst, and set ref_ssp_en after the pcie clks are stable to workaround it. rootcause: * gpr regisers wouldn't be reset by warm-rst, while the ref_ssp_en is required to be reset by pcie. (work-around in u-boot) * ref_ssp_en should be set after pcie clks are stable. (work-around in kernel) Signed-off-by: Richard Zhu <r65037@freescale.com> (cherry picked from commit 5cc825b12c6b86a22f1a6a0535b52cf3ee142e77) Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit 6193cf4e3384a59e29546d13a67657f7faeafc9e)
* MLK-11064 imx: mx6qp: Adjust AQos settings for peripheralsYe.Li2016-03-25-0/+3
| | | | | | | | | | To resolve USB camera bandwidth issue, the patch sets recommended AQoS setting from IC team value for peripheral and only on imx6qp. The address is: 0xbb0608, the value is: 0x80000201 Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 11906c712a52e7a20caf71d7c5da4e951a59db29)
* MLK-12534 mx6: shutdown vddpu and PCIE phy to save powerYe Li2016-03-25-0/+40
| | | | | | | | | | | | | | | | | | Shutdown VDDPU and PCIE phy to save power. For PCIE, the i.MX6SL and i.MX6UL does not have this module, so don't need it. For VDDPU, the i.MX6UL does not have GPU, does not need it. And on i.MX6QP there is narrow window that PRE driver is ready but GPU driver probe later, and the later GPU driver turn on PU may cause 'PRE hang' issue. To simplify thing, do not turn off PU in u-boot. Reference: commit: 6b0787b726e2ff32210d742d93ecd3f4bb2ae402 commit: 4bd0032c0eba50fa0caf43f50f735a3cfbe36a8d Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12533 mx6sx: select OSC as uart's clk parentYe Li2016-03-25-0/+13
| | | | | | | | | | As M4 is sourcing UART clk from OSC, to make UART work when M4 is enabled, need to select OSC as clk parent, 24M OSC is enough for debug UART in uboot. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Anson Huang <b20788@freescale.com> (cherry picked from commit b5e1b393192099e91c5cb75b69291c87eacb9f60)
* MLK-12532 mx6ul: Add work around for PMIC_STBY_REQ_PAD on TO1.0Ye Li2016-03-25-0/+9
| | | | | | | | According to the design team's requirement, on i.MX6UL, the PMIC_STBY_REQ_PAD should be configured to open drain 100K. The TO1.1 has fixed the issue, add work around for TO1.0. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12531 mx6sxsabresd: Add CM4 fast boot up demoYe Li2016-03-25-13/+33
| | | | | | | | | | | | | | | | | This is a demo that CM4 will boot up by u-boot without typing any command. It boots up at u-boot early init, try to minimize the time from power up to the CM4 running. Since CM4 runs on QSPI NOR XIP, we have to disable the QSPI driver in u-boot to avoid conflict. RDC for shared GPIO1 is added, but not enabled, because the kernel is not ready for shared GPIO1. Users can uncomment the CONFIG_IMX_RDC to enable it. Some legacy codes in mx6sxsabreauto are removed. We only need this work on mx6sxsabresd as a demo. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12527-3 android: Add board support to enable android fastbootYe Li2016-03-25-27/+1277
| | | | | | | | | | | Add board level support for android fastboot feature. Each board has a android specified header file for defining android related configuraitons. And add build targets for their android uboot images building. For mx6qsabreauto, mx6sabresd and mx7dsabresd, we enable the android fastboot exclusive with DFU. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12527-2 android: Add FSL android fastboot supportYe Li2016-03-25-5/+2478
| | | | | | | | | | | | | | | | | | | | | Integrate the FSL android fastboot features into community's fastboot. 1. Use USB gadget g_dnl driver 2. Integrate the FSL SD/SATA/NAND flash operations, since the GPT and EFI partitions are not support by i.MX. 3. Add FDT support to community's android image. 4. Add a new boot command "boota" for android image boot. The boota implements to load ramdisk and fdt to their loading addresses specified in boot.img header, while bootm won't do it for android image. 5. Support the authentication of boot.img at the "load_addr" for both SD and NAND. 6. We use new configuration CONFIG_FSL_FASTBOOT for Freescale's fastboot with relevant header file "fsl_fastboot.h". While disabling the configuration, the community fastboot is used. 7. Overwrite the cmdline in boot.img by using bootargs saved in local environment. 8. Add recovery and reboot-bootloader support. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12527-1 mxc_keyb: Add MXC keyboard driverYe Li2016-03-25-0/+834
| | | | | | | | | | | | | | The i.MX6SL EVK needs this driver in android fastboot support. Add this driver to u-boot. To use the driver, user must define: CONFIG_MXC_KPD Enable the driver CONFIG_MXC_KEYMAPPING Key mapping matrix CONFIG_MXC_KPD_COLMAX The column size of key mapping matrix CONFIG_MXC_KPD_ROWMAX The row size of the key mapping matrix Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12530 ehci: Fix OTG ID detection issue on mx7Ye Li2016-03-25-4/+5
| | | | | | | | | | | | There are two problems in EHCI driver for mx7, and cause the OTG ID detection failed to work. 1. The offset for phy_status register in usbnc_regs is not correct. 2. We should clear the USBNC_PHYCFG2_ACAENB bit to enable the OTG ID detection, not set it. When the bit is set, the ACA Resistance Detection is enabled, which disables the OTG ID detection, because the internal pull up is off. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12529 mx7dsabresd: Fix soc revision check issueYe Li2016-03-25-1/+1
| | | | | | | The is_soc_rev returns true when the revision is matched, this is opposited with uboot v2015 which returns 0. Have to fix this for mx7dsabresd Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12528 mx7: Enable secure mode for mx7 platformsYe Li2016-03-25-0/+1
| | | | | | | | | The CONFIG_MX7_SEC is not set at default, so the MX7 goes to non-secure mode before jumping to kernel, and needs PSCI works for secure mode operations. We have to set the CONFIG_MX7_SEC to enable the secure mode, otherwise we will get some kernel panic issues. Signed-off-by: Ye Li <ye.li@nxp.com>
* MA-7455-1 Pico: modify Pico configuration for Brillo.Peng Fan2016-03-25-157/+47
| | | | | | | | | Modify the picosom to be suit for Brillo configurations. Signed-off-by: Haoran Wang <Haoran.Wang@freescale.com> (cherry picked from commit 864fd4f019674e8333b1fdb91e9242ae75f35992) To align with 2016.03, fix several places. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MA-7455 Import picosom boot codesHaoran Wang2016-03-25-0/+1326
| | | | | | | | | Imported the picosom boot codes and board configs from technexion. Signed-off-by: Tapani Utriainen <tapani@technexion.com> Signed-off-by: Haoran Wang <Haoran.Wang@freescale.com> (cherry picked from commit d102c193f3f903055239f07ddbaab63715dbf82f)
* MLK-12416-6 imx: rdc: misc fix and updateYe Li2016-03-25-9/+50
| | | | | | | | | Change CONFIG_MXC_RDC to CONFIG_IMX_RDC. Do misc update in board header file to support RDC for M4 usage. Fix rdc interface imx_rdc_check_permission change in mxc_gpio. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12500-2 HAB: Add commented secure boot configurationsYe Li2016-03-25-1/+71
| | | | | | | | | | CONFIG_SECURE_BOOT is used for signed image building, this configuration is not enabled at default. Comment it in board header files. Users can uncomment it to enable. Also add CONFIG_CSF_SIZE for defining the CSF reserved size Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12500-1 HAB: Add kernel image authentication in image loadingYe Li2016-03-25-0/+33
| | | | | | | | | To support the trust boot chain, we integrate the authentication into the kernel image loading process. The kernel image will be verified at its load address. So when signing the kernel image, we need to use this load address which may change on different platforms. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12497-2 mx7d: Add reference DDR script for mx7d TO1.0Ye Li2016-03-25-0/+745
| | | | | | | | | | | | | | | | | | | On i.MX7D TO1.1, design team adds a mux cell at the CKE path to fix the suspend mode reset issue, but seems it add extra delay on CKE path, so CKE-CK timing violated. When DDR enters self-refresh or retention for long time(> 15seconds per testing on some boards), DDR data corruption occured, not able to decrease CKE delay, so we have to add extra delay on all other signals to balance it. DDR script needs to be fine-tuned according to this hardware change. For DDR3, since the timing margin is not good, we have to decrease the DDR frequency from 533Mhz to 400Mhz. We uses TO1.1 script at default, and retains the TO1.0 script for reference. Compass link: http://compass.freescale.net/livelink/livelink?func=ll&objid=235010235&objAction=browse&sort=name Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12497-1 mx7d: Add support for all mx7d arm2 boardsYe Li2016-03-25-2/+5153
| | | | | | | Porting all mx7d arm2 boards (mx7d 12x12 lpddr3, 12x12 ddr3, 19x19 ddr3, 19x19 lpddr2, 19x19 lpddr3) support from u-boot v2015.04. Signed-off-by: Ye Li <ye.li@nxp.com>
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