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| * | powerpc/85xx: Add FMan ethernet support to P4080DSAndy Fleming2011-09-29-5/+635
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for RGMII, SGMII, and XAUI (10Gb) Ethernet on P4080DS. The board supports add-on cards for SGMII and XAUI functionality. Which slots on the board these cards are in is a function of the SERDES option selected and muxes on the board. Additionally because of the high-configurablity which MDIO bus one is connected to is "selected" via an FPGA register. We create dummy MDIO bus for the phy layer and hide the mux manipulation in this dummy layer. Add fman fdt helper function in board common code it'll be used by several freescale boards that do various muxing of the MDIO signals based on which controller/interface one is trying to talk to. Removed CONFIG_SYS_FMAN_FW as its not used anywhere. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: Add support for FMan ethernet in Independent modeKumar Gala2011-09-29-12/+3068
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Frame Manager (FMan) on QorIQ SoCs with DPAA (datapath acceleration architecture) is the ethernet contoller block. Normally it is utilized via Queue Manager (Qman) and Buffer Manager (Bman). However for boot usage the FMan supports a mode similar to QE or CPM ethernet collers called Independent mode. Additionally the FMan block supports multiple 1g and 10g interfaces as a single entity in the system rather than each controller being managed uniquely. This means we have to initialize all of Fman regardless of the number of interfaces we utilize. Different SoCs support different combinations of the number of FMan as well as the number of 1g & 10g interfaces support per Fman. We add support for the following SoCs: * P1023 - 1 Fman, 2x1g * P4080 - 2 Fman, each Fman has 4x1g and 1x10g * P204x/P3041/P5020 - 1 Fman, 5x1g, 1x10g Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Dai Haruki <dai.haruki@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Ioana Radulescu <ruxandra.radulescu@freescale.com> Signed-off-by: Lei Xu <B33228@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Shaohui Xie <b21989@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/mpc8548cds: Cleanup mpc8548cds.cZhao Chenhui2011-09-29-7/+0
| | | | | | | | | | | | | | | | | | | | | Remove unnecessary or dead code/includes. Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/mp: add support for discontiguous coresTimur Tabi2011-09-29-29/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some SOCs have discontiguously-numbered cores, and so we can't determine the valid core numbers via the FRR register any more. We define CPU_TYPE_ENTRY_MASK to specify a discontiguous core mask, and helper functions to process the mask and enumerate over the set of valid cores. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: corenet_ds - Remove unused 'execute' perm in TLB entriesKumar Gala2011-09-29-15/+15
| | | | | | | | | | | | | | | | | | | | | We shouldn't be setting execute permissions on TLB entries that will not actually have any code run from them. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | fdt: Add new fdt_create_phandle helperKumar Gala2011-09-29-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | Add a helper function that will return a phandle value for the given node. If the node doesn't have a phandle already one will be created. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Gerald Van Baren <vanbaren@cideas.com>
| * | fdt: Rename fdt_create_phandle to fdt_set_phandleKumar Gala2011-09-29-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | The old fdt_create_phandle didn't actually create a phandle it just set one. We'll introduce a new helper that actually does creation. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Gerald Van Baren <vanbaren@cideas.com>
| * | powerpc/85xx: Fix compile warnings/errors if CONFIG_SYS_DPAA_FMAN isn't setKumar Gala2011-09-29-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | Add ifdef protection around fman specific code related to device tree clock setup. If we dont have CONFIG_SYS_DPAA_FMAN defined we shouldn't be executing this code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | fsl_ifc: Add the workaround for erratum IFC A-003399(enabled on P1010)Poonam Aggrwal2011-09-29-0/+95
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Issue: Address masking doesn't work properly. When sum of the base address, defined by BA, and memory bank size, defined by AM, exceeds 4GB (0xffff_ffff) then AMASKn[AM] doesn't mask CSPRn[BA] bits. Impact: This will impact booting when we are reprogramming CSPR0(BA) and AMASK0(AMASK) while executing from NOR Flash. Workaround: Re-programming of CSPR(BA) and AMASK is done while not executing from NOR Flash. The code which programs the BA and AMASK is executed from L2-SRAM. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/P1010: Add workaround for erratum P1010-A003549 (related to IFC)Poonam Aggrwal2011-09-29-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Issue: Peripheral connected to IFC_CS3 may hamper booting from IFC. Impact: Boot from IFC may not be successful if IFC_CS3 is used. Workaround: If IFC_CS3 is used, gate IFC_CS3 while booting from NAND or NOR. Also Software should select IFC_CS3 using PMUXCR[26:27] = 0x01. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | fsl_ifc: Add the workaround for erratum IFC-A002769 (enable on P1010)Poonam Aggrwal2011-09-29-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Issue: The NOR-FCM does not support access to unaligned addresses for 16 bit port size Impact: When 16 bit port size is used, accesses not aligned to 16 bit address boundary will result in incorrect data Workaround: The workaround is to switch to GPCM mode for NOR Flash access. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: Expanding the window of CCSRBAR in AS=1 from 4k to 1MPoonam Aggrwal2011-09-29-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For an IFC Erratum (A-003399) we will need to access IFC registers in cpu_init_early_f() so expand the TLB covering CCSR to 1M. Since we need a TLB to cover 1M we move to using TLB1 array for all the early mappings so we can cover various sizes beyond 4k. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: Add NAND/NAND_SPL support to P1010RDBDipen Dudhat2011-09-29-0/+332
| | | | | | | | | | | | | | | | | | | | | | | | | | | And various defines to enable NAND support and NAND spl code for the P1010RDB platform. Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | nand: Freescale Integrated Flash Controller NAND supportDipen Dudhat2011-09-29-7/+1149
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add NAND support (including spl) on IFC, such as is found on the p1010. Note that using hardware ECC on IFC with small-page NAND (which is what comes on the p1010rdb reference board) means there will be insufficient OOB space for JFFS2, since IFC does not support 1-bit ECC. UBI should work, as it does not use OOB for anything but ECC. When hardware ECC is not enabled in CSOR, software ECC is now used. Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> [scottwood@freescale.com: ECC rework and misc fixes] Signed-off-by: Scott Wood <scottwood@freescale.com>
| * | powerpc/85xx: Add basic support for P1010RDBPoonam Aggrwal2011-09-29-0/+1477
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Boot methods supported: NOR Flash, SPI Flash and SDCARD This patch adds the following basic interfaces: DDR3, eTSEC, DUART, I2C, SD/MMC, USB, SATA, PCIe, NOR Flash, SPI Flash. P1010RDB Overview ----------------- 1Gbyte DDR3 (on board DDR) Local Bus (IFC): 32Mbyte 16bit NOR flash 32Mbyte SLC NAND Flash 64KB CPLD device(GPCM interface) SPI Flash: 128 Mbit SPI Flash memory SD/MMC: connector to interface with the SD memory card SATA: 1 internal SATA connect to 2.5. 160G SATA2 HDD 1 eSATA connector to rear panel USB 2.0: x1 USB 2.0 port: connected via a UTMI PHY to Mini-AB interface. x1 USB 2.0 port: directly connected to Mini-AB interface Ethernet eTSEC: eTSEC1: Connected to RGMII PHY VSC8641XKO eTSEC2: Connected to SGMII PHY VSC8221 eTSEC3: Connected to SGMII PHY VSC8221 eCAN: Two DB-9 female connectors for Field bus interface UART: supports two UARTs up to 115200 bps for console TDM: 2 FXS ports connected via an external SLIC to the TDM interface. SLIC: SPI SLIC I2C: Serial EEprom Real time clock 256 Kbit M24256 I2C EEPROM PCIe: PCIe and mPCIe connectors. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: Add support for new P102x/P2020 RDB style boardsLi Yang2011-09-29-0/+2289
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following boards share a common design but with minor variations between them: P1020MSBG-PC P1020RDB-PC P1020UTM-PC P1021RDB-PC P1024RDB P1025RDB P2020RDB-PC The P1020RDB-PC shares its roots in the existing P1020RDB board design, however uses DDR3 instead of DDR2. P2020RDB-PC differs from the P102x RDB-PC with 64-bit DDR and 100Mhz SYSCLK. Key features on these boards include: * DDR3 * NOR flash * NAND flash (on RDB's only) * SPI flash (on RDB's only) * SDHC/MMC card slot * VSC7385 Ethernet switch (on P1020MBG, P1020RDB, & P1021RDB) * PCIE slot and mini-PCIE slots As these boards use soldered DDR chips not regular DIMMs, an on-board EEPROM is used to store SPD data. In case of absent or corrupted SPD, falling back to timing data embedded in the source code will be used. Raw timing data is extracted from DDR chip datasheet. Different speeds of DDR are supported with this approach. ODT option is forced to fit this set of boards, again because they don't have regular DIMMs. CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS is defined as 5ms to meet specification for writing timing. VSC firmware Address is defined by default in config file for eTSEC1. SD width is based off DIP switch. DIP switch is detected on the board by reading i2c bus and setting the appropriate mux values. Some boards have QE module in the silicon (P1021 and P1025). QE and eLBC have pins multiplexing. QE function needs to be disabled to access Nor Flash and CPLD. QE-UEC and QE-UART can be enabled for linux kernel by setting "qe" in hwconfig. In addition, QE-UEC and QE-TDM also have pins multiplexing, to enable QE-TDM for linux kernel, set "qe;tdm" in hwconfig. Syntax is as below 'setenv hwconfig qe' to enable QE UEC/UART and disable Nor-Flash/CPLD. 'setenv hwconfig 'qe;tdm'' to enalbe QE TDM and disable Nor-Flash/CPLD. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Zhao Chenhui <b26998@freescale.com> Signed-off-by: Matthew McClintock <msm@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Tang Yuantian <b29983@freescale.com> Signed-off-by: ramneek.mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Matthew McClintock <msm@freescale.com> Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Akhil Goyal <akhil.goyal@freescale.com>
| * | powerpc/85xx: relocate CCSR before creating the initial RAM areaTimur Tabi2011-09-29-58/+234
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before main memory (DDR) is initialized, the on-chip L1 cache is used as a memory area for the stack and the global data (gd_t) structure. This is called the initial RAM area, or initram. The L1 cache is locked and the TLBs point to a non-existent address (so that there's no chance it will overlap main memory or any device). The L1 cache is also configured not to write out to memory or the L2 cache, so everything stays in the L1 cache. One of the things we might do while running out of initram is relocate CCSR. On reset, CCSR is typically located at some high 32-bit address, like 0xfe000000, and this may not be the best place for CCSR. For example, on 36-bit systems, CCSR is relocated to 0xffe000000, near the top of 36-bit memory space. On some future Freescale SOCs, the L1 cache will be forced to write to the backing store, so we can no longer have the TLBs point to non-existent address. Instead, we will point the TLBs to an unused area in CCSR. In order for this technique to work, CCSR needs to be relocated before the initram memory is enabled. Unlike the original CCSR relocation code in cpu_init_early_f(), the TLBs we create now for relocating CCSR are deleted after the relocation is finished. cpu_init_early_f() will still need to create a TLB for CCSR (at the new location) for normal U-Boot purposes. This is done to keep the impact to existing U-Boot code minimal and to better isolate the CCSR relocation code. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: introduce and document CONFIG_SYS_CCSRBAR macrosTimur Tabi2011-09-29-277/+170
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce the CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW macros, which contain the high and low portions of CONFIG_SYS_CCSRBAR_PHYS. This is necessary for the assembly-language code that relocates CCSR, since the assembler does not understand 64-bit constants. CONFIG_SYS_CCSRBAR_PHYS is automatically defined from the CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW macros, so it should not be defined in a board header file. Similarly, CONFIG_SYS_CCSRBAR_DEFAULT is defined for each SOC in config_mpc85xx.h, so it should also not be defined in the board header file. CONFIG_SYS_CCSR_DO_NOT_RELOCATE is a "short-cut" macro that guarantees that CONFIG_SYS_CCSRBAR_PHYS is set to the same value as CONFIG_SYS_CCSRBAR_DEFAULT, and so CCSR will not be relocated. Since CONFIG_SYS_CCSRBAR_DEFAULT is locked to a fixed value, multi-stage U-Boot builds (e.g. NAND) are required to relocate CCSR only during the last stage (i.e. the "real" U-Boot). All other stages should define CONFIG_SYS_CCSR_DO_NOT_RELOCATE to ensure that CCSR is not relocated. README is updated with descriptions of all the CONFIG_SYS_CCSRBAR_xxx macros. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: Enable internal USB UTMI PHY on p204x/p3041/p50x0Kumar Gala2011-09-29-0/+5
| | | | | | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: Add ULPI and UTMI USB Phy support for P1010/P1014Ramneek Mehresh2011-09-29-3/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add UTMI and ULPI PHY support for USB controller on qoriq series of processors with internal UTMI PHY implemented, for example P1010/P1014 - Use both getenv() and hwconfig to get USB phy type till getenv() is depricated - Introduce CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY to specify if soc has internal UTMI phy Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Acked-by: Remy Bohmer <linux@bohmer.net> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | | Merge branch 'master' of git://git.denx.de/u-boot-i2cWolfgang Denk2011-10-04-19/+25
|\ \ \ | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-i2c: I2C: mv_i2c: fix multi-bus init issue I2C: mv_i2c: fix build issue when enable debug option
| * | | I2C: mv_i2c: fix multi-bus init issueLei Wen2011-10-03-18/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When enable the multi-bus, the current_bus is not inited in the original implementation, which make the i2c operation unpredicatable. Signed-off-by: Lei Wen <leiwen@marvell.com>
| * | | I2C: mv_i2c: fix build issue when enable debug optionLei Wen2011-10-03-1/+1
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | When DEBUG_I2C is open, the following build issue would shows up. mv_i2c.c: In function 'i2c_transfer': mv_i2c.c:257: error: 'ISR' undeclared (first use in this function) mv_i2c.c:257: error: (Each undeclared identifier is reported only once mv_i2c.c:257: error: for each function it appears in.) Signed-off-by: Lei Wen <leiwen@marvell.com>
* | | Merge branch 'emaclite' of git://git.denx.de/u-boot-microblazeWolfgang Denk2011-10-04-39/+46
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'emaclite' of git://git.denx.de/u-boot-microblaze: net: emaclite: Use dynamic allocation net: emaclite: Remove baseaddress from xemaclite net: emaclite: Use calloc instead of malloc net: emaclite: Remove deviceid property net: emaclite: Change driver name and add address
| * | | net: emaclite: Use dynamic allocationMichal Simek2011-10-03-16/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Every emaclite instance use own setting. Signed-off-by: Michal Simek <monstr@monstr.eu> Acked-by: Mike Frysinger <vapier@gentoo.org>
| * | | net: emaclite: Remove baseaddress from xemacliteMichal Simek2011-10-03-21/+21
| | | | | | | | | | | | | | | | | | | | | | | | Use dev->iobase instead of baseaddress. Signed-off-by: Michal Simek <monstr@monstr.eu>
| * | | net: emaclite: Use calloc instead of mallocMichal Simek2011-10-03-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Simplify driver logic and clear eth_device structure in one command. Signed-off-by: Michal Simek <monstr@monstr.eu>
| * | | net: emaclite: Remove deviceid propertyMichal Simek2011-10-03-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | Cleanup structure. Signed-off-by: Michal Simek <monstr@monstr.eu>
| * | | net: emaclite: Change driver name and add addressMichal Simek2011-10-03-1/+1
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | Current xilinx emaclite use net multi registration but doesn't support several emaclites interfaces. Changing driver name with adding address to name is the first step how to distiguish several drivers. Signed-off-by: Michal Simek <monstr@monstr.eu>
* | | Merge branch 'master' of git://git.denx.de/u-boot-microblazeWolfgang Denk2011-10-04-38/+40
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-microblaze: microblaze: Enable FDT/FIT support microblaze: Remove address offset for uart16550 microblaze: Do not select NFS for platforms without ethernet microblaze: Clean up reset asm code microblaze: Save and restore first unused vector microblaze: Setup MB vectors if feature is enable for u-boot microblaze: Remove debug saving value
| * | | microblaze: Enable FDT/FIT supportMichal Simek2011-10-03-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | Enable FDT and FIT support. Signed-off-by: Michal Simek <monstr@monstr.eu>
| * | | microblaze: Remove address offset for uart16550Michal Simek2011-10-03-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | U-Boot BSP handle 0x3 offset for big endian systems. Little endian Microblaze systems don't use any offset. Signed-off-by: Michal Simek <monstr@monstr.eu>
| * | | microblaze: Do not select NFS for platforms without ethernetMichal Simek2011-10-03-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Undefined network functionality for systems without ethernet and disable NFS support. Signed-off-by: Michal Simek <monstr@monstr.eu>
| * | | microblaze: Clean up reset asm codeMichal Simek2011-10-03-20/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Remove code copying - Reset address is setup from first stage bootloader - Support reset vector setup on little endian Signed-off-by: Michal Simek <monstr@monstr.eu>
| * | | microblaze: Save and restore first unused vectorMichal Simek2011-10-03-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use one memory space to detect little/big endian platforms. The first unused address(0x28) is used instead 0x0 address (reset vectors). Detection rewrited reset vector setup from first stage bootloader. Workflow: 1. Store 0x28 to r7 2. Do little/big endian test 3. Restore r7 to 0x28 Signed-off-by: Michal Simek <monstr@monstr.eu>
| * | | microblaze: Setup MB vectors if feature is enable for u-bootMichal Simek2011-10-03-12/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | For example: Setup reset vectors if reset address is setup. Setup user exception vector if user exception is enabled Signed-off-by: Michal Simek <monstr@monstr.eu>
| * | | microblaze: Remove debug saving valueMichal Simek2011-10-03-2/+0
| |/ / | | | | | | | | | | | | | | | Forget to remove debug code. Signed-off-by: Michal Simek <monstr@monstr.eu>
* | | Revert "GCC4.6: Convert various empty macros to inline functions"Wolfgang Denk2011-10-04-9/+6
|/ / | | | | | | | | | | | | | | | | | | | | | | This reverts commit 60ce53cf9f408d9ad721f8e7a87d6a564e6d5bac. The commit causes build breakage for a number of boards. This results from the fact that now the arguments of debug() actually get referenced (even if there is hope that the compiler will optimize away the debug() call). The obvious fix to that probem (change the code to always declare the referenced variables and data structures) increases the code size, and was this rejected. So it was decided to revert this commit until a better solution is found.
* | GCC4.6: Squash warning in lzo1x_decompress.cMarek Vasut2011-10-01-2/+1
| | | | | | | | | | | | | | | | | | lzo1x_decompress.c: In function ‘parse_header’: lzo1x_decompress.c:35:5: warning: variable ‘level’ set but not used [-Wunused-but-set-variable] Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Acked-by: Mike Frysinger <vapier@gentoo.org>
* | GCC4.6: Squash warning in cmd_ubi.c:Marek Vasut2011-10-01-2/+1
| | | | | | | | | | | | | | | | | | cmd_ubi.c: In function ‘ubi_volume_read’: cmd_ubi.c:319:9: warning: variable ‘count_save’ set but not used [-Wunused-but-set-variable] Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Acked-by: Mike Frysinger <vapier@gentoo.org>
* | GCC4.6: Squash warning in vmt.cMarek Vasut2011-10-01-4/+7
| | | | | | | | | | | | | | | | | | vmt.c: In function ‘ubi_free_volume’: vmt.c:681:6: warning: variable ‘err’ set but not used [-Wunused-but-set-variable] Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Acked-by: Mike Frysinger <vapier@gentoo.org>
* | GCC4,6: Squash warning in cmd_nand.cMarek Vasut2011-10-01-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | cmd_nand.c: In function ‘do_nand’: cmd_nand.c:490:7: warning: variable ‘chip’ set but not used [-Wunused-but-set-variable] cmd_nand.c:489:7: warning: variable ‘part’ set but not used [-Wunused-but-set-variable] Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Scott Wood <scottwood@freescale.com> Acked-by: Mike Frysinger <vapier@gentoo.org>
* | GCC4.6: Squash warning in nand_bbt.cMarek Vasut2011-10-01-4/+1
| | | | | | | | | | | | | | | | | | nand_bbt.c: In function ‘search_bbt’: nand_bbt.c:465:6: warning: variable ‘bits’ set but not used [-Wunused-but-set-variable] Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Scott Wood <scottwood@freescale.com>
* | GCC4.6: Squash warning in cmd_mem.cMarek Vasut2011-10-01-4/+4
| | | | | | | | | | | | | | | | | | | | | | cmd_mem.c: In function ‘do_mem_loop’: cmd_mem.c:474:25: warning: variable ‘junk’ set but not used [-Wunused-but-set-variable] The assigned variable can be removed because the pointers are volatile so accesses to their addresses are always generated. Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
* | GCC4.6: Squash warnings in ipu_disp.cMarek Vasut2011-10-01-57/+48
| | | | | | | | | | | | | | | | | | | | | | | | ipu_disp.c: In function ‘ipu_disp_set_global_alpha’: ipu_disp.c:1237:11: warning: variable ‘flow’ set but not used [-Wunused-but-set-variable] ipu_disp.c: In function ‘ipu_disp_set_color_key’: ipu_disp.c:1302:16: warning: variable ‘flow’ set but not used [-Wunused-but-set-variable] Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Stefano Babic <sbabic@denx.de>
* | GCC4.6: Squash warnings in lcd.cMarek Vasut2011-10-01-4/+5
| | | | | | | | | | | | | | | | | | | | | | lcd.c: In function ‘lcd_drawchars’: lcd.c:214:9: warning: variable ‘off’ set but not used [-Wunused-but-set-variable] lcd.c: In function ‘lcd_display_bitmap’: lcd.c:617:16: warning: variable ‘compression’ set but not used [-Wunused-but-set-variable] Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
* | GCC4.6: Squash warning in cmd_nvedit.cMarek Vasut2011-10-01-2/+1
| | | | | | | | | | | | | | | | cmd_nvedit.c: In function ‘do_env_edit’: cmd_nvedit.c:463:6: warning: variable ‘len’ set but not used [-Wunused-but-set-variable] Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
* | GCC4.6: Squash warning in cmd_flash.cMarek Vasut2011-10-01-4/+6
| | | | | | | | | | | | | | | | cmd_flash.c: In function ‘do_protect’: cmd_flash.c:474:6: warning: variable ‘p’ set but not used [-Wunused-but-set-variable] Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
* | GCC4.6: Convert various empty macros to inline functionsMarek Vasut2011-10-01-6/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the following gcc4.6 problems: cmd_date.c: In function ‘do_date’: cmd_date.c:50:6: warning: variable ‘old_bus’ set but not used [-Wunused-but-set-variable] asix.c: In function ‘asix_init’: asix.c:317:6: warning: variable ‘rx_ctl’ set but not used [-Wunused-but-set-variable] usb.c: In function ‘usb_parse_config’: usb.c:331:17: warning: variable ‘ch’ set but not used [-Wunused-but-set-variable] usb.c: In function ‘usb_hub_port_connect_change’: usb.c:1123:29: warning: variable ‘portchange’ set but not used [-Wunused-but-set-variable] usb.c: In function ‘usb_hub_configure’: usb.c:1183:25: warning: variable ‘hubsts’ set but not used [-Wunused-but-set-variable] usb_storage.c: In function ‘usb_stor_CB_reset’: usb_storage.c:466:6: warning: variable ‘result’ set but not used [-Wunused-but-set-variable] Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
* | sbc82xx: delete support for obsolete SBC8240/SBC8260Paul Gortmaker2011-10-01-3123/+4
| | | | | | | | | | | | | | | | | | | | The EST SBC8260 is over 10 years old, and the SBC8240 older than that. With the tiny amount of RAM (by today's standards), there really isn't anyone interested in running the latest U-boot on these EOL products anymore. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> CC: jon.diekema@smiths-aerospace.com
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