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| * rk3399: Reserve space for ARM Trust FirmwareKever Yang2016-07-31-1/+2
| | | | | | | | | | | | | | RK3399 needs reserve 0x200000 at the beginning of DRAM, for ATF bl31. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: rk3036: update MAINTAINER fileXu Ziyuan2016-07-31-4/+4
| | | | | | | | | | | | | | Update MAINTAINER files for kylin_rk3036, evb_rk3036. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * configs: rockchip: remove no use MACROKever Yang2016-07-31-8/+0
| | | | | | | | | | | | | | | | The CONFIG_ROCKCHIP_COMMON and CONFIG_SPL_ROCKCHIP_COMMON are no use now, remove them. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * mmc-uclass: correct the device numberKever Yang2016-07-31-3/+9
| | | | | | | | | | | | | | | | | | Not like the mmc-legacy which the devnum starts from 1, it starts from 0 in mmc-uclass, so the device number should be (devnum + 1) in get_mmc_num(). Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* | sunxi: Re-enable h3 emac supportHans de Goede2016-07-31-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | With the recent bug fixes for the sun8i_emac driver all known issues are resolved, so we can re-enable the driver. While at it, also enable the emac on the Orange Pi One. Cc: Chen-Yu Tsai <wens@csie.org> Cc: Corentin LABBE <clabbe.montjoie@gmail.com> Cc: Amit Singh Tomar <amittomer25@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Acked-by: Jagan Teki <jteki@openedev.com>
* | net: sun8i_emac: Fix DMA alignment issues with the rx / tx buffersHans de Goede2016-07-31-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes the following CACHE warnings when using sun8i_emac: => dhcp BOOTP broadcast 1 BOOTP broadcast 2 CACHE: Misaligned operation at range [7bf594a8, 7bf59628] BOOTP broadcast 3 CACHE: Misaligned operation at range [7bf59c90, 7bf59e10] CACHE: Misaligned operation at range [7bf5a478, 7bf5a5f8] DHCP client bound to address 10.42.43.80 (1009 ms) Note this commit also changes the max rx size from 2024 to 2044, matching what the kernel driver uses. Cc: Chen-Yu Tsai <wens@csie.org> Cc: Corentin LABBE <clabbe.montjoie@gmail.com> Cc: Amit Singh Tomar <amittomer25@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sunxi: On newer SoCs use words 1-3 instead of just word 3 from the SIDHans de Goede2016-07-31-1/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It seems that bytes 13-14 of the SID / bytes 1-2 from word 3 of the SID are always 0 on H3 making it a poor candidate to use as source for the serialnr / mac-address, and the other non constant words (1 and 2) also have quite a few bits which are the same for some boards, This commits switches to using the crc32 of words 1 - 3 to get a more unique value for the mac-address / serialnr. Cc: Chen-Yu Tsai <wens@csie.org> Cc: Corentin LABBE <clabbe.montjoie@gmail.com> Cc: Amit Singh Tomar <amittomer25@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sunxi: Ensure that the NIC specific bytes of the mac are not all 0Hans de Goede2016-07-31-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | On 2 of my H3 boards bytes 13-15 of the SID are all 0 leading to the NIC specific bytes of the mac all being 0, which leads to the boards not getting an ipv6 address from the dhcp server. This commits adds a check to ensure this does not happen. Cc: Chen-Yu Tsai <wens@csie.org> Cc: Corentin LABBE <clabbe.montjoie@gmail.com> Cc: Amit Singh Tomar <amittomer25@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sunxi: Hummingbird_A31_defconfig: Drop MACPWR optionChen-Yu Tsai2016-07-31-1/+1
| | | | | | | | | | | | | | | | | | | | MACPWR was used to bring the Ethernet PHY out of reset. The designware driver now supports the phy reset gpio binding, so this is no longer needed. In fact in requesting the same GPIO, it makes the designware driver fail to probe. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | sunxi: gpio: Add .xlate function for gpio phandle resolutionChen-Yu Tsai2016-07-31-0/+16
|/ | | | | | | | | | | | | sunxi uses a 2 cell phandle for gpio bindings. Also there are no seperate nodes for each pin bank. Add a custom .xlate function to map gpio phandles to the correct pin bank device. This fixes gpio_request_by_name usage. Fixes: 7aa974858422 ("dm: sunxi: Modify the GPIO driver to support driver model") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* m68k: code reformatting for all start.S filesAngelo Dureghello2016-07-30-501/+449
| | | | | | | | | | | | | This patch is style-related only, to reformat all the start.S code, actually not following a coherent style inside single files and between different cpu start.S files. Linux format has been respected, as - max line width at 80 columns - one 8 cols tab between asm instructions and operands - inline comments, where any, fixed at col 41 Signed-off-by: Angelo Dureghello <angelo@sysam.it>
* ARM: am57xx_evm: Enable QSPI supportVignesh R2016-07-30-0/+51
| | | | | | | | | | AM571x IDK and AM572x IDK EVMs have spansion s25fl256s QSPI flash on the board connected to TI QSPI IP over CS0. Therefore enable QSPI support. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* ARM: dts: am57xx-idk-common: Enable support for QSPIVignesh R2016-07-30-0/+49
| | | | | | | | | | | AM571x and AM572x IDK have a spansion s25fl256s QSPI flash on the board connected to TI QSPI over CS0. Hence, add QSPI and flash slave DT nodes. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* configs: am43xx_evm_defconfig: Enable CONFIG_SPI_FLASH_BARVignesh R2016-07-30-0/+1
| | | | | | | | | | AM437x SK and AM437x IDK EVMs have 64MB flash, therefore enable CONFIG_SPI_FLASH_BAR to access flash regions above 16MB. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* ARM: dts: dra7xx: Update spi-max-frequency for QSPIVignesh R2016-07-30-2/+2
| | | | | | | | | | | According to AM572x DM SPRS953A, QSPI max bus speed is 76.8MHz. Therefore update the spi-max-frequency value of QSPI node for DRA74 and DRA72 evm. This increase flash read speed by ~2MB/s. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
* configs: dra7xx: Update QSPI speed to 76.8MHzVignesh R2016-07-30-1/+1
| | | | | | | | | | Now that QSPI driver can support 76.8MHz, update the CONFIG_SF_DEFAULT_SPEED to the same value. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
* spi: ti_qspi: dra7xx: Add support to use 76.8MHz clockVignesh R2016-07-30-5/+12
| | | | | | | | | | According to AM572x DM SPRS953A, QSPI bus speed can be 76.8MHz, update the driver to use the same. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
* ARM: dra7xx: Change DPLL_PER_HS13 divider valueLokesh Vutla2016-07-30-1/+1
| | | | | | | | | | | According to AM572x DM SPRS953A, QSPI bus speed can be 76.8MHz, hence update QSPI input clock divider value (DPLL_PER_HS13) to provide 76.8MHz clock, so that driver can use the same. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* sf: sf_params: Add AT25DF321 flash supportWenyou Yang2016-07-30-1/+2
| | | | | | | | Add AT25DF321 flash support. Fix AT25DF321A device name. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* spi: ti_qspi: Remove delay in read path for dra7xxVignesh R2016-07-30-3/+0
| | | | | | | | | | | | As per commit b545a98f5dc563 ("spi: ti_qspi: Add delay for successful bulk erase) says its added to meet bulk erase timing constraints. But bulk erase is a cmd to flash and delay in read path does not make sense. Morever, testing on DRA74/DRA72 evm has shown that this delay is no longer required. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
* spi: ti_qspi: Fix compiler warning when DEBUG macro is setVignesh R2016-07-30-2/+2
| | | | | | | | | | clk_div is uninitialized at the beginning of ti_spi_set_speed(), move debug() print after clk_div calculation to avoid compiler warning and to have proper value of clk_div printed during debugging. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
* spi: ti_qspi: Fix failure on multiple READ_ID cmdVignesh R2016-07-30-3/+2
| | | | | | | | | | | | | | Populating QSPI_RD_SNGL bit(0x1) in priv->cmd means that value QSPI_INVAL (0x4) is not written to CMD field of QSPI_SPI_CMD_REG in ti_qspi_cs_deactivate(). Therefore CS is never deactivated between successive READ ID which results in sf probe to fail. Fix this by not populating priv->cmd with QSPI_RD_SNGL and OR it wih priv->cmd as required (similar to the convention followed in the driver). Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
* spi: Add support for N25Q016AMoritz Fischer2016-07-30-0/+1
| | | | | | | | This commit adds support in the spi-nor driver for the N25Q016A, a 16Mbit SPI NOR flash from Micron. Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2016-07-28-402/+3882
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| * MAINTAINERS: i.MX: Add board/freescale/*mx* pathFabio Estevam2016-07-28-0/+1
| | | | | | | | | | | | | | | | | | | | | | Pass the board/freescale/*mx*/ path as files maintained by Stefano Babic. While this is not ideal and does not cover all the i.MX board cases, it gives at least a better hint for the /scripts/get_maintainer.pl tool. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
| * mx7dsabresd: MAINTAINERS: Add mx7dsabresd_secure_defconfigFabio Estevam2016-07-28-0/+1
| | | | | | | | | | | | Add an entry for the mx7dsabresd_secure_defconfig target. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
| * mx7_common: initialize generic timer on all CPU'sStefan Agner2016-07-28-0/+1
| | | | | | | | | | | | | | | | | | Use CONFIG_TIMER_CLK_FREQ to let the non-secure init code initialize the generic timer on all CPU's. This allows to make use of the timer freuquency register also on other CPU than the start CPU which is important for KVM. Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
| * mx6ul_14x14_evk: Remove unused defineDiego Dorta2016-07-28-3/+0
| | | | | | | | | | | | | | Remove unused define constant. Signed-off-by: Diego Dorta <diego.dorta@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
| * cgtqmx6eval: Remove uneeded PHYS_SDRAM_SIZEFabio Estevam2016-07-28-1/+0
| | | | | | | | | | | | | | | | | | | | | | cgtqmx6eval uses the imx_ddr_size() function to calculate the DDR size in runtime, so there is no need to define PHYS_SDRAM_SIZE. Remove the unneeded definition. Cc: Otavio Salvador <otavio@ossystems.com.br> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Acked-by: Otavio Salvador <otavio@ossystems.com.br>
| * novena: Remove uneeded PHYS_SDRAM_SIZEFabio Estevam2016-07-28-1/+0
| | | | | | | | | | | | | | | | | | | | | | novena uses the imx_ddr_size() function to calculate the DDR size in runtime, so there is no need to define PHYS_SDRAM_SIZE. Remove the unneeded definition. Cc: Marek Vasut <marex@denx.de> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Acked-by: Marek Vasut <marex@denx.de>
| * bx50v3: Use imx_ddr_size() for calculating the DDR sizeFabio Estevam2016-07-28-3/+1
| | | | | | | | | | | | | | | | | | imx_ddr_size() can be used to calculate the DDR size in runtime. By using this function we no longer need to define PHYS_SDRAM_SIZE. Cc: Martin Donnelly <martin.donnelly@ge.com> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
| * aristainetos: Use imx_ddr_size() for calculating the DDR sizeFabio Estevam2016-07-28-2/+1
| | | | | | | | | | | | | | | | | | | | imx_ddr_size() can be used to calculate the DDR size in runtime. By using this function we no longer need to define PHYS_SDRAM_SIZE. Cc: Heiko Schocher <hs@denx.de> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Acked-by: Heiko Schocher <hs@denx.de>
| * warp: Use imx_ddr_size() for calculating the DDR sizeFabio Estevam2016-07-28-2/+1
| | | | | | | | | | | | | | | | imx_ddr_size() can be used to calculate the DDR size in runtime. By using this function we no longer need to define PHYS_SDRAM_SIZE. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
| * warp7: Move some USB configuration options to defconfigBreno Lima2016-07-28-9/+6
| | | | | | | | | | | | | | | | | | Currently it's recommended to move some configuration options to the defconfig file. Move some USB related options to the defconfig file. Signed-off-by: Breno Lima <breno.lima@nxp.com>
| * colibri_imx7: add Colibri iMX7S/iMX7D module supportStefan Agner2016-07-28-0/+896
| | | | | | | | | | | | | | | | | | | | | | This commit adds support for the Toradex Computer on Modules Colibri iMX7S/iMX7D. The two modules/SoC's are very similar hence can be easily supported by one board. The board code detects RAM size at runtime which is one of the differences between the two boards. The board also uses the UART's in DTE mode, hence making use of the new DTE support via serial DM. Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
| * cgtqmx6eval: Replace is_mx6q() for macroBreno Lima2016-07-28-11/+3
| | | | | | | | | | | | | | | | It's not necessary to implement the is_mx6q function, there is a macro in sys_proto.h already implemented. Signed-off-by: Breno Lima <breno.lima@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
| * mx6cuboxi: Replace is_mx6q() for macroBreno Lima2016-07-28-10/+2
| | | | | | | | | | | | | | | | It's not necessary to implement the is_mx6q function, there is a macro in sys_proto.h already implemented. Signed-off-by: Breno Lima <breno.lima@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
| * wandboard: Replace is_cpu_type() for macroBreno Lima2016-07-28-2/+2
| | | | | | | | | | | | | | | | It's not necessary to use the is_cpu_type function, there is a macro in sys_proto.h already implemented. Signed-off-by: Breno Lima <breno.lima@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
| * imx: ventana: add dt fixup for watchdog external resetTim Harvey2016-07-28-0/+30
| | | | | | | | | | | | | | | | | | | | | | Added removal of the fsl,ext-reset-output property in the wdog node for board revisions that pre-date the addition of the external watchdog reset signal. This property is a recent addition to mainline linux kernel in order to specify that the IMX watchdog external reset should be used instead of the internal chip-level reset. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * imx: ventana: refactor board-specific dt fixups (no functional change)Tim Harvey2016-07-28-73/+93
| | | | | | | | | | | | | | | | | | | | | | | | Re-factor the board-specific dt fixups so that they are easier to follow and extend in the future: - use defines for DT paths - use switch/case per board - order models numerically There is no functional change in the code Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * imx: ventana: make hwconfig initialize based on board configurationTim Harvey2016-07-28-5/+16
| | | | | | | | | | | | | | | | | | | | The hwconfig env var allows user to control hardware specific configuration of board specific features but not all Ventana boards have the same features. We will use the magic default value of "_UNKNOWN_" to signify that the bootloader should create this based on detected board model. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * imx: ventana: add extra DIO's for GW5520Tim Harvey2016-07-28-0/+36
| | | | | | | | | | | | | | The GW5520 has 10 DIO's instead of the typical 4 found on the Ventana product family. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * imx: ventana: make number of digital I/O's dynamicTim Harvey2016-07-28-210/+199
| | | | | | | | | | | | Replace the static list of board-specific digital I/O's with a dynamic list. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * imx: ventana: make RS232 enable board specificTim Harvey2016-07-28-9/+27
| | | | | | | | | | | | Not all Ventana boards have an RS232 transceiver, make it board specific. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * imx: ventana: re-enable late board info displayTim Harvey2016-07-28-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | 3b1f681131149b5f62602f582a7e60b0185a2a49 caused a regression that removes board info dispaly for Gateworks Ventana boards because it made the invalid assumption that CONFIG_DISPLAY_BOARDINFO_LATE was the same thing as CONFIG_DISPLAY_BOARDINFO. Ventana needs to call show_board_info in late init because we need to have the i2c eeprom based model info. Re-define CONFIG_DISPLAY_BOARDINFO_LATE to allow that to happen. Cc: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * imx: ventana: default pci to disabledTim Harvey2016-07-28-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The IMX6 PCIe host controller does not have a proper reset and as such there are several issues that can arise if PCI is enabled in the bootloader follwed by Linux trying to re-configure LTSSM and/or toggling PERST# to the devices. For now, the best approach seems to default to disabling PCI by defaulting pciedisable=1. This can be overridden by the user if they need PCI in the bootloader, for example: - GW552x needing ethernet access in bootloader - GW16082 expansion board needing a device-tree fixup for irq mapping Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * pci: allow disabling of pci init/enum via envTim Harvey2016-07-28-0/+4
| | | | | | | | Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * imx: ventana: add dt fixup for eth1 mac-addressTim Harvey2016-07-28-0/+35
| | | | | | | | | | | | | | Ventana boards with a PCI Marvell Sky2 GigE MAC require the MAC address to be placed in a DT node in order for the mainline linux driver to obtain it. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * imx: ventana: add dt fixup for GW16082 irq mappingTim Harvey2016-07-28-0/+228
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The GW16082 mini-PCI expansion mezzanine uses a TI XIO2001 PCIe-to-PCI bridge with legacy INTA/B/C/D interrupts. These interrupts are assigned in the reverse order according to the PCI spec. If the TI bridge is found on the Ventana PCI bus, add device-tree nodes according to bus enumeration explicitly defining the interrupt mapping to override the default PCI mapping in the Linux kernel. This allows the GW16082 to work with upstream kernels that support device-tree irq parsing. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * mx7dsabresd_secure_defconfig: Use CONFIG_ARMV7_BOOT_SEC_DEFAULTFabio Estevam2016-07-28-10/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no need for introducing MX7_SEC, as there is the CONFIG_ARMV7_BOOT_SEC_DEFAULT option for this purpose. Switch to CONFIG_ARMV7_BOOT_SEC_DEFAULT and get rid of MX7_SEC. Tested by booting a 4.1.15 NXP kernel with mx7dsabresd_secure_defconfig target. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Acked-by: Stefan Agner <stefan.agner@toradex.com>
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