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* i2c: mvtwsi: Add documentationmario.six@gdsys.cc2016-07-26-19/+144
| | | | | | | Add full documentation to all driver functions. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Stefan Roese <sr@denx.de>
* i2c: mvtwsi: Make delay times frequency-dependentmario.six@gdsys.cc2016-07-26-42/+85
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some devices using the MVTWSI driver have the option to run at speeds faster than Standard Mode (100kHZ). On the Armada 38x controllers, this is actually necessary, since due to erratum FE-8471889, a timing violation concerning repeated starts prevents the controller from working correctly in Standard Mode. One of the workarounds recommended in the erratum is to set the bus to Fast Mode (400kHZ) operation and ensure all connected devices are set to Fast Mode. In the current version of the driver, however, the delay times are hard-coded to 10ms, corresponding to Standard Mode operation. To take full advantage of the faster modes, we would need to either keep the currently configured I2C speed in a globally accessible variable, or pass it to the necessary functions as a parameter. For DM, the first option is not a problem, and we can simply keep the speed in the private data of the driver. For the legacy interface, however, we would need to introduce a static variable, which would cause problems with boots from NOR flashes; see commit d6b7757 "i2c: mvtwsi: Eliminate twsi_control_flags." As to not clutter the interface with yet another parameter, we therefore keep the default 10ms delays for the legacy functions. In DM mode, we make the delay time dependant on the frequency to allow taking full advantage of faster modes of operation (tested with up to 1MHZ frequency on Armada MV88F6820). Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Stefan Roese <sr@denx.de>
* i2c: mvtwsi: Handle zero-length offsets properlymario.six@gdsys.cc2016-07-26-8/+13
| | | | | | | | | | | | | Zero-length offsets are not properly handled by the driver. When a read operation with a zero-length offset is started, a START condition is asserted, and since no offset bytes are transferred, a repeated START is issued immediately after, which confuses the controller. To fix this, we send the first START only if any address bytes need to be sent, and keep track of the expected start status accordingly. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Stefan Roese <sr@denx.de>
* i2c: mvtwsi: Add compatibility to DMmario.six@gdsys.cc2016-07-26-1/+117
| | | | | | | | | | | | | | | | | This patch adds the necessary functions and Kconfig entry to make the MVTWSI I2C driver compatible with the driver model. A possible device tree entry might look like this: i2c@11100 { compatible = "marvell,mv64xxx-i2c"; reg = <0x11000 0x20>; clock-frequency = <100000>; u-boot,i2c-slave-addr = <0x0>; }; Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Stefan Roese <sr@denx.de>
* i2c: mvtwsi: Make address length variablemario.six@gdsys.cc2016-07-26-9/+21
| | | | | | | | | | | | | The length of the address parameter of the __twsi_i2c_read and __twsi_i2c_write functions is fixed to four bytes. As a final step in the preparation of the DM conversion, we make the length of this parameter variable by turning it into an array of bytes, and convert the 32 bit value that's passed to the legacy functions into a four-byte-array on the fly. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Stefan Roese <sr@denx.de>
* i2c: mvtwsi: Factor out adap parametermario.six@gdsys.cc2016-07-26-51/+46
| | | | | | | | | To be able to use the compatibility layer from the DM functions, we factor the adap parameter out of all functions, and pass the actual register base instead. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Stefan Roese <sr@denx.de>
* i2c: mvtwsi: Add compatibility functionsmario.six@gdsys.cc2016-07-26-9/+38
| | | | | | | | To prepare for the DM conversion, we add a layer of compatibility functions to be used by both the legacy and the DM functions. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Stefan Roese <sr@denx.de>
* i2c: mvtwsi: Use 'uint' instead of 'unsigned int'mario.six@gdsys.cc2016-07-26-5/+5
| | | | | | | | | | Since some additional parameters will be added in the course of this patch series (especially with the addition of DM support), we replace the longer "unsigned int" declarations with "uint" declarations to keep the parameter lists more readable. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Stefan Roese <sr@denx.de>
* i2c: mvtwsi: Get rid of status parametermario.six@gdsys.cc2016-07-26-13/+13
| | | | | | | | | | | | | | | | | | | | The twsi_stop function contains a parameter "status," which is used to pass in the current exit status of the function calling twsi_stop, and either return this status unchanged if it indicates an error, or return twsi_stop's exit status if it does not indicate an error. While not massively complicated, this adds another purpose to the twsi_stop function, which should have the sole purpose of asserting a STOP condition on the bus (and not manage the exit status of its caller). Therefore, we move the exit status management into the caller functions by introducing a "stop_status" variable and returning either the status before the twsi_stop call (kept in the "status" variable), or the status from the twsi_stop call, depending on which indicates an error. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Stefan Roese <sr@denx.de>
* i2c: mvtwsi: Eliminate flags parametermario.six@gdsys.cc2016-07-26-42/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Due to breaking boots from NOR flashes, commit d6b7757 ("i2c: mvtwsi: Eliminate twsi_control_flags") removed the static global twsi_control_flags variable, which kept a set of default flags that were always or'd to the control register when writing. It was replaced with a flags parameter, which was passed around between the functions that needed it. Since the twsi_control_flags variable was used just for the purposes of a) setting the MVTWSI_CONTROL_TWSIEN on every control register write, and b) setting the MVTWSI_CONTROL_ACK from twsi_i2c_read if needed, anyway, the added overhead of another variable being passed around is no longer justified, and we are better off implementing this flag setting logic locally in the functions that actually write to the control register. Therefore, this patch sets MVTWSI_CONTROL_TWSIEN on every control register write, replaces the twsi_i2c_read's flags parameter with a ack_flag parameter, which tells the function whether to acknowledge the read or not, and removes every other instance of the flags variable. This has the added benefit that now every notion of "global default flags" is gone, and it's much easier to see which control flags are actually set at which point in time. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Stefan Roese <sr@denx.de>
* i2c: mvtwsi: Improve and fix commentsmario.six@gdsys.cc2016-07-26-67/+62
| | | | | | | | This patch fixes only comments/documentation: Streamline capitalization and improve grammar/punctuation. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Stefan Roese <sr@denx.de>
* i2c: mvtwsi: Streamline code and add documentationmario.six@gdsys.cc2016-07-26-38/+75
| | | | | | | | | Convert groups of logically connected preprocessor defines into proper enums, one macro into an inline function, and add documentation to/extend existing documentation of these items. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Stefan Roese <sr@denx.de>
* i2c: mvtwsi: Fix style violationsmario.six@gdsys.cc2016-07-26-8/+8
| | | | | | | | This patch fixes seven style violations: Six superfluous spaces after casts, and one logical continuation violation. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Stefan Roese <sr@denx.de>
* defconfig: am57xx_hs_evm: enable i2c driver modelMugunthan V N2016-07-26-0/+1
| | | | | | | Enable i2c driver model for am57xx_hs_evm as omap i2c supports driver model. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
* defconfig: am57xx_evm: enable i2c driver modelMugunthan V N2016-07-26-0/+1
| | | | | | | | Enable i2c driver model for am57xx_evm as omap i2c supports driver model. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* defconfig: dra7xx_hs_evm: enable i2c driver modelMugunthan V N2016-07-26-0/+1
| | | | | | | | Enable i2c driver model for dra7xx_hs_evm as omap i2c supports driver model. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* defconfig: dra7xx_evm: enable i2c driver modelMugunthan V N2016-07-26-0/+1
| | | | | | | | Enable i2c driver model for dra7xx_evm as omap i2c supports driver model. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* defconfig: am43xx_hs_evm: enable i2c driver modelMugunthan V N2016-07-26-0/+1
| | | | | | | | Enable i2c driver model for am43xx_hs_evm as omap i2c supports driver model. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* defconfig: am43xx_evm: enable i2c driver modelMugunthan V N2016-07-26-0/+1
| | | | | | | | Enable i2c driver model for am43xx_evm as omap i2c supports driver model. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* defconfig: am335x_evm: enable i2c driver modelMugunthan V N2016-07-26-0/+1
| | | | | | | | Enable i2c driver model for am335x_evm as omap i2c supports driver model. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* defconfig: am335x_boneblack_vboot: enable i2c driver modelMugunthan V N2016-07-26-0/+9
| | | | | | | | | Enable i2c driver model for am335x_boneblack_vboot as omap i2c supports driver model. Also enable CONFIG_DM_I2C_COMPAT for legacy drivers of i2c devices. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* drivers: i2c: omap24xx_i2c: adopt omap_i2c driver to driver modelMugunthan V N2016-07-26-0/+99
| | | | | | | Convert omap i2c driver to adopt i2c driver model Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* drivers: i2c: omap24xx_i2c: prepare driver for DM conversionMugunthan V N2016-07-26-133/+175
| | | | | | | Prepare the driver for DM conversion. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* ti_armv7_common: i2c: do not define DM_I2C for splMugunthan V N2016-07-26-0/+8
| | | | | | | | Since omap's spl doesn't support DM currently, do not define DM_I2C for spl build. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* drivers: i2c: uclass: parse dt parameters only when CONFIG_OF_CONTROL is enableMugunthan V N2016-07-26-0/+14
| | | | | | | | parse dt parameter of i2c devices only when CONFIG_OF_CONTROL is enabled. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* omap5/dra7: i2c: correct register offset for sync registerMugunthan V N2016-07-26-3/+3
| | | | | | | | | | | | The register offset of i2c_sysc offset is not correct as per omap5[1]/dra7[2] TRM, correct the offsets as per the documentation. [1] - http://www.ti.com/lit/pdf/swpu249 [2] - http://www.ti.com/lit/pdf/spruhz6 Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* omap4: i2c: correct register offset for sync registerMugunthan V N2016-07-26-3/+3
| | | | | | | | | | The register offset of i2c_sysc offset is not correct as per omap4 TRM [1], correct the offsets as per the documentation. [1] - http://www.ti.com/lit/ug/swpu235ab/swpu235ab.pdf Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* tools: env: Fix format warnings in debugMarcin Niestroj2016-07-26-7/+10
| | | | | | | | | | Format warnings (-Wformat) were shown in printf() calls after defining DEBUG macro. Update format string and explicitly cast variables to suppress all warnings. Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
* Prepare v2016.09-rc1Tom Rini2016-07-25-2/+2
| | | | Signed-off-by: Tom Rini <trini@konsulko.com>
* sandbox: Migrate CONFIG_I2C_EEPROMTom Rini2016-07-25-1/+1
| | | | | | | | | Most users of CONFIG_I2C_EEPROM were migrated to defconfig a while ago, but sandbox was skipped. Leave it off for sandbox_spl where it does not build, but does not need to be either. Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge git://git.denx.de/u-boot-nand-flashTom Rini2016-07-25-13/+2057
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| * mtd: fix compiler warningsSteve Rae2016-07-24-2/+7
| | | | | | | | | | | | | | - add missing declaration - update debug output format specifiers Signed-off-by: Steve Rae <steve.rae@raedomain.com>
| * mtd: nand: fix bug writing 1 byte less than page sizeHector Palacios2016-07-24-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | nand_do_write_ops() determines if it is writing a partial page with the formula: part_pagewr = (column || writelen < (mtd->writesize - 1)) When 'writelen' is exactly 1 byte less than the NAND page size the formula equates to zero, so the code doesn't process it as a partial write, although it should. As a consequence the function remains in the while(1) loop with 'writelen' becoming 0xffffffff and iterating until the watchdog timeout triggers. To reproduce the issue on a NAND with 2K page (0x800): => nand erase.part <partition> => nand write $loadaddr <partition> 7ff Signed-off-by: Hector Palacios <hector.palacios@digi.com>
| * sunxi: Enable NAND controller on the CHIPBoris Brezillon2016-07-24-0/+44
| | | | | | | | | | | | | | Enable the NAND controller in the sun5i-r8-chip.dts. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: nand: Increase CONFIG_SYS_NAND_MAX_ECCPOS valueBoris Brezillon2016-07-24-0/+1
| | | | | | | | | | | | | | On some sunxi boards we have NANDs exposing 1664 OOB bytes per page. Define the CONFIG_SYS_NAND_MAX_ECCPOS value accordingly. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
| * mtd: nand: Increase the max OOB sizeBoris Brezillon2016-07-24-1/+1
| | | | | | | | | | | | | | Some NANDs are now exposing 1664 OOB bytes per page. Adjust the NAND_MAX_OOBSIZE value accordingly. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
| * mtd: nand: Add a full-id entry for the H27QCG8T2E5R‐BCF NANDBoris Brezillon2016-07-24-0/+4
| | | | | | | | | | | | | | Add a full-id entry for the H27QCG8T2E5R‐BCF NAND. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Hans de Goede <hdegoede@redhat.com>
| * sun5i: Add NAND controller to the sun5i DTSIMaxime Ripard2016-07-24-0/+49
| | | | | | | | | | | | | | Add the NAND controller definition to sun5i.dtsi. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
| * mtd: nand: Add the sunxi NAND controller driverBoris Brezillon2016-07-24-4/+1862
| | | | | | | | | | | | | | | | | | | | | | We already have an SPL driver for the sunxi NAND controller, now add the normal/standard one. The source has been copied from Linux 4.6 with a few changes to make it work in u-boot. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Hans de Goede <hdegoede@redhat.com>
| * mtd: nand: add common DT init codeBrian Norris2016-07-24-0/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These are already-documented common bindings for NAND chips. Let's handle them in nand_base. If NAND controller drivers need to act on this data before bringing up the NAND chip (e.g., fill out ECC callback functions, change HW modes, etc.), then they can do so between calling nand_scan_ident() and nand_scan_tail(). The original commit has been slightly reworked to use the fdtdec_xxx() helpers (instead of the of_xxxx() ones). Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: Add missing macros to configure the NAND controller clkBoris Brezillon2016-07-24-0/+5
| | | | | | | | | | | | | | We need some macros to manipulate the NAND controller clock. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Hans de Goede <hdegoede@redhat.com>
| * cmd, nand: add an option to disable the verification when writing in raw modeBoris Brezillon2016-07-24-5/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Modern NANDs do not guarantee that data written in raw mode will not contain bitflips just after writing them. This is fine since the number of bitflips should be rather low and thus fixable by the ECC engine, but since we are reading data in raw mode to verify if they match the input data we cannot prevent failures if some bits are flipped. The option of using standard mode to verify the data is not acceptable either, since one of the usage of raw mode is to allow flashing images that do not respect the standard NAND page layout or the default ECC config (this is the case on Allwinner platforms, where the ROM code tests several hardcoded configs, which are not necessarily matching the NAND characteristics). Add an extension to the nand write.raw command allowing one to disable the verification step. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | arm64: thunderx_88xx_defconfig: remove unneeded CONFIG_SYS_EXTRA_OPTIONSMasahiro Yamada2016-07-25-1/+0
| | | | | | | | | | | | | | | | ARM64 is correctly select'ed in arch/arm/Kconfig, so this line in the defconfig is unneeded. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | dtoc: Correct the type widening code in fdt_fallbackSimon Glass2016-07-25-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | This code does not match the fdt version in fdt.py. When dtoc is unable to use the Python libfdt library, it uses the fallback version, which does not widen arrays correctly. Fix this to avoid a warning 'excess elements in array initialize' in dt-platdata.c which happens on some platforms. Reported-by: Tom Rini <trini@konsulko.com> Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Tom Rini <trini@konsulko.com>
* | hashtable: Fix compiler warning on 32-bit sandboxSimon Glass2016-07-25-5/+5
| | | | | | | | | | | | | | This fixes a mismatch between the %zu format and the type used on sandbox. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* | part_efi: Fix compiler warning on 32-bit sandboxSimon Glass2016-07-25-5/+5
| | | | | | | | | | | | | | This fixes a mismatch between the %zu format and the type used on sandbox. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* | lzmadec: Use the same type as the lzma callSimon Glass2016-07-25-2/+3
| | | | | | | | | | | | | | | | With sandbox on 32-bit the size_t type can be a little inconsistent. Use the same type as the caller expects to avoid a compiler warning. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* | sandbox: Add instructions about building on 32-bit machinesSimon Glass2016-07-25-1/+7
| | | | | | | | | | | | | | | | Sandbox is built with 64-bit ints by default. This doesn't work properly on 32-bit machines. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* | tools, rsa: Further minor cleanups on top of c236ebd and 2b9ec7mario.six@gdsys.cc2016-07-25-5/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [NOTE: I took v1 of these patches in, and then v2 came out, this commit is squashing the minor deltas from v1 -> v2 of updates to c236ebd and 2b9ec76 into this commit - trini] - Added an additional NULL check, as suggested by Simon Glass to fit_image_process_sig - Re-formatted the comment blocks Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Simon Glass <sjg@chromium.org> [For merging the chnages from v2 back onto v1] Signed-off-by: Tom Rini <trini@konsulko.com>
* | ARM: am33xx: Always inhibit init/refresh during DDR phy initRuss Dill2016-07-25-12/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A couple of commits have modified the am33xx/am437x ddr2/ddr3 initialization path to fix certain issues, but have had the side effect of causing L3 noc errors during initialization. The two commits are: 69b918 "am33xx,ddr3: fix ddr3 sdram configuration" fc46ba "arm: am437x: Enable hardware leveling for EMIF" The EMIF_REG_INITREF_DIS_MASK bit still needs to be set for all platforms. This delays initialization and refresh until a later stage. The 500us timer can be programmed for platforms that require it and for platforms that don't require it. It is currently hardcoded for 400MHz systems. For systems with a higher memory frequency this needs to be a larger value, and for systems with a lower memory frequency this can be a lower value. This can be considered a separate issue and corrected in a later commit. Signed-off-by: Russ Dill <Russ.Dill@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
generated by cgit v1.1 at 2024-11-10 04:47:49 +0000