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* | Convert CONFIG_SPL_HASH_SUPPORT to KconfigSimon Glass2016-09-16-2/+2
| | | | | | | | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Convert CONFIG_SPL_CRYPTO_SUPPORT to KconfigSimon Glass2016-09-16-2/+2
| | | | | | | | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* | spear: Use upper case for CONFIG optionsSimon Glass2016-09-16-34/+29
| | | | | | | | | | | | | | | | | | There are a few options which use lower case. We should use upper case for all CONFIG options. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Add usbtty/nand hunk to include/configs/spear3xx_evb.h] Signed-off-by: Tom Rini <trini@konsulko.com>
* | Move existing use of CONFIG_SPL_RSA to KconfigSimon Glass2016-09-16-2/+51
| | | | | | | | | | | | | | A few boards define this in a header file which is incorrect. It means that Kconfig options that rely on this cannot be used. Move it. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Move existing use of CONFIG_SPL_DM to KconfigSimon Glass2016-09-16-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A few boards define this in a header file which is incorrect. It means that Kconfig options that rely on this cannot be used. Move it. Note that quite a few boards defined this options but do not appear to actually use SPL: BSC9132QDS_NOR_DDRCLK100_SECURE BSC9132QDS_NOR_DDRCLK133_SECURE BSC9132QDS_SDCARD_DDRCLK100_SECURE BSC9132QDS_SDCARD_DDRCLK133_SECURE BSC9132QDS_SPIFLASH_DDRCLK100_SECURE BSC9132QDS_SPIFLASH_DDRCLK133_SECURE C29XPCIE_NOR_SECBOOT P1010RDB-PA_36BIT_NAND_SECBOOT P1010RDB-PA_36BIT_SPIFLASH_SECBOOT P1010RDB-PA_NAND_SECBOOT P1010RDB-PA_NOR_SECBOOT P1010RDB-PB_36BIT_NOR_SECBOOT P1010RDB-PB_36BIT_SPIFLASH_SECBOOT P1010RDB-PB_NAND_SECBOOT P1010RDB-PB_NOR_SECBOOT P3041DS_SECURE_BOOT P4080DS_SECURE_BOOT P5020DS_NAND_SECURE_BOOT P5040DS_SECURE_BOOT T1023RDB_SECURE_BOOT T1024QDS_DDR4_SECURE_BOOT T1024QDS_SECURE_BOOT T1024RDB_SECURE_BOOT T1040RDB_SECURE_BOOT T1042D4RDB_SECURE_BOOT T1042RDB_SECURE_BOOT T2080QDS_SECURE_BOOT T2080RDB_SECURE_BOOT T4160QDS_SECURE_BOOT T4240QDS_SECURE_BOOT ls1021aqds_nor_SECURE_BOOT ls1021atwr_nor_SECURE_BOOT ls1043ardb_SECURE_BOOT For these boards CONFIG_SPL_DM will no-longer be defined in SPL. But since they apparently don't have an SPL, this should not matter. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Kconfig: tpl: Add some TPL support options to KconfigSimon Glass2016-09-16-0/+67
| | | | | | | | | | | | | | Some of the SPL options have TPL equivalents. Add these to Kconfig so that we can convert these options over to work from Kconfig. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Kconfig: spl: Add SPL support options to KconfigSimon Glass2016-09-16-52/+411
| | | | | | | | | | | | | | | | There are a lot of SPL options in U-Boot to enable various features and drivers. Currently these do not use Kconfig. Add them to Kconfig along with suitable help, and drop them from the README. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Use separate options for TPL supportSimon Glass2016-09-16-40/+80
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present TPL uses the same options as SPL support. In a few cases the board config enables or disables the SPL options depending on whether CONFIG_TPL_BUILD is defined. With the move to Kconfig, options are determined for the whole build and (without a hack like an #undef in a header file) cannot be controlled in this way. Create new TPL options for these and update users. This will allow Kconfig conversion to proceed for these boards. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Drop CONFIG_SPL_RAM_SUPPORTSimon Glass2016-09-16-1/+0
| | | | | | | | | | | | This option does not exist in U-Boot. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
* | arm: fsl: Adjust ordering of #ifndef CONFIG_SPL_BUILDSimon Glass2016-09-16-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | The secure boot header files incorrectly define SPL options only if CONFIG_SPL_BUILD is defined. This means that the options are only enabled in an SPL build, and not with a normal 'make xxx_defconfig'. This means that moveconfig.py cannot work, since it sees the options as disabled even when they may be manually enabled in an SPL build. Fix this by changing the order. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Kconfig: Move SPL settings into their own fileSimon Glass2016-09-16-464/+465
| | | | | | | | | | | | Move the SPL settings into common/spl where most of the SPL code is kept. Signed-off-by: Simon Glass <sjg@chromium.org>
* | moveconfig: Add an option to commit changesSimon Glass2016-09-16-0/+18
| | | | | | | | | | | | | | | | | | | | | | The moveconfig tool is quite clever and generally produces results that are suitable for sending as a patch without further work. The main required step is to add the changes to a commit. Add an option to do this automatically. This allows moveconfig to be used from a script to convert multiple CONFIG options, once per commit. Signed-off-by: Simon Glass <sjg@chromium.org>
* | moveconfig: Add an option to skip promptsSimon Glass2016-09-16-14/+23
| | | | | | | | | | | | | | | | At present it is not easy to use moveconfig from a script since it asks for user input a few times. Add a -y option to skip this and assume that 'y' was entered. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Correct defconfigs using savedefconfigSimon Glass2016-09-16-1/+3
| | | | | | | | | | | | | | | | | | Update the defconfig files to match their canonical form, as produced by 'make safedefconfig'. This is the result of running 'tools/moveconfig.py -s' on the tree. Signed-off-by: Simon Glass <sjg@chromium.org>
* | i2c: at91_i2c: Fix the wrong include fileWenyou Yang2016-09-13-1/+1
| | | | | | | | | | | | | | Since the 'clk_client.h' doesn't exist, it should be 'clk.h'. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | rockchip: i2c: fix >32 byte writesJohn Keeping2016-09-13-2/+2
| | | | | | | | | | | | | | | | | | The special handling of the chip address and register address must only happen before we send the data buffer, otherwise we will end up inserting both of these every 32 bytes. Signed-off-by: John Keeping <john@metanate.com> Acked-by: Simon Glass <sjg@chromium.org>
* | rockchip: i2c: move register write out of inner loopJohn Keeping2016-09-13-2/+2
| | | | | | | | | | | | | | | | | | | | | | There is no point in writing intermediate values to the txdata registers. Also add padding to the debug logging to make it easier to read when there are leading zeroes. Signed-off-by: John Keeping <john@metanate.com> Acked-by: Simon Glass <sjg@chromium.org>
* | rockchip: i2c: use named constant when appropriateJohn Keeping2016-09-13-1/+1
|/ | | | | | | Make it clear that we are using the same value in two adjacent lines. Signed-off-by: John Keeping <john@metanate.com> Acked-by: Simon Glass <sjg@chromium.org>
* Prepare v2016.09Tom Rini2016-09-12-1/+1
| | | | Signed-off-by: Tom Rini <trini@konsulko.com>
* sf: fix sf probeCyrille Pitchen2016-09-12-1/+0
| | | | | | | | | | | | | This patch fixes the "sf probe" command. The very first SPI flash probe passes, for instance when u-boot tries to read its environment settings from a (Q)SPI memory but next "sf probe" commands fail because the flash memory node is unbound from the SPI controller children nodes. Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Hannes Schmelzer <oe5hpm@oevsv.at> Reviewed-by: Simon Glass <sjg@chromium.org>
* common, kconfig: move VERSION_VARIABLE to KconfigHeiko Schocher2016-09-09-73/+222
| | | | | | | move VERSION_VARIABLE from board config file into a Kconfig option. Signed-off-by: Heiko Schocher <hs@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-netTom Rini2016-09-09-46/+49
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| * net: asix: Fix AX88772B when used with DriverModelJoshua Scott2016-09-09-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A previous patch (net: asix: fix operation without eeprom) added a two-byte shift to the packet buffer when receiving a packet on the AX88772B. This shift was not included when the driver was updated to work with DriverModel. Testing on a Marvell DB-88F6820-ACM showed that the adapter was not functioning correctly (EHCI timeouts). This patch brings the two-byte shift to the DriverModel implementation of ops->recv (asix_eth_recv). Testing on the same board, we were able to TFTP a file over and confirm that the crc32 was correct. Signed-off-by: Joshua Scott <joshua.scott@alliedtelesis.co.nz> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * Revert "net: nfs: Correct the reply data buffer size"Joe Hershberger2016-09-09-1/+1
| | | | | | | | | | | | | | | | | | This reverts commit 6279b49e6c2fdaf8665355d1777bc90cd41fcf90. This caused a bad data crc. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reported-by: Guillaume GARDET <guillaume.gardet@free.fr>
| * Revert "net: nfs: Use the tx buffer to construct rpc msgs"Joe Hershberger2016-09-09-45/+43
| | | | | | | | | | | | | | | | | | This reverts commit 998372b4798fd7ebb666f571950df925b8d80f69. This caused a data abort on some platform. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reported-by: Guillaume GARDET <guillaume.gardet@free.fr>
* | cmd: Rework disk.c usageTom Rini2016-09-09-7/+3
| | | | | | | | | | | | | | | | | | | | We only need the function found in cmd/disk.c when we have IDE, SCSI or USB_STORAGE enabled. While the first two are easy to get right, in the 3rd case we assume that the set of cases where we do have USB and do not enable USB_STORAGE are small enough that we can take the small bloat of un-discarded strings on gcc prior to 6.x Signed-off-by: Tom Rini <trini@konsulko.com>
* | configs: Migrate CONFIG_USB_STORAGETom Rini2016-09-09-235/+1052
| | | | | | | | | | | | | | In some cases we were missing CONFIG_USB=y so enable that when needed. Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* | configs: Resync with savedefconfigTom Rini2016-09-09-549/+392
|/ | | | Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2016-09-09-56/+1576
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| * warp7: Print secure/non-secure mode infoFabio Estevam2016-09-06-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | warp7 has two targets: - warp7_defconfig: boots in non-secure mode - warp7_secure_defconfig: boots in secure mode Print the mode that is being used to help users to easily identify which target is running on the board. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
| * warp7: Use PARTUUID to specify the rootfs locationFabio Estevam2016-09-06-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | warp7 can run different kernel versions, such as NXP 4.1 or mainline. Currently the rootfs location is passed via mmcblk number and the problem with this approach is that the mmcblk number for the eMMC changes depending on the kernel version. In order to avoid such issue, use UUID method to specify the rootfs location. Succesfully tested booting a NXP 4.1 and also a mainline kernel. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
| * warp7: Add a secure mode targetFabio Estevam2016-09-06-0/+36
| | | | | | | | | | | | | | NXP kernel expects to boot in secure mode, so introduce warp7_secure_defconfig target which selects CONFIG_ARMV7_BOOT_SEC_DEFAULT. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
| * mx6ul_14x14_ev: Enable the CCGR clocks earlierFabio Estevam2016-09-06-2/+2
| | | | | | | | | | | | | | | | | | | | | | To be in the safe side we need to enable the CCGR clocks prior to calling arch_cpu_init(). Inspired by Tim Harvey's commit d783c2744f9 ("imx: ventana: fix boot to SD"). Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Eric Nelson <eric@nelint.com> Tested-by: Eric Nelson <eric@nelint.com>
| * mx6ul_14x14_evk: Adjust SPL DDR3 settingsFabio Estevam2016-09-06-7/+7
| | | | | | | | | | | | | | | | Adjust DDR3 initialization done in SPL by comparing them against the NXP DCD table. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Eric Nelson <eric@nelint.com>
| * mx6ul_14x14_evk: Pass refsel and refr fields to avoid hangFabio Estevam2016-09-06-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When running a NXP 4.1 kernel with U-Boot mainline on a mx6ul-evk, we observe a hang when going into the lowest operational point of cpufreq. This hang issue does not happen on the NXP U-Boot version. After comparing the SPL DDR initialization against the DCD table from NXP U-Boot, the key difference that causes the hang is the MDREF register setting: DATA 4 0x021B0020 0x00000800 ,which means: REF_SEL = 0 --> Periodic refresh cycle: 64kHz REFR = 1 ---> Refresh Rate - 2 refreshes So adjust the MDREF initialization for mx6ul_evk accordingly to fix the kernel hang issue at low bus frequency. Reported-by: Eric Nelson <eric@nelint.com> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Eric Nelson <eric@nelint.com>
| * mx6: ddr: Allow changing REFSEL and REFR fieldsFabio Estevam2016-09-06-4/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently MX6 SPL DDR initialization hardcodes the REF_SEL and REFR fields of the MDREF register as 1 and 7, respectively for DDR3 and 0 and 3 for LPDDR2. Looking at the MDREF initialization done via DCD we see that boards do need to initialize these fields differently: $ git grep 0x021b0020 board/ board/bachmann/ot1200/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800 board/ccv/xpress/imximage.cfg:DATA 4 0x021b0020 0x00000800 /* MMDC0_MDREF */ board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x7800 board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6qsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6qsabreauto/mx6dl.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6qsabreauto/mx6qp.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6sabresd/mx6dlsabresd.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6slevk/imximage.cfg:DATA 4 0x021b0020 0x00001800 board/freescale/mx6sxsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00000800 board/freescale/mx6sxsabresd/imximage.cfg:DATA 4 0x021b0020 0x00000800 board/warp/imximage.cfg:DATA 4 0x021b0020 0x00001800 So introduce a mechanism for users to be able to configure REFSEL and REFR fields as needed. Keep all the mx6 SPL users in their current REF_SEL and REFR values, so no functional changes for the existing users. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Eric Nelson <eric@nelint.com>
| * mx7dsabresd: Directly write to register LDOGCTLFabio Estevam2016-09-06-3/+1
| | | | | | | | | | | | | | | | | | Register LDOGCTL contains only bit 0 as a valid bit, so there is no need to do a read-modify-write operation. Simplify the code by writing directly to this register. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
| * mx7dsabresd: Directly write to register LDOGCTLFabio Estevam2016-09-06-3/+1
| | | | | | | | | | | | | | | | | | Register LDOGCTL contains only bit 0 as a valid bit, so there is no need to do a read-modify-write operation. Simplify the code by writing directly to this register. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
| * pico-imx6ul: Directly write to register LDOGCTLFabio Estevam2016-09-06-3/+1
| | | | | | | | | | | | | | | | | | Register LDOGCTL contains only bit 0 as a valid bit, so there is no need to do a read-modify-write operation. Simplify the code by writing directly to this register. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
| * ARM: board: cm_fx6: fix mtd partition fixupChristopher Spinrath2016-09-06-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ft_board_setup may return early in the case that the board revision cannot be obtained. In that case it is assumed that no revision specific correction in the fdt is neccessary. But the mtd partitions will not be fixed up either altough they are not revision specific. Move the call to fdt_fixup_mtdparts in front of the revision specific part to ensure that the partitions are fixed up even if the board revision cannot be obtained. While on it, fix a spelling mistake in a comment introduced by the same commit. Fixes: 62d6bac66038 ("ARM: board: cm_fx6: fixup mtd partitions in the fdt") Signed-off-by: Christopher Spinrath <christopher.spinrath@rwth-aachen.de> Reviewed-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Nikita Kiryanov <nikita@compulab.co.il>
| * mx6ul_14x14_evk: don't use array for SD2 card detect padEric Nelson2016-09-06-14/+10
| | | | | | | | | | | | | | | | | | Only a single pad is changed to change sdhc2_dat3 from an SDIO pin to and from GPIO4:5, so remove the array and use the imx_iomux_v3_setup_pad() routine. Signed-off-by: Eric Nelson <eric@nelint.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
| * warp7: Modify fdt_file environment variableBreno Lima2016-09-06-1/+1
| | | | | | | | | | | | | | | | Use imx7s-warp.dts as fdt_file because this is the name that upstream kernel will deploy. Signed-off-by: Breno Lima <breno.lima@nxp.com> Acked-by: Fabio Estevam <fabio.estevam@nxp.com>
| * warp: Fix RAM size runtime detectionFabio Estevam2016-09-06-1/+116
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit a13d3757f7df ("warp: Use imx_ddr_size() for calculating the DDR size") warp board no longer boots. The reason for the breakage is that the warp board is using the DDR configuration from mx6slevk. A fundamental difference between warp and mx6slevk is that warp only uses one DDR chip select while mx6slevk uses two. The imx_ddr() function calculates the RAM size in runtime by reading the values of registers MDCTL and MDMISC. So in order to fix this warp boot issue, create a imximage DDR file specific to warp, where the MDCTL register is configured to only activates a single chip select. Reported-by: Breno Lima <breno.lima@nxp.com> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Breno Lima <breno.lima@nxp.com>
| * warp7: Add PMIC supportVanessa Maegima2016-09-06-0/+69
| | | | | | | | | | | | | | | | Add PMIC support. Tested by command "pmic PFUZE3000 dump". Signed-off-by: Vanessa Maegima <vanessa.maegima@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
| * arm: imx: Add support for Advantech DMS-BA16 boardAkshay Bhat2016-09-06-0/+1244
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for Advantech DMS-BA16 board. The board is based on Advantech BA16 module which has a i.MX6D processor. The board supports: - FEC Ethernet - USB Ports - SDHC and MMC boot - SPI NOR - LVDS and HDMI display Basic information about the module: - Module manufacturer: Advantech - CPU: Freescale ARM Cortex-A9 i.MX6D - SPECS: Up to 2GB Onboard DDR3 Memory; Up to 16GB Onboard eMMC NAND Flash Supports OpenGL ES 2.0 and OpenVG 1.1 HDMI, 24-bit LVDS 1x UART, 2x I2C, 8x GPIO, 4x Host USB 2.0 port, 1x USB OTG port, 1x micro SD (SDHC),1x SDIO, 1x SATA II, 1x 10/100/1000 Mbps Ethernet, 1x PCIe X1 Gen2 Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com> Cc: u-boot@lists.denx.de Cc: sbabic@denx.de
| * mx7dsabresd: Print secure/non-secure mode infoFabio Estevam2016-09-06-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | mx7dsabresd has two targets: - mx7dsabresd_defconfig: boots in non-secure mode - mx7dsabresd_secure_defconfig: boots in secure mode Print the mode that is being used to help users to easily identify which target is running on the board. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
| * mtd: nand: mxs: fix cache alignment for cache lines >32Stefan Agner2016-09-06-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | Currently the command buffer gets allocated with a size of 32 bytes. This causes warning messages on systems with cache lines bigger than 32 bytes: CACHE: Misaligned operation at range [9df17a00, 9df17a20] Define command buffer to be at least 32 bytes, but more if cache line is bigger. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
| * imx: ventana: enable splashscreen supportTim Harvey2016-09-06-3/+4
| | | | | | | | Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * board: tbs2910: fix HDMI pre-console bufferSoeren Moch2016-09-06-1/+3
| | | | | | | | | | | | | | HDMI output must be enabled very early to also enable the pre-console buffer Signed-off-by: Soeren Moch <smoch@web.de> Reviewed-by: Stefano Babic <sbabic@denx.de>
| * board: tbs2910: always enable usbkbdSoeren Moch2016-09-06-7/+6
| | | | | | | | | | | | | | 'usb start' is much faster now, so always enable usb keyboard Signed-off-by: Soeren Moch <smoch@web.de> Reviewed-by: Stefano Babic <sbabic@denx.de>
generated by cgit v1.1 at 2024-12-27 18:31:17 +0000