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* x86: chromebox_panther: Drop the cache line size hackBin Meng2016-02-05-2/+0
| | | | | | | Now that the RTL8169 driver warning is fixed we can drop this. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* efi: app: Disable CONFIG_USB_EHCI_PCIBin Meng2016-02-05-0/+1
| | | | | | | | It does not build if without CONFIG_DM_PCI_COMPAT. For now we just disable it, until some day we add USB support to EFI application. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* efi: app: Clean up defconfigBin Meng2016-02-05-4/+1
| | | | | | | | Move some #undef from efi-x86.h to efi-x86_defconfig as these are already Kconfig options. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: quark: Use Quark's own PCI config APIsBin Meng2016-02-05-2/+3
| | | | | | | | | There are still two places in Quark's MRC codes that use the generic legacy PCI APIs, but as we are phasing out these legacy APIs, switch to use Quark's own PCI config routines. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* net: e1000: Convert to use DM PCI APIBin Meng2016-02-05-1/+78
| | | | | | | Update this driver to use proper DM PCI APIs. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* net: designware: Use dm_pci_mem_to_phys() in the probe routineBin Meng2016-02-05-3/+1
| | | | | | | Convert to use native DM PCI API dm_pci_mem_to_phys(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* net: pch_gbe: Convert to use DM PCI APIBin Meng2016-02-05-16/+13
| | | | | | | Use native DM PCI APIs instead of legacy compatible ones. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: pci: Drop legacy PCI APIsBin Meng2016-02-05-65/+0
| | | | | | | | | Now that we have converted all x86 codes to use DM PCI APIs, drop those legacy ones. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* x86: pci: Use DM PCI APIs in pci_assign_irqs()Bin Meng2016-02-05-3/+3
| | | | | | | | Drop legacy PCI APIs usage in pci_assign_irqs() as well. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* x86: qemu: Convert to use DM PCI APIBin Meng2016-02-05-17/+17
| | | | | | | | Use pci_[read|write]_config intead of x86_pci_[read|write]_config. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* x86: tnc: Remove IGD and SDVO devices from driver modelBin Meng2016-02-05-0/+36
| | | | | | | | | | | | | | | | | | | With recent DM PCI changes to vesa_fb driver, external graphics card does not work any more. This is because: after setting the function disable bit, IGD and SDVO devices will disappear in the PCI configuration space. This however creates an inconsistent state from a driver model PCI controller point of view, as these two PCI devices are still attached to its parent's child device list as maintained by the driver model. Some driver model PCI APIs like dm_pci_find_class() used in the vesa_fb driver, are referring to the list to speed up the finding process instead of re-enumerating the whole PCI bus, so it gets the stale cached data which is wrong. To fix this, manually remove these two devices. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* x86: tnc: Use DM PCI API in disable_igd()Bin Meng2016-02-05-3/+19
| | | | | | | | | Once we get udevice of IGD and SDVO, we can use its udevice to access PCI configuration space with dm_pci_write_config32(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* x86: tnc: Change disable_igd() to have a return valueBin Meng2016-02-05-3/+7
| | | | | | | | | So far disable_igd() does not have any return value, but we may need that in the future. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* x86: irq: Convert to use DM PCI APIBin Meng2016-02-05-4/+4
| | | | | | | | | Now that we have irq router's udevice passed as a parameter, it's time to start using the DM PCI API instead of those legacy ones. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* x86: irq: Move irq_router to a per driver privBin Meng2016-02-05-46/+51
| | | | | | | | | | | At present irq_router is declared as a static struct irq_router in arch/x86/cpu/irq.c. Since it's a driver control block, it makes sense to move it to a per driver priv. Adjust existing APIs to accept an additional parameter of irq_router's udevice. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* x86: irq: Get irq_router's bdf via dm_pci_get_bdf()Bin Meng2016-02-05-8/+1
| | | | | | | | | There is no need to parse PCH's <reg> property as we have already a DM PCI API dm_pci_get_bdf() that can handle this. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* x86: minnowmax: Drop io-base property in the pch_pinctrl nodeBin Meng2016-02-05-1/+0
| | | | | | | | IOBASE is now obtained from PCH driver, drop this <io-base> property. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* x86: Drop asm/arch/gpio.hBin Meng2016-02-05-92/+2
| | | | | | | | | asm/arch/gpio.h is not needed anymore as we get the GPIO base from PCH driver. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* x86: ich6_gpio: Convert to use proper DM APIBin Meng2016-02-05-255/+186
| | | | | | | | | | | | | | | | At present this GPIO driver still uses the legacy PCI API. Now that we have proper PCH drivers we can use those to obtain the information we need. While the device tree has nodes for the GPIO peripheral it is not in the right place. It should be on the PCI bus as a sub-peripheral of the PCH device. Update the device tree files to show the GPIO controller within the PCH, so that PCI access works as expected. This also adds '#address-cells' and '#size-cells' to the PCH node. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* x86: pch9: Implement get_io_base opBin Meng2016-02-05-0/+17
| | | | | | | | IO_BASE is only seen on PCH9 device, implement the get_io_base op. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* dm: pch: Add get_io_base opBin Meng2016-02-05-0/+29
| | | | | | | | | | On some newer chipset (eg: BayTrail), there is an IO base address register on the PCH device which configures the base address of a memory-mapped I/O controller. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* x86: pch: Implement get_gpio_base opBin Meng2016-02-05-0/+99
| | | | | | | | Implement get_gpio_base op for bd82x6x, pch7 and pch9 drivers. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* dm: pch: Add get_gpio_base opBin Meng2016-02-05-0/+29
| | | | | | | | | | x86 GPIO registers are accessed via I/O port whose base address is configured in a PCI configuration register on the PCH device. Add an op get_gpio_base to get the GPIO base address from PCH. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* dm: pch: Rename get_sbase op to get_spi_baseBin Meng2016-02-05-14/+14
| | | | | | | | Spell out 'sbase' to 'spi_base' so that it looks clearer. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* dm: pch: Remove pch_get_version opBin Meng2016-02-05-48/+0
| | | | | | | | | | | | | pch_get_version op was only used by the ich spi controller driver, and does not really provide a good identification of pch controller so far, since we see plenty of Intel PCH chipsets and one differs from another a lot, which is not simply either a PCHV_7 or PCHV_9. Now that ich spi controller driver was updated to not get such info from pch, the pch_get_version op is useless now. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* x86: quark: Drop unprotect_spi_flash()Bin Meng2016-02-05-17/+0
| | | | | | | | | Unprotecting SPI flash is now handled in the SPI controller driver, via a call to the PCH driver. Drop the ad-hoc version. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* x86: tnc: Drop unprotect_spi_flash()Bin Meng2016-02-05-17/+0
| | | | | | | | | Unprotecting SPI flash is now handled in the SPI controller driver, via a call to the PCH driver. Drop the ad-hoc version. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* spi: ich: Change PCHV_ to ICHV_Bin Meng2016-02-05-8/+13
| | | | | | | | | | | The ICH SPI controller supports two variants, one of which is ICH7 compatible and the other is ICH9 compatible. Change 'pch_version' to 'ich_version' to better match its original name. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jteki@openedev.com> Tested-by: Simon Glass <sjg@chromium.org>
* spi: ich: Use compatible strings to distinguish controller versionBin Meng2016-02-05-11/+31
| | | | | | | | | | At present ich spi driver gets the controller version information via pch, but this can be simply retrieved via spi node's compatible string. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jteki@openedev.com> Tested-by: Simon Glass <sjg@chromium.org>
* spi: ich: Some clean upBin Meng2016-02-05-47/+47
| | | | | | | | | | | | This cleans up the ich spi driver a little bit: - Remove struct ich_spi_slave that is not referenced anywhere - Remove ending period in some comments - Move struct ich_spi_platdata and struct ich_spi_priv to ich.h - Add #ifndef _ICH_H_ .. in ich.h Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jteki@openedev.com>
* x86: x86-common.h: Add CONFIG_BOOTDELAYStefan Roese2016-02-05-0/+2
| | | | | | | | | | | | | Without this CONFIG_BOOTDELAY, autobooting does not work at all. As autoboot_command() from common/* will not get called. So lets define CONFIG_BOOTDELAY, so that auto-booting works on x86. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Miao Yan <yanmiaobest@gmail.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org> Tested-by: Miao Yan <yanmiaobest@gmail.com> Acked-by: Bin Meng <bmeng.cn@gmail.com>
* autoboot.c: Fill env vars in process_fdt_options() only if TEXT_BASE is setStefan Roese2016-02-05-2/+2
| | | | | | | | | | | | | | | | The x86 build target "efi-x86" has no TEXT_BASE configured. And with the introduction of CONFIG_BOOTDELAY for x86, this function is now called for this board as well. Resulting in compile errors for this target. Without TEXT_BASE it makes no sense to fill these values. So lets only configure the env variable if TEXT_BASE is defined. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2016-02-04-2/+2
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| * usb: gadget: dwc2_udc_otg: modified the check condition for max packet size ↵Frank Wang2016-02-04-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | of ep_in in high speed In current high speed fastboot, fs_ep_in.wMaxPacketSize is configured 64 bytes as default, as a result, it failed to match the size at initialization stage in usb controller. Actually, hardware can support less than or equal to 512 bytes in high speed mode, so I changed the condition from '!=' to '>' to fix this issue. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Tested-by: Steve Rae <srae@broadcom.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2016-02-04-1/+1
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| * | Revert "arm: socfpga: set the fpga global bit to disable HPS to FPGA signals"Dinh Nguyen2016-02-04-1/+1
| |/ | | | | | | | | | | | | | | Apparently, the logic for the FPGA global bit is not universal between Gen5 and Gen10 devices is not the same. Disabling this bit, while applicable to Gen10 devices, will break FPGA programming on Gen5 devices. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* | imx: mx6: implement board_mmc_get_env_devPeng Fan2016-02-04-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | Implement board_mmc_get_env_dev for the boards. Following is examples: SD1/SD2/SD3: return devno; SD2/SD3: return devno - 1; SD2/SD4: if (devno == 2), return dev - 2; return dev - 1; Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* | imx: mx6: implement mmc_get_env_devPeng Fan2016-02-04-0/+32
| | | | | | | | | | | | | | | | | | | | Implement mmc_get_env_dev, devno can be got from smbr1 of SRC. Introduce a weak function board_mmc_get_env_dev, different boards can implement it according to different sdhc controllers that used by the board. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* | imx: mx7dsabresd: move mmc_get_env_devno to soc codePeng Fan2016-02-04-15/+26
| | | | | | | | | | | | | | | | | | | | | | Move mmc_get_env_devno to soc.c and rename to mmc_get_env_dev to match the one in common/env_mmc.c. Introduce a weak function board_mmc_get_env_dev. Different boards can implement this according to sdhc controller which is used by the board. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* | dm: vybrid_gpio: Drop legacy codeBhuvanchandra DV2016-02-02-18/+0
| | | | | | | | | | | | | | | | All boards using this driver are with device tree support, hence drop the legacy code in driver to have a pure DT solution. Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | dm: lpuart: Drop the legacy codeBhuvanchandra DV2016-02-02-99/+2
| | | | | | | | | | | | | | | | All boards using this driver are with device tree support, hence drop the legacy code in driver to have a pure DT solution. Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | arm: vybrid: Drop enabling GPIO, SPI and UART in legacy modeBhuvanchandra DV2016-02-02-19/+0
| | | | | | | | | | | | | | | | | | Remove the legacy way of enabling GPIO, SPI and UART on Vybrid based boards since these driver's now only supports DT mode. Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Acked-by: Stefan Agner <stefan.agner@toradex.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | arm: vybrid: Update defconfig'sBhuvanchandra DV2016-02-02-14/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Let's go with pure DT solution for board's based on NXP/Freescale Vybrid platform. - Merge the DT defconfig with non-DT defconfig for Toradex Colibri VF50/VF61 and drop the non-DT defconfig. - Update the legacy defconfigs for NXP/Freescale VF610 Tower Board with DT. - Update the legacy defconfigs for Phytec phyCORE-vybrid Board with DT. Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Acked-by: Stefan Agner <stefan.agner@toradex.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | arm: pcm052: Add device tree file'sBhuvanchandra DV2016-02-02-1/+24
| | | | | | | | | | | | | | | | | | - Add device tree files for Phytec phyCORE-Vybrid Board. - Enable lpuart support for Phytec phyCORE-Vybrid Board. - Use UART1 for stdout. Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | arm: vf610-twr: Add device tree file'sBhuvanchandra DV2016-02-02-1/+24
| | | | | | | | | | | | | | | | | | - Add device tree files for NXP/Freescale VF610 Tower Board. - Enable lpuart support on NXP/Freescale VF610 Tower Board. - Use UART1 as stdout. Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | arm: colibri-vf: Enable serial supportBhuvanchandra DV2016-02-02-0/+10
| | | | | | | | | | | | | | | | - Enable lpuart support on Toradex Colibri VF50/VF61 - Use UART0 for stdout. Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | arm: vybrid: Update the license stringBhuvanchandra DV2016-02-02-20/+0
| | | | | | | | | | | | | | | | Since SPDX license is already there, drop the full one. Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Acked-by: Stefan Agner <stefan.agner@toradex.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | arm: vybrid: Enable lpuart supportBhuvanchandra DV2016-02-02-0/+43
| | | | | | | | | | | | | | | | Add device tree node's for lpuart on Vybrid platform Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Acked-by: Stefan Agner <stefan.agner@toradex.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | imx: mx6sxsabresd: Add MCIMX28LCD display supportYe Li2016-02-02-0/+81
| | | | | | | | | | | | | | | | The i.MX6SX SABRESD board supports MCIMX28LCD (800x480x24) at LCDIF1 port, enable this display feature by adding relevant BSP codes and configurations. Signed-off-by: Ye Li <ye.li@nxp.com>
* | imx: mx6ul/sx: Fix issue in LCDIF clock dividers calculationYe Li2016-02-02-4/+0
| | | | | | | | | | | | | | | | | | | | The checking with max frequency supported is not correct, because the temp is calculated by max pre and post dividers. We can decrease any divider to meet the max frequency limitation. Actually, the calculation below the codes is doing this way to find best pre and post dividers. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
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