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* sunxi: Add i2c supportHans de Goede2014-07-18-0/+64
| | | | | | | | | | | | | Add support for the i2c controller found on all Allwinner sunxi SoCs, this is the same controller as found on the Marvell orion5x and kirkwood SoC families, with a slightly different register layout, so this patch uses the existing mvtwsi code. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Acked-By: Prafulla Wadaskar <prafulla@marvell.com> Acked-by: Heiko Schocher <hs@denx.de> [ ijc -- updated u-boot-spl-fel.lds ]
* mvtwsi: convert to CONFIG_SYS_I2C frameworkHans de Goede2014-07-16-41/+37
| | | | | | | | | | | | Note this has only been tested on Allwinner sunxi devices (support for which gets introduced by a later patch). The kirkwood changes have been compile tested using the wireless_space board config, the orion5x changes have been compile tested using the edminiv2 board config. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Heiko Schocher <hs@denx.de>
* sunxi: Avoid unused variable warning.Ian Campbell2014-07-08-1/+3
| | | | | | | | Mark rc as __maybe_unused since it is infact unused on systems with neither EMAC nor GMAC. Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Acked-by: Tom Rini <trini@ti.com>
* sunxi: Add Ian Campbell and Hans de Goede as cubietruck board-maintainersHans de Goede2014-07-06-2/+2
| | | | | Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: Add support for using MII phy-s with the GMAC nicChen-Yu Tsai2014-07-06-0/+11
| | | | | | | | | | Many A20 boards (ie Cubieboard2, A20-OLinuXino_MICRO) use an 100 Mbit MII phy together with the GMAC nic found in the A20 SoC, add support for this (this will get used when we add these boards in a later patch). Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: Add emac glue, enable emac on the cubieboardHans de Goede2014-07-06-1/+14
| | | | | Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* net: Rename and cleanup sunxi (Allwinner) emac driverStefan Roese2014-07-06-74/+70
| | | | | | | | | | | | | | | | | There have been 3 versions of the sunxi_emac support patch during its development. Somehow version 2 ended up in upstream u-boot where as the u-boot-sunxi git repo got version 3. This bumps the version in upstream u-boot to version 3 of the patch: - Initialize MII clock earlier so mii access to allow independent use - Name change from WEMAC to EMAC to match mainline kernel & chip manual - Cosmetic code cleanup Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net> Signed-off-by: Oliver Schinagl <oliver@schinagl.nl> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: Add sun5i supportHans de Goede2014-07-06-0/+135
| | | | | | | | | | | | | | | | | | | Add support for the Allwinner A13 and A10s SoCs also know as the Allwinner sun5i family, and the A13-OLinuXinoM A13 based and r7-tv-dongle A10s based boards. The only differences compared to the already supported sun4i and sun7i families are all in the DRAM controller initialization: -Different hcpr values -Different MBUS settings -Some other small initialization changes Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net> Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Oliver Schinagl <oliver@schinagl.nl> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: Add sun4i supportHans de Goede2014-07-06-3/+143
| | | | | | | | | | | | | | | | | Add support for the Allwinner A10 SoC also known as the Allwinner sun4i family, and add the Cubieboard board which uses the A10 SoC. Compared to sun7 only the DRAM controller is a bit different: -Controller reset bits are inverted, but only for Rev. A -Different hpcr values -No MBUS on sun4i -Various other initialization changes Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net> Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Oliver Schinagl <oliver@schinagl.nl> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: Implement reset_cpuHans de Goede2014-07-06-0/+12
| | | | | | | There is no way to reset the cpu, so use the watchdog for this. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: Remove mmc DMA supportHans de Goede2014-07-06-135/+7
| | | | | | | | | | | | | | | | The DMA code in sunxi_mmc.c is broken. mmc_trans_data_by_dma() allocates the dma descriptors on the stack, and then exits while the dma transfer is in progress, so the dma engine is reading stack memory which at that point may be re-used. So far we've gotten away with this by luck, but recent u-boot changes have shifted the stack start address by 16 bytes, which combined with dma alignment now exposes this problem. Since we end up just busy waiting for the dma engine anyway, this commit fixes things by simply removing the dma code, resulting in smaller bug-free code. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: Fix u-boot-spl.lds to refer to .vectorsHans de Goede2014-07-06-0/+1
| | | | | | | | | Adjust the u-boot-spl.lds linker script to match the changes made in the 41623c91b09a0c865fab41acdaff30f060f29ad6 "arm: move exception handling out of start.S files" commit. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: mksunxiboot: Fix loading of files with a size which is not a multiple ↵Hans de Goede2014-07-06-6/+4
| | | | | | | | | | | | | of 4 We should not be aligning the amount of bytes which we try to read from the disk, this leads to trying to read more bytes then there are which fails. file_size is already aligned to BLOCK_SIZE before being stored in img.header.length, so there is no need for load_size at all. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* socfpga: Relocate arch common functions away from boardChin Liang See2014-07-05-23/+24
| | | | | | | | | | | | | To move the arch common function away from board folder to arch/arm/cpu/armv7/socfpga folder. Its to avoid code duplication for other non Altera dev kit which is using socfpga device. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Dinh Nguyen <dinguyen@altera.com> Acked-by: Detlev Zundel <dzu@denx.de>
* integrator: switch to generic boardLinus Walleij2014-07-05-0/+1
| | | | | | | | | Turn on generic board for the integrators, as per the request in the startup message. Everything just works, tested on the Integrator/AP and Integrator/CP. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Simon Glass <sjg@chromium.org>
* ARM: rpi_b: enable GENERIC_BOARDStephen Warren2014-07-05-0/+1
| | | | | | | Serial port, SD card, and LCD all work. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Acked-by: Simon Glass <sjg@chromium.org>
* arm, calimain: Add CONFIG_SYS_GENERIC_BOARDChristian Riesch2014-07-05-1/+2
| | | | Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
* arm: Fix armv8 compilation errorShaibal.Dutta2014-07-05-1/+1
| | | | | | | | | | | Fix following compilation error when CONFIG_ARM64 is defined Error: unknown or missing system register name at operand 2 -- `mrs x0,daifmsr daifset,#3' Signed-off-by: Shaibal.Dutta <shaibal.dutta@broadcom.com> Signed-off-by: Darwin Rambo <drambo@broadcom.com> Reviewed-by: Darwin Rambo <drambo@broadcom.com>
* arm:board:h2200: Add CONFIG_SYS_GENERIC_BOARDŁukasz Dałek2014-07-05-0/+1
| | | | | | | Enable 'generic board init' for H2200 palmtop. Signed-off-by: Lukasz Dalek <luk0104@gmail.com> Acked-by: Marek Vasut <marex@denx.de>
* arm: spl: fix include guardJeroen Hofstee2014-07-05-2/+2
| | | | | cc: Tom Rini <trini@ti.com> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
* Reformat boards.cfgAlbert ARIBAUD2014-07-05-10/+10
| | | | | Run tools/reformat.py -i -d '-' -s 8 to reorder boards as header comments suggest
* socfpga: Adding Scan Manager driverChin Liang See2014-07-05-1/+980
| | | | | | | | | | | | Scan Manager driver will be called to configure the IOCSR scan chain. This configuration will setup the IO buffer settings Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Wolfgang Denk <wd@denx.de> CC: Pavel Machek <pavel@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
* socfpga: Adding DesignWare watchdog supportChin Liang See2014-07-05-0/+15
| | | | | | | | | | | To enable the DesignWare watchdog support at SOCFPGA Cyclone V dev kit. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Anatolij Gustschin <agust@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Heiko Schocher <hs@denx.de> Cc: Tom Rini <trini@ti.com>
* watchdog/denali: Adding DesignWare watchdog driver supportChin Liang See2014-07-05-0/+75
| | | | | | | | | | | | To add the DesignWare watchdog driver support. It required information such as register base address and clock info from configuration header file within include/configs folder. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Anatolij Gustschin <agust@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Heiko Schocher <hs@denx.de> Cc: Tom Rini <trini@ti.com>
* arm: ep9315: Return back Cirrus Logic EDB9315A board supportSergey Kostanbaev2014-07-04-27/+1636
| | | | | | | This patch returns back support for old ep93xx processors family Signed-off-by: Sergey Kostanbaev <sergey.kostanbaev@gmail.com> Cc: albert.u.boot@aribaud.net
* gpio: spear_gpio: Fix gpio_set_value() implementationAxel Lin2014-07-04-1/+4
| | | | | | | | | | | | | | | | In current gpio_set_value() implementation, it always sets the gpio control bit no matter the value argument is 0 or 1. Thus the GPIOs never set to low. This patch fixes this bug. The address bus is used as a mask on read/write operations, so that independent software drivers can set their GPIO bits without affecting any other pins in a single write operation. Thus we don't need a read-modify-write to update the register. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Stefan Roese <sr@denx.de> Reviewed-by: Vipin Kumar <vipin.kumar@st.com> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
* ARM: cache_v7: use __weakJeroen Hofstee2014-07-04-55/+15
| | | | | | | | | | This is not only more readable but also prevents a warning about a missing prototype. The prototypes which are actually missing are added. cc: Albert Aribaud <albert.u.boot@aribaud.net> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl> Reviewed-by: Tom Rini <trini@ti.com>
* ARMv8/ls2085a_emu: Add LS2085A emulator and simulator board supportYork Sun2014-07-04-2/+622
| | | | | | | | | | | | | | | | LS2085A is an ARMv8 implementation. This adds board support for emulator and simulator: Two DDR controllers UART2 is used as the console IFC timing is tightened for speedy booting Support DDR3 and DDR4 as separated targets Management Complex (MC) is enabled Support for GIC 500 (based on GICv3 arch) Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com> Signed-off-by: J. German Rivera <German.Rivera@freescale.com> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
* armv8/fsl-lsch3: Add support to load and start MC FirmwareJ. German Rivera2014-07-03-3/+383
| | | | | | | | | | | | | | | | Adding support to load and start the Layerscape Management Complex (MC) firmware. First, the MC GCR register is set to 0 to reset all cores. MC firmware and DPL images are copied from their location in NOR flash to DDR. MC registers are updated with the location of these images. Deasserting the reset bit of MC GCR register releases core 0 to run. Core 1 will be released by MC firmware. Stop bits are not touched for this step. U-boot waits for MC until it boots up. In case of a failure, device tree is updated accordingly. The MC firmware image uses FIT format. Signed-off-by: J. German Rivera <German.Rivera@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com> Signed-off-by: Shruti Kanetkar <Shruti@Freescale.com>
* ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoCYork Sun2014-07-03-4/+944
| | | | | | | | | | | | | | Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
* ARMv8: Adjust MMU setupYork Sun2014-07-03-30/+44
| | | | | | | Make MMU function reusable. Platform code can setup its own MMU tables. Signed-off-by: York Sun <yorksun@freescale.com> CC: David Feng <fenghua@phytium.com.cn>
* Added 64-bit MMIO accessors for ARMv8J. German Rivera2014-07-03-0/+8
| | | | | | | This is needed for accessing peripherals with 64-bit MMIO registers, from ARMv8 processors. Signed-off-by: J. German Rivera <German.Rivera@freescale.com>
* arm: Add support for semihosting for armv8 fastmodel targets.Darwin Rambo2014-07-03-12/+462
| | | | | | | | | | | | | | | | | | | | | | The armv8 ARM Trusted Firmware (ATF) can be used to load various ATF images and u-boot, and does this for virtual platforms by using semihosting. This commit extends this idea by allowing u-boot to also use semihosting to load the kernel/ramdisk/dtb. This eliminates the need for a bootwrapper and produces a more realistic boot sequence with virtual models. Though the semihosting code is quite generic, support for armv7 in fastmodel is less useful due to the wide range of available silicon and the lack of a free armv7 fastmodel, so this change contains an untested armv7 placeholder for the service trap opcode. Please refer to doc/README.semihosting for a more detailed description of semihosting and how it is used with the armv8 virtual platforms. Signed-off-by: Darwin Rambo <drambo@broadcom.com> Cc: trini@ti.com Cc: fenghua@phytium.com.cn Cc: bhupesh.sharma@freescale.com
* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-07-02-1078/+4245
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| * Merge remote-tracking branch 'u-boot-samsung/master'Albert ARIBAUD2014-07-01-256/+717
| |\ | | | | | | | | | | | | | | | | | | | | | Conflicts: boards.cfg Conflict was trivial between goni maintainer change and lager_nor removal.
| | * Samsung: Goni: change maintainer to Robert BaldygaPrzemyslaw Marczak2014-06-30-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Robert Baldyga will now take care of this board. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Robert Baldyga <r.baldyga@samsung.com> Acked-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * PMIC: MAX77686: fix invalid bus checkJeroen Hofstee2014-06-23-5/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since p->bus is unsigned checking for negative values is optimized away. Since bus is already used as an argument use tmp. While at it, don't declare variables in the middle of a function. cc: Rajeshwari Shinde <rajeshwari.s@samsung.com> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * Exynos: Split 5250 and 5420 memory bank configurationMichael Pratt2014-06-23-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since snow has a different memory configuration than peach, split the configuration between the 5250 and 5420. Exynos 5420 supports runtime memory configuration detection, and can make the determination between 4 and 7 banks at runtime. Include the bank size with the number of banks for context to make the number of banks meaningful. Signed-off-by: Michael Pratt <mpratt@chromium.org> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * Exynos5: Config: Enable USB boot mode for all Exynos5 SoCsAkshay Saraswat2014-06-23-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Right now USB booting is enabled for Exynos5250 only. Moving all the configs for USB boot mode from exynos5250-dt.h to exynos5-dt.h in order to enableUSB booting for all Exynos5 SoCs. Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * Exynos5: Config: Increase SPL footprint for Exynos5420Akshay Saraswat2014-06-23-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Max footprint for SPL in both Exynos 5250 and 5420 is limited to 14 KB. For Exynos5250 we need to keep it 14 KB because BL1 supports only fixed size SPL downloading. But in case of Exynos5420 we need not restrict it to 14 KB. And also, the SPL size for Exynos5420 is expected to increase with the upcoming patches and the patches under review right now. Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * Exynos5: Config: Place environment at the end of SPI flashAkshay Saraswat2014-06-23-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently environment resides at the location where BL2 ends. This may hold good in case there is an empty space at this position. But what if this place already has a binary or is expected to have one. To avoid such scenarios it is better to save environment at the end of the flash. Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * Exynos5420: Introduce support for the Peach-Pit boardAkshay Saraswat2014-06-23-133/+362
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While the Exynos5420 chip is used in both Smdk5420 and in the Peach-Pit line of devices, there could be other boards using the same chip, so a common configuration file is being added (exynos5420.h) as well as two common device tree files (exynos54xx.dtsi & exynos5420.dtsi). The peach board as declared in boards.cfg is a copy of smdk5420 declaration. The configuration files are similar, but define different default device trees, console serial ports and prompts. The device tree files for smdk5420 and peach-pit inherit from the same common file. Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * Exynos5420: Let macros be used for exynos5420Akshay Saraswat2014-06-23-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Macros defined in exynos5_setup.h specific to SMDK5420 are required for Peach-Pit too. Hence, replacing CONFIG_SMDK5420 with CONFIG_EXYNOS5420 to enable these macros for all the boards based on Exynos5420. Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * Exynos: SPI: Fix reading data from SPI flashAkshay Saraswat2014-06-23-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SPI recieve and transfer code in exynos_spi driver has a logical bug. We read data in a variable which can hold an integer. Then we assign this integer 32 bit value to another variable which has data type uchar. Latter represents a unit of our recieve buffer. Everytime when we write a value to our recieve buffer we step ahead by 4 units when actually we wrote to one unit. This results in the loss of 3 bytes out of every 4 bytes recieved. This patch intends to fix this bug. Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * trats/trats2: exynos_power_init: return 0 if no battery detected.Przemyslaw Marczak2014-06-19-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Generic board support is now enabled for Exynos 4, and if any init function returns an error then the init process is stopped. This makes a boot issue on the Trats and Trats2 devices. If the device is supplied by USB cable or an external power supply then it can't boot because function exynos_power_init returns an error. Now this function returns 0 if battery is not connected. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Piotr Wilczek <p.wilczek@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * Arndale: Enable preboot supportTushar Behera2014-06-18-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | We need to run 'usb start' as preboot command so that ethernet comes up during u-boot prompt. Signed-off-by: Tushar Behera <tushar.b@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * FIX: config: goni: Change goni configuration to store envs at eMMCŁukasz Majewski2014-06-18-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | Up till now goni's configuration has been stored at OneNAND. Since u-boot itself is now stored at eMMC it is more handy to store envs there as well. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * FIX: config: goni: Change goni configuration to use Tizen's THOR downlodaderŁukasz Majewski2014-06-16-0/+8
| | | | | | | | | | | | | | | | | | | | | Modify GONI's configuration to utilize THOR downloader. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * Exynos5420: DMC: Add software read levelingAkshay Saraswat2014-06-13-7/+255
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sometimes Read DQ and DQS are not in phase. Since, this phase shift differs from board to board, we need to calibrate it at DRAM init phase, that's read DQ calibration. This patch adds SW Read DQ calibration routine to compensate this skew. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * DMC: exynos5420: Gate CLKM to when reading PHY_CON13Doug Anderson2014-06-13-5/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | when CLKM is running. If we stop CLKM when sampling it the glitches all go away, so we'll do that as per Samsung suggestion. We also check the "is it locked" bits of PHY_CON13 and loop until they show the the value sampled actually represents a locked value. It doesn't appear that the glitching and "is it locked" are related, but it seems wise to wait until the PHY tells us the value is good before we use it. In practice we will not loop more than a couple times (and usually won't loop at all). Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
generated by cgit v1.1 at 2024-11-09 10:44:10 +0000