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| * | | phy: Return correct error code when timeout happensMichal Simek2016-05-24-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Return -ETIMEDOUT if timeout happens. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Stephen Warren <swarren@nvidia.com>
| * | | net: xilinx: Handle error value from phy_startup()Michal Simek2016-05-24-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Handle error returned by phy_startup() properly. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Stephen Warren <swarren@nvidia.com>
| * | | mkimage: Report information about fpgaMichal Simek2016-05-24-1/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add FIT_FPGA_PROP that user can identify an optional entry for fpga. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | fpga: Fix typo in function commentMichal Simek2016-05-24-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Trivial patch. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | ARM64: zynqmp: Enable CLK frameworkMichal Simek2016-05-24-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | ZynqMP is using fixed clocks now that's why enabling it to be available for drivers. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | ARM64: zynqmp: Add SPL support supportMichal Simek2016-05-24-3/+209
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support RAM and MMC boot mode in SPL also with SPL_FIT images. In MMC boot mode two boot options are available: 1) Boot flow with ATF(EL3) and full U-Boot(EL2): aarch64-linux-gnu-objcopy -O binary bl31.elf bl31.bin mkimage -A arm64 -O linux -T kernel -C none -a 0xfffe5000 -e 0xfffe5000 -d bl31.bin atf.ub cp spl/boot.bin <sdcard fat partition> cp atf.ub <sdcard fat partition> cp u-boot.bin <sdcard fat partition> 2) Boot flow with full U-Boot(EL3): cp spl/boot.bin <sdcard> cp u-boot*.img <sdcard> 3) emmc boot mode dd if=/dev/zero of=sd.img bs=1024 count=1024 parted sd.img mktable msdos parted sd.img mkpart p fat32 0% 100% kpartx -a sd.img mkfs.vfat /dev/mapper/loop0p1 mount /dev/mapper/loop0p1 /mnt/ cp spl/boot.bin /mnt cp u-boot.img /mnt cp u-boot.bin /mnt cp atf.ub /mnt umount /dev/mapper/loop0p1 kpartx -d sd.img cp sd.img /tftpboot/ and program it via u-boot tftpb 10000 sd.img mmcinfo mmc write 10000 0 $filesize mmc rescan mmc part ls mmc 0 psu_init() function contains low level SoC setup generated for every HW design by Xilinx design tools. xil_io.h is only supporting file to fix all dependencies from tools. The same solution was used on Xilinx Zynq. The patch also change CONFIG_SYS_INIT_SP_ADDR to the end of OCM which stays at the same location all the time. Bootrom expects starting address to be at 0xfffc0000 that's why this address is SPL_TEXT_BASE. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | ARM64: zynqmp: Add missing u-boot,dm-pre-reloc to DTSIMichal Simek2016-05-24-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | Add missing u-boot,dm-pre-reloc to get IPs initialized. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | ARM64: zynqmp: Align gic ranges for 64k in device treeAlexander Graf2016-05-24-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GIC ranges in the zynqmp device tree are only 4kb aligned. Since commit 12e14066f we automatically deal with aliases GIC regions though, so we can map them transparently into guests even on 64kb page size systems. This patch makes use of that features and sets GICC and GICV to 64kb aligned and sized regions. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | tools: zynqmpimage: Add Xilinx ZynqMP boot header generationMichal Simek2016-05-24-1/+280
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the zynqmpimage to mkimage. Only basic functionality is supported without encryption and register initialization with one partition which is filled by U-Boot SPL. For more detail information look at Xilinx ZynqMP TRM. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | SPL: FIT: Enable SPL_FIT_LOAD in RAM based boot modeMichal Simek2016-05-24-9/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support loading FIT in SPL for RAM bootmode. CONFIG_SPL_LOAD_FIT_ADRESS points to address where FIT image is stored in memory. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
| * | | ARM: zynq: Call ps7_post_config() for SPLMichal Simek2016-05-24-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | If ps7_post_config() is defined call it. It is enabling for example level shifters for PL bitstreams. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | ARM64: zynqmp: Enable option to overwrite default variablesMichal Simek2016-05-24-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Enable overwriting variables out of main config file. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | spl: Introduce new function spl_board_prepare_for_bootMichal Simek2016-05-24-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Call this function before passing control from SPL. For fpga case it is necessary to enable for example level shifters when bitstream is programmed. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | ARM64: zynqmp: Add debug uart for zc1751-dc1Michal Simek2016-05-24-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | It is helpful for debugging. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | ARM64: zynqmp: Enable SPI_FLASH and FLASH_BAR for ep108Michal Simek2016-05-24-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Add missing SPI flash options. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | ARM64: zynqmp: Remove CONFIG_PREBOOTMichal Simek2016-05-24-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_PREBOOT variable is breaking ./test/py framework. Remove it. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | ARM: zynq: Add support for SPL_LOAD_FITMichal Simek2016-05-24-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | Enable minimal function to be able to compile SPL_LOAD_FIT. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | ARM64: zynqmp: Wire up debug_uart setupMichal Simek2016-05-24-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | It has to be enabled by debug_uart_init(). Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | ARM64: zynqmp: Enable eMMC boot partitions commandsMichal Simek2016-05-24-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Enable some additional features of the eMMC boot partitions. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | ARM64: zynqmp: Add support for reading MAC from eepromMichal Simek2016-05-24-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for on board eeprom with programmed MAC for using in u-boot to have uniq address for every board. Most of the time uniq MAC address is on a label on the board. If address is not programmed use these command to program it. On zcu102: ZynqMP> mm.b 0 00000000: 00 ? 00 00000001: a0 ? 0a 00000002: 35 ? 35 00000003: 02 ? 02 00000004: 00 ? ef 00000005: 00 ? 67 00000006: 00 ? q i2c dev 5 i2c write 0 54 20 6 i2c md 54 20 Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | ARM64: zynqmp: Enable missing distro default optionsMichal Simek2016-05-24-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | Enable all options which distros requires. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | ARM64: zynqmp: Enable HUSH parser for all zynqmp targetsMichal Simek2016-05-24-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | Enable HUSH for all zynqmp boards which don't have it. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | ARM: dts: zynq: describe SLCR as simple-mfd rather than simple-busMasahiro Yamada2016-05-24-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 9f56917ab88a ("dm: core: make simple-bus compatible to simple-mfd") made possible to import the following commit: Linux commit: bc5ba9b98435bf76d92e0954da1784695aa449f1 The SLCR (System-Level Control Registers) block is an MFD (Multi Function Device) rather than a bus. "simple-mfd" seems a more suitable compatible string than "simple-bus". Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | gpio: zynq: Add support for reading gpio pin stateMichal Simek2016-05-24-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add zynq_gpio_get_function() which return status on gpio pin. This function enables gpio status command. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | ARM: zynq: load u-boot.img whether CONFIG_OF_SEPARATE is defined or notMasahiro Yamada2016-05-24-5/+1
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | Since commit ad1ecd2063da ("fdt: Build a U-Boot binary without device tree"), u-boot-dtb.img is identical to u-boot.img, so SPL can always load u-boot.img whether CONFIG_OF_SEPARATE is defined or not. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-atmelTom Rini2016-05-24-3/+625
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| * | | ARM: sama5d2: Implement boot device autodetectionMarek Vasut2016-05-24-1/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement support for saving ARM register R4 early during boot using save_boot_params . Implement support for decoding the stored register R4 value in spl_boot_device() to obtain boot device from which the SoC booted. This way, the SPL will always load U-Boot from the same device from which the SPL itself booted instead of using hard-coded boot device. This functionality is useful for example when booting sama5d2-xplained from SD card, where by default the SPL would try loading the U-Boot from eMMC and fail. This is because eMMC is on SDHCI0 (BOOT_DEVICE_MMC1), while SD slot is on SDHCI1 (BOOT_DEVICE_MMC2) and the SPL was hard-wired to always boot from BOOT_DEVICE_MMC1. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
| * | | ARM: atmel: Enable FIT image support for SAMA5DxMarek Vasut2016-05-24-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable the fitImage support for the entire SAMA5Dx lineup of CPUs. The fitImage is superior image format to uImage and it is useful to have it available. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas@biessmann.org> [rebase on current ToT] Signed-off-by: Andreas Bießmann <andreas@biessmann.org>
| * | | board: sama5d2_xplained: change SDHCI GCK's clock source to UPLLWenyou Yang2016-05-24-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change the clock source of the SDHCI's generated clock from PLLA to UPLL clock to align to Linux driver. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
| * | | ARM: at91: clock: complete the GCK's clock sourcesWenyou Yang2016-05-24-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the UPLL clock and master clock as a clock source for getting the generated clock frequency to complete its clock sources support. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
| * | | ARM: at91: clock: fix the GCK's clock sourceWenyou Yang2016-05-24-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before enabling a generated clock whose source is from the UPLL clock, check and enable the UPLL clock. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
| * | | board: atmel: sama5d2_xplained: fix the missing pin config of SDMMC0Wenyou Yang2016-05-24-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the missing pin config of the SDMMC0 interface. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
| * | | board: atmel: add SAMA5D2 PTC Engineering boardWenyou Yang2016-05-24-0/+500
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The board supports following features: - Boot media support: NAND Flash/SPI Flash - Support ethernet - Support USB mass storage Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
| * | | ARM: at91: sama5d2: add macro & field definitionsWenyou Yang2016-05-24-0/+29
| |/ / | | | | | | | | | | | | | | | | | | They will be used on SAMA5D2 PTC board. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
* | | Merge branch 'master' of git://git.denx.de/u-boot-x86Tom Rini2016-05-23-7530/+9859
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| * | x86: galileo: Override SMBIOS product nameBin Meng2016-05-23-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Override the default product name U-Boot reports in the SMBIOS table, to be compatible with the Intel provided UEFI BIOS, as Linux kernel drivers (drivers/mfd/intel_quark_i2c_gpio.c and drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c) make use of it to do different board level configuration. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: Switch to use SMBIOS Kconfig options when writing SMBIOS tablesBin Meng2016-05-23-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | Make use of the newly added Kconfig options of board manufacturer and product name to write SMBIOS tables. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: kconfig: Add two options for SMBIOS manufacturer and product nameBin Meng2016-05-23-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | This introduces two Kconfig options to be used by SMBIOS tables: board manufacturer and product name. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: galileo: Enable MP table generationBin Meng2016-05-23-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Now that we have added CPU uclass driver and fixed the IOAPIC ID conflict, enable MP table generation so that IOAPIC can be used by the Linux kernel. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: broadwell: Correct I/O APIC IDBin Meng2016-05-23-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Currently ID 2 is assgined to broadwell I/O APIC, however per chromebook_samus.dts 2 is the core#2 LAPIC ID. Now we change I/O APIC ID to 4 to avoid conflict. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: quark: Assign a unique I/O APIC IDBin Meng2016-05-23-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After power-on, both LAPIC and I/O APIC appear with the same APIC ID zero, which creates an ID conflict. When generating MP table, U-Boot reports zero as the LAPIC ID in the processor entry, and zero as the I/O APIC ID in the I/O APIC as well as the I/O interrupt assignment entries. Such MP table confuses Linux kernel and finally a kernel panic is seen during boot: BUG: unable to handle kernel paging request at ffff9000 IP: [<c101d462>] native_io_apic_write+0x22/0x30 *pdpt = 00000000014fb001 *pde = 00000000014ff067 *pte = 0000000000000000 Oops: 0002 [#1] Modules linked in: Pid: 1, comm: swapper Tainted: G W 3.8.7 #3 intel galileo/galileo EIP: 0060:[<c101d462>] EFLAGS: 00010086 CPU: 0 EIP is at native_io_apic_write+0x22/0x30 ... Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000009 Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: Call lapic_setup() in interrupt_init()Bin Meng2016-05-23-7/+5
| | | | | | | | | | | | | | | | | | | | | Let's configure LAPIC in a common place - interrupt_init(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: Remove SMP limitation in lapic_setup()Bin Meng2016-05-23-6/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | At present LAPIC is enabled and configured as virtual wire mode in lapic_setup() only when CONFIG_SMP is on. This limitation is however not necessary as for uniprocessor this is still needed. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: Don't touch IA32_APIC_BASE MSR on Intel QuarkBin Meng2016-05-23-12/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Intel Quark processor core provides an integrated Local APIC but does not support the IA32_APIC_BASE MSR. As a result, the Local APIC is always globally enabled and the Local APIC base address is fixed at 0xfee00000. Attempting to access the IA32_APIC_BASE MSR causes a general protection fault. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: galileo: Enable CPU driverBin Meng2016-05-23-0/+14
| | | | | | | | | | | | | | | | | | | | | Add a cpu node in the device tree and enable CPU driver. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: Use latest microcode for all BayTrail boardsBin Meng2016-05-23-6574/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | Update board device tree to include latest microcode, and remove the old no longer needed microcode. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
| * | x86: baytrail: Update to latest microcodeBin Meng2016-05-23-0/+6568
| | | | | | | | | | | | | | | | | | | | | | | | Update BayTrail microcde to rev 325 (for CPUID 30673), rev 907 (for CPUID 30679). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: Add some notes for MRC cache with Intel FSPBin Meng2016-05-23-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | MRC cache relies on Intel FSP to produce a special GUID that contains the MRC cache data. Add such information in the CONFIG_ENABLE_MRC_CACHE help entry. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: crownbay: Disable boot stage supportBin Meng2016-05-23-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is observed that when enabling boot stage support, occasionally the board reboots during boot over and over again, and eventually boots to shell. This was seen on my board, but not on Jian's board. Debugging shows that the TSC timer calibration against PIT fails as boot stage APIs utilize timer in a very early stage and at that time TSC/PIT may not be stable enough for the calibration to pass. Disable it for now. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Cc: Jian Luo <Jian.Luo4@boschrexroth.de> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | acpi: Clean IASL generated intermediate filesBin Meng2016-05-23-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For boards that support ACPI, there are dsdt.aml, dsdt.asl.tmp and dsdt.c in the board directory after a successful build. These are intermediate files generated by IASL, and should be removed during a 'make clean'. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-11-15 06:05:52 +0000