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| * | Refactor OneNAND IPL codeKyungmin Park2009-09-28-20/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Refactoring the OneNAND IPL code and some minor fixed: - Remove unnecessary header file - Fix wrong access at read interrupt - The recent OneNAND has 4KiB pagesize Also Board can override OneNAND IPL image Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
| * | MIPS: VCT: Remove read_spareram referenceShinya Kuribayashi2009-09-28-1/+0
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The commit ecad289fc6bd9d89ef4d5093cc7b6fd712fd0d29 (OneNAND: Remove unused read_spareram and add unlock_all as kernel does) forgot to remove a local reference to read_spareram in board/micronas/vct/ebi_onenand.c, which causes the following build failure when configured with OneNAND: ebi_onenand.c: In function 'onenand_board_init': ebi_onenand.c:196: error: 'struct onenand_chip' has no member named 'read_spareram' make[1]: *** [ebi_onenand.o] Error 1 make[1]: *** Waiting for unfinished jobs.... make: *** [board/micronas/vct/libvct.a] Error 2 Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com> Acked-by: Stefan Roese <sr@denx.de> Cc: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-ubiWolfgang Denk2009-09-30-1/+1
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| * | ubifs: Correct dereferencing of files-after-symlinksSimon Kagstrom2009-09-28-1/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Files in directories which are symlinked to were not dereferenced correctly in last commit. E.g., with a symlink /boot/lnk -> /boot/real_dir loading /boot/lnk/uImage will fail. This patch fixes that by simply seeing to it that the target base directory has a slash after it. Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net> Signed-off-by: Stefan Roese <sr@denx.de>
* | Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk2009-09-30-1388/+1358
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| * | ppc4xx: Remove mtsdram0() marcos and use common mtsdram() insteadStefan Roese2009-09-28-22/+20
| | | | | | | | | | | | | | | | | | Additionally some whitespace coding style fixes. Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: Convert PPC4xx SDRAM defines from lower case to upper caseStefan Roese2009-09-28-357/+341
| | | | | | | | | | | | | | | | | | | | | | | | | | | The latest PPC4xx register cleanup patch missed some SDRAM defines. This patch now changes lower case UIC defines to upper case. Also some names are changed to match the naming in the IBM/AMCC users manuals (e.g. mem_mcopt1 -> SDRAM0_CFG). Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: Convert PPC4xx UIC defines from lower case to upper caseStefan Roese2009-09-28-1029/+1017
| |/ | | | | | | | | | | | | The latest PPC4xx register cleanup patch missed the UIC defines. This patch now changes lower case UIC defines to upper case. Signed-off-by: Stefan Roese <sr@denx.de>
* | Merge branch 'master' of git://git.denx.de/u-boot-i2cWolfgang Denk2009-09-30-36/+69
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| * | fsl_i2c: Do not generate STOP after read.Joakim Tjernlund2009-09-28-5/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | __i2c_read always ends with a STOP condition thereby releasing the bus. It is cleaner to do the STOP magic in i2c_read(), like i2c_write() does. This may also help future multimaster systems which wants to hold on to the bus until all transactions are finished. Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
| * | fsl_i2c: Impl. AN2919, rev 5 to calculate FDR/DFSRJoakim Tjernlund2009-09-28-35/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | The latest AN2919 has changed the way FDR/DFSR should be calculated. Update the driver according to spec. However, Condition 2 is not accounted for as it is not clear how to do so. Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Acked-by: Wolfgang Grandegger <wg@grandegger.com>
| * | fsl_i2c: Add CONFIG_FSL_I2C_CUSTOM_{DFSR/FDR}Joakim Tjernlund2009-09-28-3/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | Some boards need a higher DFSR value than the spec currently recommends so give these boards the means to define there own. For completeness, add CONFIG_FSL_I2C_CUSTOM_FDR too. Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
| * | fsl_i2c: Wait for STOP condition to propagateJoakim Tjernlund2009-09-28-4/+8
| |/ | | | | | | | | | | | | | | | | | | | | | | | | After issuing a STOP one must wait until the STOP has completed on the bus before doing something new to the controller. Also add an extra read of SR as the manual mentions doing that is a good idea. Remove surplus write of CR just before a write, isn't required and could potentially disturb the I2C bus. Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc83xxWolfgang Denk2009-09-30-148/+292
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| * | mpc83xx: retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfieldsKim Phillips2009-09-26-123/+188
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | some LCRR bits are not documented throughout the 83xx family RMs. New board porters copying similar board configurations might omit setting e.g., DBYP since it was not documented in their SoC's RM. Prevent them bricking their board by retaining power on reset values in bit fields that the board porter doesn't explicitly configure via CONFIG_SYS_<registername>_<bitfield> assignments in the board config file. also move LCRR assignment to cpu_init_r[am] to help ensure no transactions are being executed via the local bus while CLKDIV is being modified. also start to use i/o accessors. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * | sbc8349: tidy up Makefile to use new configuration script.Paul Gortmaker2009-09-25-14/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 804d83a5 allows us to move all the configuration variation tweaks out of the top level Makefile and down into the board config header. This takes advantage of that for the sbc8349 board. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * | mpc83xx: mpc8360emds: Add QE USB device tree fixupsAnton Vorontsov2009-09-25-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | With this patch we can change QE USB mode without need to hand-edit the device tree. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * | mpc83xx: mpc8360emds: Use RGMII-ID mode, add workarounds for rev. 2.1 CPUsAnton Vorontsov2009-09-25-8/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes various ethernet issues with gigabit links handling in U-Boot. The workarounds originally implemented by Kim Phillips for Linux kernel. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * | mpc83xx: mpc8360emds: Don't use LBC SDRAM when DDR is availableAnton Vorontsov2009-09-25-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit 5c2ff323a94e27e481f70c44838d43fcd844dd46 ("mpc8360emds: rework LBC SDRAM setup"), LBC SDRAM is available for use in Linux. Though, it appears that QE Ethernet in Gigabit mode can't transmit large packets when it tries to work with a data in LBC SDRAM (memtest didn't discover any issues, is LBC SDRAM just too slow?). With this patch we can still use the board without DDR memory, but if DDR is available, we don't use LBC SDRAM. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * | net: uec: Fix uccf.h and uec.h headers to include headers they depend onAnton Vorontsov2009-09-25-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | Headers should include headers containing prototypes and defines they depend on, don't assume that they're included by somebody else. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * | net: uec_phy: Implement TXID and RXID RGMII modes for Marvell PHYsAnton Vorontsov2009-09-25-2/+14
| |/ | | | | | | | | | | | | This will be needed for MPC8360E-MDS boards with rev. 2.1 CPUs. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-fdtWolfgang Denk2009-09-30-8/+15
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| * cmd_fdt.c: fix parse of byte streams and stringsKen MacLeod2009-09-24-8/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 4abd844d8e extended the fdt command parser to handle property strings which are split across multiple arguments but it was broken for byte streams and strings. Byte stream parsing: * Fixes where it would terminate early or go into an endless loop. * Fixes a 0x00 being inserted into the data if there is a space after '[' or a separate argument. * Fixes dereferencing the argument pointer after the last argument. * Checks for bad characters. String parsing: * Treat multiple arguments as a string list. This fixes an issue where only the last argument was stored. Signed-off-by: Ken MacLeod <ken@bitsko.slc.ut.us>
* | mpc5121ads: fix breakage introduced when reordering elpida_mddrc_config[]Wolfgang Denk2009-09-25-1/+1
|/ | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* mucmc52, uc101: delete ata@3a00 node, if no CF card is detectedHeiko Schocher2009-09-25-0/+41
| | | | | | | | | | | U-Boot can detect if an IDE device is present or not. If not, and this new config option is activated, U-Boot removes the ATA node from the DTS before booting Linux, so the Linux IDE driver does not probe the device and crash. This is needed for buggy hardware (uc101) where no pull down resistor is connected to the signal IDE5V_DD7. Signed-off-by: Heiko Schocher <hs@denx.de>
* mpc5200, mucmc52, uc101: config cleanupHeiko Schocher2009-09-25-504/+404
| | | | | | | | | | | | | | - As these boards are similiar, collect common config options in manroland/common.h and manroland/mpc52xx-common.h for mpc5200 specific common options for this manufacturer. - add OF support - update default environment Signed-off-by: Heiko Schocher <hs@denx.de> Minor edit of commit message. Signed-off-by: Wolfgang Denk <wd@denx.de>
* Fix "ppc/85xx: Clean up use of LAWAR defines" breakageWolfgang Denk2009-09-25-1/+1
| | | | | | | | | Commit 002741ae86 modified include/asm-ppc/mmu.h such that the LAWAR_ defines were only enabled for the 83xx platform, but they are also needed on MPC512x system. Enabling these for E300 systems seems thus more appropriate. Signed-off-by: Wolfgang Denk <wd@denx.de>
* Add Elpida Memory Configuration to mpc5121ads BoardsMartha M Stan2009-09-25-4/+130
| | | | | | | | Signed-off-by: Martha M Stan <mmarx@silicontkx.com> Minor coding style cleanup. Signed-off-by: Wolfgang Denk <wd@denx.de>
* mpc512x: Streamlined fixed_sdram() init sequence.Martha M Stan2009-09-25-82/+109
| | | | | | | | | | | | | | | | | | | Signed-off-by: Martha M Stan <mmarx@silicontkx.com> Minor cleanup: Re-ordered default_mddrc_config[] to have matching indices. This allows to use the same index "N" for source and target fields; before, we had code like this out_be32(&im->mddrc.ddr_time_config2, mddrc_config[3]); which always looked like a copy & paste error because 2 != 3. Also, use NULL when meaning a null pointer. Signed-off-by: Wolfgang Denk <wd@denx.de>
* Merge branch 'master' of /home/wd/git/u-boot/custodiansWolfgang Denk2009-09-24-774/+1559
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| * ppc/p4080: Determine various chip frequencies on CoreNet platformsKumar Gala2009-09-24-4/+133
| | | | | | | | | | | | | | | | | | | | The means to determine the core, bus, and DDR frequencies are completely new on CoreNet style platforms. Additionally on p4080 we can have different frequencies for FMAN and PME IP blocks. We need to keep track of the FMAN & PME frequencies since they are used for time stamping capabilities inside each block. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * ppc/p4080: Handle timebase enabling and frequency reportingKumar Gala2009-09-24-1/+22
| | | | | | | | | | | | | | | | | | On CoreNet style platforms the timebase frequency is the bus frequency defined by 16 (on PQ3 it is divide by 8). Also on the CoreNet platforms the core not longer controls the enabling of the timebase. We now need to enable the boot core's timebase via CCSR register writes. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * ppc/p4080: Add various p4080 related defines (and p4040)Kumar Gala2009-09-24-2/+15
| | | | | | | | | | | | | | | | | | | | | | There are various locations that we have chip specific info: * Makefile for which ddr code to build * Added p4080 & p4040 to cpu_type_list and SVR list * Added number of LAWs for p4080 * Set CONFIG_MAX_CPUS to 8 for p4080 Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * ppc/p4080: CoreNet platfrom style secondary core releaseKumar Gala2009-09-24-3/+65
| | | | | | | | | | | | | | | | | | The CoreNet platform style of bringing secondary cores out of reset is a bit different that the PQ3 style. Mostly the registers that we use to setup boot translation, enable time bases, and boot release the cores have moved around. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * ppc/p4080: CoreNet platfrom style CCSRBAR settingKumar Gala2009-09-24-18/+54
| | | | | | | | | | | | | | | | On CoreNet based platforms the CCSRBAR address is split between an high & low register and we no longer shift the address. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * ppc/p4080: Add support for CoreNet style platform LAWsKumar Gala2009-09-24-11/+146
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On CoreNet based platforms the LAW address is split between an high & low register and we no longer shift the address. Also, the target IDs on CoreNet platforms have been completely re-assigned. Additionally, added a new find_law() API to which LAW an address hits in. This is need for the CoreNet style boot release code since it will need to determine what the target ID should be set to for boot window translation. Finally, enamed LAWAR_EN to LAW_EN and moved to header so we can use it elsewhere. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * ppc/p4080: Add p4080 platform immap definitionsKumar Gala2009-09-24-20/+271
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The p4080 SoC has a significant amount of commonality with the 85xx/PQ3 platform. We reuse the 85xx immap and just add new definitions for local access and global utils. The global utils is now broken into global utils, clocking and run control/power management. The offsets from CCSR for a number of blocks have also changed. We introduce the CONFIG_FSL_CORENET define to distinquish the PQ3 style of platform from the new p4080 platform. We don't use QoirQ as there are products (like p2020) that are PQ3 based platforms but have the QoirQ name. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * ppc/85xx: Fix enabling of L2 cacheKumar Gala2009-09-24-3/+4
| | | | | | | | | | | | | | We need to flash invalidate the locks in addition to the cache before we enable. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * 85xx-fdt: Fixed l2-ctlr's compatible prop for QorIQVivek Mahajan2009-09-24-3/+10
| | | | | | | | | | | | | | | | The code assumed names where just numbers and always prefixed 'mpc'. However newer QorIQ don't follow the mpc naming scheme. Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * ppc/85xx: add cpu init config file for boot from NANDMingkai Hu2009-09-24-0/+63
| | | | | | | | | | | | | | | | | | When boot from NAND, the NAND flash must be connected to br/or0. Also init RAM(L2 SRAM or DDR SDRAM) for load the second image to it. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * immap_85xx: add porpllsr's plat ratio definitionMingkai Hu2009-09-24-0/+2
| | | | | | | | | | Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * ppc/85xx: add ld script file for boot from NANDMingkai Hu2009-09-24-0/+67
| | | | | | | | | | | | | | | | | | The first stage 4K image uses a seperate ld script file to generate 4K image. This patch moves it to the cpu/mpc85xx/* to make it avaliable for 85xx platform. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * mpc8610hpcd: Use common 86xx fdt fixup codePeter Tyser2009-09-24-13/+1
| | | | | | | | | | | | | | | | Using the common 86xx fdt fixups removes some board-specific code and should make the mpc8610hpcd easier to maintain in the long run. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * sbc85x0: tidy up Makefile to use new configuration script.Paul Gortmaker2009-09-24-29/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | Commit 804d83a5 allows us to move all the configuration variation tweaks out of the top level Makefile and down into the boards config header. This takes advantage of that for the sbc8540/sbc8560 boards. There were a couple of cheezy comments pointing at incorrect files, or files that don't exist, so I've cleaned those up too. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * sbc8548: allow enabling PCI via a make config optionPaul Gortmaker2009-09-24-12/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Prior to this commit, to enable PCI, you had to go manually edit the board config header, and if you had 33MHz PCI, you had to manually change CONFIG_SYS_NS16550_CLK too, which was not real user friendly, This adds the typical PCI and clock speed make targets to the toplevel Makefile in accordance with what is being done with other boards (i.e. using the "-t" to mkconfig). Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * sbc8548: update PCI/PCI-e support codePaul Gortmaker2009-09-24-143/+96
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PCI/PCI-e support for the sbc8548 was based on an earlier version of what the MPC8548CDS board was using, and in its current state it won't even compile. This re-syncs it to match the latest codebase and makes use of the new shared PCI functions to reduce board duplication. It borrows from the MPC8568MDS, in that it pulls the PCI-e I/O back to 0xe280_0000 (where PCI2 would be on MPC8548CDS), and similarly it coalesces the PCI and PCI-e mem into one single TLB. Both PCI-x and PCI-e have been tested with intel e1000 cards under linux (with an accompanying dts change in place) Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * fsl_pci: create a SET_STD_PCI_INFO() helper wrapperPaul Gortmaker2009-09-24-0/+12
| | | | | | | | | | | | | | | | Recycle the recently added PCI-e wrapper used to reduce board duplication of code by creating a similar version for plain PCI. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * sbc8548: correct local bus SDRAM size from 64M to 128MPaul Gortmaker2009-09-24-12/+61
| | | | | | | | | | | | | | | | | | | | | | The size of the LB SDRAM on this board is 128MB, spanning CS3 and CS4. It was previously only being configured for 64MB on CS3, since that was what the original codebase of the MPC8548CDS had. In addition to setting up BR4/OR4, this also adds the TLB entry for the second half of the SDRAM. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * sbc8548: use I/O accessorsPaul Gortmaker2009-09-24-46/+45
| | | | | | | | | | | | | | | | Sweep throught the board specific file and replace the various register proddings with the equivalent I/O accessors. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * sbc8548: remove eTSEC3/4 voltage hackPaul Gortmaker2009-09-24-6/+0
| | | | | | | | | | | | | | | | With only eTSEC1 and 2 being brought out to RJ-45 connectors, we aren't interested in the eTSEC3/4 voltage hack on this board Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
generated by cgit v1.1 at 2024-11-07 18:36:29 +0000