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* sunxi: Use binman for sunxi boardsSimon Glass2016-12-20-6/+18
| | | | | | | | Move sunxi boards to use binman. This involves adding the image definition to the device tree and using it in the Makefile. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* tegra: Use a U-Boot-specific .dtsi fileSimon Glass2016-12-20-4/+23
| | | | | | | | With the new device-tree rules it is possible to put device-tree changes needed by U-Boot into their own file. As an example of this approach, move Tegra over to use it. Signed-off-by: Simon Glass <sjg@chromium.org>
* binman: Automatically include a U-Boot .dtsi fileSimon Glass2016-12-20-1/+58
| | | | | | | | | | | | | | | | | | | | | | For boards that need U-Boot-specific additions to the device tree, it is a minor annoyance to have to add these each time the tree is synced with upstream. Add a means to include a file (e.g. u-boot.dtsi) automatically into the .dts file before it is compiled. The file uses is the first one that exists in this list: arch/<arch>/dts/<board.dts>-u-boot.dtsi arch/<arch>/dts/<soc>-u-boot.dtsi arch/<arch>/dts/<cpu>-u-boot.dtsi arch/<arch>/dts/<vendor>-u-boot.dtsi arch/<arch>/dts/u-boot.dtsi Signed-off-by: Simon Glass <sjg@chromium.org> Suggested-by: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* binman: Allow configuration options to be used in .dts filesSimon Glass2016-12-20-0/+5
| | | | | | | | | It is sometimes useful to be able to reference configuration options in a device tree source file. Add the necessary includes so that this works. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* binman: Add a build rule for binmanSimon Glass2016-12-20-0/+6
| | | | | | | | | Add a standard command definition for binman so that it can be used in makefiles. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* binman: Add support for building x86 images with FSP/CMCSimon Glass2016-12-20-0/+74
| | | | | | | | Add support for two more from the inexhaustible supply of x86 binary blob types. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* binman: Add support for building x86 ROMs with SPLSimon Glass2016-12-20-1/+315
| | | | | | | | When building for 64-bit x86 we need an SPL binary in the ROM. Add support for this. Also increase entry test code coverage to 100%. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* binman: Add support for u-boot.img as an input binarySimon Glass2016-12-20-0/+33
| | | | | | | Add an entry type for u-boot.img (a legacy U-Boot image) and a simple test. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* binman: Add support for building x86 ROMsSimon Glass2016-12-20-3/+760
| | | | | | | | | | | | The structure of x86 ROMs is pretty complex. There are various binary blobs to place in the image. Microcode requires special handling so that it is available to very early code and can be used without any memory whatsoever. Add support for the various entry types that are currently needed, along with some tests. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* binman: Add basic entry types for U-BootSimon Glass2016-12-20-0/+1080
| | | | | | | | Add entries to support some standard U-Boot binaries, such as u-boot.bin, u-boot.dtb, etc. Also add some tests for these. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* binman: Introduce binman, a tool for building binary imagesSimon Glass2016-12-20-0/+1255
| | | | | | | | | | | | | This adds the basic code for binman, including command parsing, processing of entries and generation of images. So far no entry types are supported. These will be added in future commits as examples of how to add new types. See the README for documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2016-12-16-176/+95
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| * Revert "sf: Fix quad bit set for micron devices"Cyrille Pitchen2016-12-15-63/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit c56ae7519f141523ba1248b22b5b5169b21772fe. Once the 'Quad Enable' bit is cleared in their Enhanced Volatile Configuration Register (EVCR), Micron memories expect ALL commands to use the SPI 4-4-4 protocol. Commands using SPI 1-y-z protocols are no longer accepted. Within the reverted commit, the write_evcr() function is implemented using the spi_flash_write_common(), which is a shortcut for the [ spi_flash_cmd_write_enable(), spi_flash_cmd_write(), spi_flash_cmd_wait_ready() ] sequence. Since the internal state of the Micron memory has been changed when the spi_flash_cmd_write() function completes, the later call of the spi_flash_cmd_wait_ready() function fails. Indeed the SPI controller driver is not aware of the SPI protocol switch. Further patches will fix the support of Micron QSPI memories. Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> [Rebase on master, use JEDEC_MFR(info) in place of idcode0] Signed-off-by: Jagan Teki <jagan@openedev.com>
| * sf: Do not force the DT memory map size to exactly match the devicePhil Edworthy2016-12-15-1/+1
| | | | | | | | | | | | | | | | | | As long as the memory mapped size specifeid in the DT is the same or bigger than the device size, it will work. So do not force the sizes to be identical. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * mtd: spi: don't return -1 when scan succeedFabien Parent2016-12-15-2/+2
| | | | | | | | | | | | | | | | | | | | In spi_flash_scan, 'ret' is initialled to -1, but 'ret' is not always used to store a return value, in that case, even when the function succeed, an error (-1) will be returned. Lets just return 0 if we hit the end of the function. Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * spi: cadence_qspi: Move DT prop code to match layoutPhil Edworthy2016-12-15-1/+1
| | | | | | | | | | | | | | | | Move the code to read the "sram-size" property into the other code that reads properties from the node, rather than the SF subnode. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * spi: cadence_qspi: Fix CS timingsPhil Edworthy2016-12-15-11/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The Cadence QSPI controller has specified overheads for the various CS times that are in addition to those programmed in to the Device Delay register. The overheads are different for the delays. In addition, the existing code does not handle the case when the delay is less than a SCLK period. This change accurately calculates the additional delays in Ref clocks. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * spi: cadence_qspi: Remove returns from end of void functionsPhil Edworthy2016-12-15-8/+0
| | | | | | | | | | | | Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Acked-by: Marek Vasut <marek.vasut@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * spi: cadence_qspi: Use spi mode at the point it is neededPhil Edworthy2016-12-15-9/+5
| | | | | | | | | | | | | | | | Instead of extracting mode settings and passing them as separate args to another function, just pass the SPI mode as an arg. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * spi: cadence_qspi: Clean up the #define namesPhil Edworthy2016-12-15-43/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | A lot of the #defines are for single bits in a register, where the name has _MASK on the end. Since this can be used for both a mask and the value, remove _MASK from them. Whilst doing so, also remove the unnecessary brackets around the constants. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Acked-by: Marek Vasut <marek.vasut@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * spi: cadence_qspi: Use #define for bits instead of bit shiftsPhil Edworthy2016-12-15-18/+19
| | | | | | | | | | | | | | | | | | | | | | | | Most of the code already uses #defines for the bit value, rather than the shift required to get the value. This changes the remaining code over. Whislt at it, fix the names of the "Rd Data Capture" register defs. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Acked-by: Marek Vasut <marek.vasut@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * spi: cadence_qspi: Better debug information on the SPI clock ratePhil Edworthy2016-12-15-3/+3
| | | | | | | | | | | | | | | | Show what the output clock rate actually is. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Acked-by: Marek Vasut <marek.vasut@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * spi: cadence_qspi: Fix baud rate calculationPhil Edworthy2016-12-15-16/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | With the existing code, when the requested SPI clock rate is near to the lowest that can be achieved by the hardware (max divider of the ref clock is 32), the generated clock rate is wrong. For example, with a 50MHz ref clock, when asked for anything less than a 1.5MHz SPI clock, the code sets up the divider to generate 25MHz. This change fixes the calculation. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * spi: cadence_qspi: Fix clearing of pol/pha bitsPhil Edworthy2016-12-15-2/+2
| | | | | | | | | | | | | | | | Or'ing together bit positions is clearly wrong. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Acked-by: Marek Vasut <marek.vasut@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * spi: Add error checking for invalid bus widthsSimon Glass2016-12-15-2/+2
| | | | | | | | | | | | | | | | | | | | At present an invalid bus width prints a message but does not return an error. This is the opposite of the correct behaviour. Adjust it to avoid code bloat in the common case, and avoid hard-to-debug failure in the uncommon case. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * ARM: dts: am437x-idk: Fix QSPI compatible stringVignesh R2016-12-15-1/+1
| | | | | | | | | | | | | | | | | | | | Unlike Linux kernel, U-Boot depends on "spi-flash" compatible to probe m25p80 spi-nor devices. Hence, add "spi-flash" compatible string to m25p80 node. Without this patch, flash device DT data is not parsed and QSPI operates in unsupported mode leading to data corruption. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* | Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-12-16-36/+624
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| * | ARMv8: LS1043A: Enable LS1043A default PSCI supportmacro.wave.z@gmail.com2016-12-15-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A most basic PSCI implementation with only one psci_version is added for LS1043A, this can verify the generic PSCI framework, and more platform specific implementation will be added later. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | ARMv8: Setup PSCI memory and device treemacro.wave.z@gmail.com2016-12-15-5/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | Newly add ARMv8 PSCI needs to be initialized, be copied or reserved in right place, this patch does all the setup steps. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | ARMv8: Add basic PSCI frameworkmacro.wave.z@gmail.com2016-12-15-0/+312
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces a generic ARMv8 PSCI framework, with all functions returning a dummy ARM_PSCI_RET_NI (Not Implemented), then it is up to each platform to implement their own functions based on this framework. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | ARMv8: Enable SMC instructionmacro.wave.z@gmail.com2016-12-15-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | PSCI implementation needs the SMC instruction to be enabled. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | ARMv8: Add secure sections for PSCI text and datamacro.wave.z@gmail.com2016-12-15-1/+91
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds secure_text, secure_data and secure_stack sections for ARMv8 to hold PSCI text and data, and it is based on the legacy implementation of ARMv7. ARMV8_SECURE_BASE defines the address for PSCI secure sections, ARMV8_PSCI and ARMV8_PSCI_NR_CPUS are firstly used in this patch, so they are introduce here in Kconfig too. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | ARMv8: LS1043A: change macro CONFIG_ARMV8_PSCI definitionmacro.wave.z@gmail.com2016-12-15-9/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | NXP/Freescale uses macro CONFIG_ARMV8_PSCI to enable their private PSCI implementation in PPA firmware, but this macro naming too generic, so this patch replaces it with a specic one CONFIG_FSL_PPA_ARMV8_PSCI. And this macro CONFIG_ARMV8_PSCI will be used for a generic PSCI for ARMv8 which will be added in following patchs. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | driver: fsl-mc: qbman: Add QBMAN 4.1 supportPriyanka Jain2016-12-15-13/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS2080A SoC family has QBMAN ver 4.0 whereas newer SoCs like LS2088A, LS1088A has QBMAN ver 4.1 QBMAN ver 4.0 and ver 4.1 supports dqrr size as 4 and 8 respectively. Add support of to check QBMAN version based on SoC SVR update dqrr_size accordingly update code to support larger dqrr_size Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: ls1043a: dts: Fix the ranges table of IFC nodeHou Zhiqiang2016-12-15-8/+8
| | | | | | | | | | | | | | | | | | | | | Corrected the ranges table of the IFC node. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: ls1043ardb: dts: Fix the unit-address of some I2C device nodesHou Zhiqiang2016-12-15-2/+2
| | | | | | | | | | | | | | | | | | | | | The unit-address should be the same as the I2C address of the device. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | fsl/board/ddr: optimize board-specific cpo for erratum A-009942Shengzhou Liu2016-12-15-0/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Optimize board-specific cpo for erratum A-009942 on b4860qds, ls1043aqds, ls1043ardb, ls1046aqds, ls1046ardb, ls2080ardb, t102xqds, t102xrdb, t1040qds, t104xrdb, t208xqds, t208xrdb, t4qds, t4rdb boards. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | fsl/ddr: Enable erratum-a009942 workaround for B/T-seriesShengzhou Liu2016-12-15-0/+5
| |/ | | | | | | | | | | | | Enable ERRATUM_A009942 workaround for B-series and T-series platforms. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | Kconfig: Move USE_ARCH_MEMCPY/MEMSET to KconfigFabio Estevam2016-12-16-25/+18
| | | | | | | | | | | | | | | | | | Move USE_ARCH_MEMCPY/MEMSET options to Kconfig. Make it "default y" for the ARMv7 architecture and make it depend on !ARM64 && !SPL. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
* | travis-ci: Add zynq_zc702 target supportMichal Simek2016-12-14-0/+6
|/ | | | | | It depends on qemu v2.8.0-rc3 which includes device loader property. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* MAINTAINERS: DFU: Change e-mail address for DFU maintainerLukasz Majewski2016-12-12-1/+1
| | | | | | | Despite I leave Samsung by the end of the year, I'm going to maintain DFU in u-boot. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
* MAINTAINERS: ONENAND: MTD: Mark Samsung's OneNAND as orphanedLukasz Majewski2016-12-12-2/+2
| | | | | | | | | Since I leave Samsung by the end of the year, I will not have access to OneNAND devices anymore. Hence the custodian position has been marked as "Orphaned". Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
* Merge git://www.denx.de/git/u-boot-marvellTom Rini2016-12-12-64/+1800
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| * arm64: mvebu: Enable hush parser in A8K default configurationKonstantin Porotchkin2016-12-12-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable hush parser in Armada-7040 and Armada-8040 DB default configurations. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * arm64: mvebu: Enable PCIe support in Armada-7040 configurationKonstantin Porotchkin2016-12-12-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable PCIe bus support in Armada-7040 DB default configuration Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * arm64: mvebu: Add L3 cache flush functionality to A8K familyKonstantin Porotchkin2016-12-12-0/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add missing L3 cache flush functionality which absence prevents Linux kernel from normal boot in case the L3 cache is enabled by ATF. The L3 cache is named the "last level" cache in order to keep the terminology similar to the ATF code. This cache should not be disabled by u-boot since the Linux kernel cannot activate it, so it is activates at ATF stage. However the cache flush is required for preventing data corruption after disabling the MMU and the data cache before passing control to the loaded Linux image. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * arm64: mvebu: Enable pin control support in A8K default configKonstantin Porotchkin2016-12-12-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable mvebu pin control support in the default configuration files for Armada-7040 and Armada-8040 development boards Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * arm64: mvebu: Enable BUBT command support in A8K default configKonstantin Porotchkin2016-12-12-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable mvebu "bubt" command support in the default configuration file for Armada-7040 and Armada-8040 development boards Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * arm64: mvebu: Add pin control nodes to A8K family DTS filesKonstantin Porotchkin2016-12-12-22/+183
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add pin control nodes to APN806, CP-master, CP-slave and Armada-7040 and Armada-8040 boards DTS files Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * arm64: mvebu: pinctrl: Add pin control driver for A8K familyKonstantin Porotchkin2016-12-12-0/+651
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a DM port of Marvell pin control driver. The A8K SoC family contains several silicone dies interconnected in a single package. Every die is normally equipped with its own pin controller unit. There are 2 pin controllers in A70x0 SoC and 3 in A80x0 SoC. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
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