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* ARM: uniphier: rework UniPhier SoC select in KconfigMasahiro Yamada2016-02-29-39/+30
| | | | | | | | | | The chains of "depends on <SoC_name>" in the current Kconfig is clumsy. The idea here is to allow users to choose a SoC group first (SoC group consists of some SoCs that can coexist in one binary). Then, allow to enable/disable each SoC support in the selected SoC group. This makes the Kconfig menu clearer. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: merge two defconfig filesMasahiro Yamada2016-02-29-35/+3
| | | | | | | | PH1-Pro5 support and ProXstream2/PH1-LD6b support can coexist in one image and there is bit more room in SPL to accommodate all of them. Merge uniphier_pro5_defconfig into uniphier_pxs2_defconfig. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: rename variable for DRAM controller base addressMasahiro Yamada2016-02-29-114/+113
| | | | | | Rename the variable that contains the base address for consistency. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: deprecate umc_dram_init_{start, poll}Masahiro Yamada2016-02-29-23/+18
| | | | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: remove unused macros for UMC base addressesMasahiro Yamada2016-02-29-11/+0
| | | | | | | These macros are no longer used. These base addresses are SoC-dependent, so they should not be placed in the header. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: rework DRAM size handling in UMC init codeMasahiro Yamada2016-02-29-15/+15
| | | | | | | | | Currently, DRAM size is converted twice: size in byte -> size in Gbit -> enum Optimize the code by converting the "size in byte" into enum directly. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: optimize PH1-Pro4 UMC init code with "for" loopMasahiro Yamada2016-02-29-55/+59
| | | | | | | Now this code can be re-written with a "for" statement instead of calling the same function multiple times. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: optimize PH1-LD4 UMC init code with "for" loopMasahiro Yamada2016-02-29-41/+49
| | | | | | | Now this code can be re-written with a "for" statement instead of calling the same function multiple times. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: optimize PH1-sLD8 UMC init code with "for" loopMasahiro Yamada2016-02-29-40/+43
| | | | | | | Now this code can be re-written with a "for" statement instead of calling the same function multiple times. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: refactor UMC init code for PH1-LD4Masahiro Yamada2016-02-29-24/+55
| | | | | | Move frequency-dependent register settings to arrays for clean-up. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: support more DRAM use cases for PH1-sLD8Masahiro Yamada2016-02-29-6/+40
| | | | | | Support DDR3-1600 / 512MB DDR size. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: refactor UMC init code for PH1-sLD8Masahiro Yamada2016-02-29-8/+29
| | | | | | Move frequency-dependent register settings to arrays for clean-up. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: refactor DDR-PHY init codeMasahiro Yamada2016-02-29-30/+40
| | | | | | | The if-else statements for the frequency-dependent register settings seem clumsy. Moving them to arrays would make it cleaner. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: remove unused argument of ph1_ld4_ddrphy_init()Masahiro Yamada2016-02-29-16/+10
| | | | | | | The DDR PHY settings no longer depend on the DRAM size. Drop the argument from the init function. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: merge DDR PHY init code for 3 SoCsMasahiro Yamada2016-02-29-167/+14
| | | | | | | | Now these three are almost the same. The only difference is the DTPR1 register dependency on the DRAM size, but it can be ignored. (It has already been ignored in PH1-sLD8 and PH1-Pro4.) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: add a field to specify DDR3+Masahiro Yamada2016-02-29-35/+44
| | | | | | | | | | | | | Add a field to distinguish DDR3+ from (standard) DDR3. It also allows to delete CONFIG_DDR_STANDARD (this is not a software configuration, but a board attribute). Default DDR3 spec for each SoC: PH1-LD4, PH1-sLD8: DDR3+ Others: DDR3 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: disable debug circuit clocks for PH1-Pro4Masahiro Yamada2016-02-29-2/+2
| | | | | | | These settings control the clocks around the memory controller. The debug ability is unneeded once it works properly. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: remove UMC_INITCTL* and UMC_DRMR* settingsMasahiro Yamada2016-02-29-60/+0
| | | | | | | | These settings were used only for the PH1-sLD3 and older SoCs. The PH1-LD4 and newer one just ignore them because their DDR-PHY take care of such timing parameters instead. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: refactor UMC init code for ProXstream2Masahiro Yamada2016-02-29-45/+64
| | | | | | | | | | | | | | | | | Currently, a dummy value is defined for the UMC_SPCCTLA register when the DRAM size is zero. This seems weird because the controller does not need setting in the first place if the size is zero. Also, redefine enum dram_size to represent the DRAM size per 16-bit unit. This makes things simpler because the channel 0 and 1 are connected with 32-bit width DRAM, while the channel 2 is connected with 16-bit width one. I am renaming SIZE_* into DRAM_SZ_* (and also FREQ_* to DRAM_FREQ_* for consistency) while I am here because SIZE_* might be easily mixed-up with the macros in include/linux/sizes.h. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: use pr_err() where possibleMasahiro Yamada2016-02-29-5/+5
| | | | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: optimize ProXstream2 UMC init code with "for" loopMasahiro Yamada2016-02-29-22/+11
| | | | | | | Now this code can be re-written with a "for" statement instead of calling the same function multiple times. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: rework struct uniphier_board_dataMasahiro Yamada2016-02-29-114/+161
| | | | | | | | This commit reworks "struct uniphier_board_data" with an array of DRAM channel data in it. It will allow further cleanups by means of "for" statements that iterate over the DDR channels. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: remove unused umc_polling()Masahiro Yamada2016-02-29-9/+0
| | | | | | This function is unused. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: default to environment in eMMCMasahiro Yamada2016-02-29-6/+11
| | | | | | | Of the several boot devices supported, it looks like the eMMC is the most commonly used. Enable CONFIG_ENV_IS_IN_MMC by default. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: add emmcupdate commandMasahiro Yamada2016-02-29-0/+21
| | | | | | | | | | | | The Boot ROM expects the boot image (SPL) in the Boot Partition 1. So, updating images involves the hardware partition switch. It might be a bit advanced for some users. To be user-friendly, this commit adds a useful command to update the images; just put SPL and U-Boot proper into the public directory of the TFTP server and execute "run emmcupdate" from the command line. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: add a command to find the first MMC (non-SD) deviceMasahiro Yamada2016-02-29-0/+34
| | | | | | | | | | | UniPhier SoC family supports both (e)MMC boot and SD card boot; however, both of them are handled in the same uclass. When booting from the eMMC, we want to know the device number of the (e)MMC, not SD. This command is useful to find the first MMC (non-SD) device. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: add eMMC boot supportMasahiro Yamada2016-02-29-0/+64
| | | | | | | | Export device nodes needed for eMMC boot (eMMC node, pinctrl, and clock) to the SPL DTB. CONFIG_SUPPORT_EMMC_BOOT is also necessary to use "mmc partconf" command. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: dts: uniphier: add SD/MMC host controller nodesMasahiro Yamada2016-02-29-0/+217
| | | | | | This host controller is available for all UniPhier SoCs. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: enable UniPhier SD/MMC host driverMasahiro Yamada2016-02-29-0/+10
| | | | | | | Enable the driver in all UniPhier defconfig files and add some needed defines to the common files. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* mmc: uniphier: add driver for UniPhier SD/MMC host controllerMasahiro Yamada2016-02-29-0/+759
| | | | | | | Add a driver for the on-chip SD/eMMC host controller used by UniPhier SoC family. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: dts: uniphier: add GPIO controller nodesMasahiro Yamada2016-02-29-0/+938
| | | | | | Make the GPIO driver really active. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: enable GPIO command and driver for UniPhier SoCsMasahiro Yamada2016-02-29-0/+11
| | | | | | | This allows to use the "gpio" command. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org>
* gpio: do not include <asm/arch/gpio.h> for UniPhierMasahiro Yamada2016-02-29-0/+2
| | | | | | | | | I implemented a GPIO driver based on Driver Model for the UniPhier SoC family, but I could not find any good reason why such SoC specific GPIO headers are needed. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org>
* gpio: uniphier: add driver for UniPhier GPIO controllerMasahiro Yamada2016-02-29-0/+155
| | | | | | | This GPIO controller device is used on UniPhier SoCs. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org>
* ARM: dts: uniphier: rework System Bus nodesMasahiro Yamada2016-02-29-19/+20
| | | | | | Follow the changes of DTS in Linux. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* Merge git://git.denx.de/u-boot-usbTom Rini2016-02-26-1/+1
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| * usb: ehci: Fix warning on aarch64Marek Vasut2016-02-26-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the following warning on aarch64 introduced by using p2v/v2p functions in the code: In file included from ./arch/arm/include/asm/byteorder.h:29:0, from include/compiler.h:125, from include/image.h:19, from include/common.h:88, from drivers/usb/host/ehci-hcd.c:10: drivers/usb/host/ehci-hcd.c: In function ‘ehci_td_buffer’: drivers/usb/host/ehci-hcd.c:250:49: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] td->qt_buffer[idx] = cpu_to_hc32(virt_to_phys((void *)addr)); ^ include/linux/byteorder/little_endian.h:34:51: note: in definition of macro ‘__cpu_to_le32’ #define __cpu_to_le32(x) ((__force __le32)(__u32)(x)) ^ drivers/usb/host/ehci-hcd.c:250:24: note: in expansion of macro ‘cpu_to_hc32’ td->qt_buffer[idx] = cpu_to_hc32(virt_to_phys((void *)addr)); Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Tom Rini <trini@konsulko.com>
* | Merge git://git.denx.de/u-boot-dmTom Rini2016-02-26-43/+138
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| * | pci: Fix compiler warnings in dm_pciauto_setup_device()Bin Meng2016-02-26-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the following compiler warnings when DEBUG is on. warning: 'bar_res' may be used uninitialized in this function. drivers/pci/pci_auto.c:101:21: if (!enum_only && pciauto_region_allocate(bar_res, bar_size, ^ Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | spi: Re-enable the SPI flash testsSimon Glass2016-02-26-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | These are working correctly again, so re-enable them. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jteki@openedev.com> Tested-by: Jagan Teki <jteki@openedev.com>
| * | spi: Correct two error return valuesSimon Glass2016-02-26-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When an error number is provided we should use it, not change it. This fixes the SPI and SPI flash tests. One of these is long-standing. The other seems to have been introduced by commit 1e90d9fd (sf: Move read_id code to sf_ops). Signed-off-by: Simon Glass <sjg@chromium.org> Fixes: 1e90d9fd (sf: Move read_id code to sf_ops) Reviewed-by: Jagan Teki <jteki@openedev.com> Tested-by: Jagan Teki <jteki@openedev.com>
| * | sandbox: spi: Remove an incorrect free()Simon Glass2016-02-26-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We must not free data that is managed by driver mode. Remove this line, which is a hangover from the pre-driver-model code. This fixes a problem where 'sf probe' crashes U-Boot if the backing file for the SPI flash cannot be found. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jteki@openedev.com> Tested-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | sandbox: spi: Add more debugging to SPI emulationSimon Glass2016-02-26-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | Add a little more debugging to help when things go wrong. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jteki@openedev.com> Tested-by: Jagan Teki <jteki@openedev.com>
| * | sandbox: Enable the early timerSimon Glass2016-02-26-0/+1
| | | | | | | | | | | | | | | | | | | | | Enable this so that tracing works with sandbox. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | sandbox: Correct ordering of defconfigSimon Glass2016-02-26-5/+5
| | | | | | | | | | | | | | | | | | This has got out of order: fix it. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | sandbox: timer: Support the early timerSimon Glass2016-02-26-3/+15
| | | | | | | | | | | | | | | | | | Add support for the early timer so we can use tracing with sandbox again. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | timer: Set up the real timer after driver model is availableSimon Glass2016-02-26-2/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | When using the early timer, we need to manually trigger setting up the real timer. This will not happen automatically. Do this immediately after starting driver model. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | timer: Provide an early timerSimon Glass2016-02-26-7/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In some cases the timer must be accessible before driver model is active. Examples include when using CONFIG_TRACE to trace U-Boot's execution before driver model is set up. Enable this option to use an early timer. These functions must be supported by your timer driver: timer_early_get_count() and timer_early_get_rate(). Signed-off-by: Simon Glass <sjg@chromium.org>
| * | timer: Support tracing fullySimon Glass2016-02-26-3/+3
| | | | | | | | | | | | | | | | | | | | | A few of the functions in the timer uclass are not marked with 'notrace'. Fix this so that tracing can be used with CONFIG_TRACE. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | trace: Improve the trace test number recognitionSimon Glass2016-02-26-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | The awk tool can be confused by return character (ASCII 13) in its input since it thinks there is a separate field. These can appear if the terminal is in raw mode, perhaps due to a previous U-Boot crash with sandbox. This is very confusing. Remove these so that the trace test passes. Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-12-05 00:48:59 +0000