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* powerpc/85xx: don't display address map size (32-bit vs. 36-bit) during bootTimur Tabi2012-04-24-52/+9
| | | | | | | | | | | | | | | | Most 85xx boards can be built as a 32-bit or a 36-bit. Current code sometimes displays which of these is actually built, but it's inconsistent. This is especially problematic since the "default" build for a given 85xx board can be either one, so if you don't see a message, you can't always know which size is being used. Not only that, but each board includes code that displays the message, so there is duplication. The 'bdinfo' command has been updated to display this information, so we don't need to display it at boot time. The board-specific code is deleted. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* cmd_bdinfo: display the address map size (32-bit vs. 36-bit)Timur Tabi2012-04-24-0/+8
| | | | | | | | | Some Freescale SOCs support 32-bit and 36-bit physical addressing, and U-Boot must be built to enable one or the other. Add this information to the bdinfo command. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* PowerPC: correct the SATA for p1/p2 rdb-pc platformJerry Huang2012-04-24-1/+1
| | | | | | | | For p1/p2 rdb-pc platform, use the PCIe-SATA Silicon Image SATA controller. Therefore, the SATA driver will use sata_sil, instead sata_sil3114. Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> CC: Andy Fleming <afleming@gmail.com>
* powerpc/corenet_ds: Slave core in holdoff when boot from SRIOLiu Gang2012-04-24-0/+135
| | | | | | | | | | | | | | | | | | When boot from SRIO, slave's core can be in holdoff after powered on for some specific requirements. Master can release the slave's core at the right time by SRIO interface. Master needs to: 1. Set outbound SRIO windows in order to configure slave's registers for the core's releasing. 2. Check the SRIO port status when release slave core, if no errors, will implement the process of the slave core's releasing. Slave needs to: 1. Set all the cores in holdoff by RCW. 2. Be powered on before master's boot. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
* powerpc/corenet_ds: Slave reads ENV from master when boot from SRIOLiu Gang2012-04-24-1/+130
| | | | | | | | | | | | | | | | | | | | When boot from SRIO, slave's ENV can be stored in master's memory space, then slave can fetch the ENV through SRIO interface. NOTE: Because the slave can not erase, write master's NOR flash by SRIO interface, so it can not modify the ENV parameters stored in master's NOR flash using "saveenv" or other commands. Master needs to: 1. Put the slave's ENV into it's own memory space. 2. Set an inbound SRIO window covered slave's ENV stored in master's memory space. Slave needs to: 1. Set a specific TLB entry in order to fetch ucode and ENV from master. 2. Set a LAW entry with the TargetID SRIO1 or SRIO2 for ucode and ENV. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
* powerpc/corenet_ds: Slave uploads ucode when boot from SRIOLiu Gang2012-04-24-5/+46
| | | | | | | | | | | | | | | | | When boot from SRIO, slave's ucode can be stored in master's memory space, then slave can fetch the ucode image through SRIO interface. For the corenet platform, ucode is for Fman. Master needs to: 1. Put the slave's ucode image into it's own memory space. 2. Set an inbound SRIO window covered slave's ucode stored in master's memory space. Slave needs to: 1. Set a specific TLB entry in order to fetch ucode from master. 2. Set a LAW entry with the TargetID SRIO1 or SRIO2 for ucode. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
* powerpc/corenet_ds: Slave module for boot from SRIOLiu Gang2012-04-24-0/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For the powerpc processors with SRIO interface, boot location can be configured from SRIO1 or SRIO2 by RCW. The processor booting from SRIO can do without flash for u-boot image. The image can be fetched from another processor's memory space by SRIO link connected between them. The processor boots from SRIO is slave, the processor boots from normal flash memory space and can help slave to boot from its memory space is master. They are different environments and requirements: master: 1. NOR flash for its own u-boot image, ucode and ENV space. 2. Slave's u-boot image in master NOR flash. 3. Normally boot from local NOR flash. 4. Configure SRIO switch system if needed. slave: 1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV. 2. Boot location should be set to SRIO1 or SRIO2 by RCW. 3. RCW should configure the SerDes, SRIO interfaces correctly. 4. Slave must be powered on after master's boot. 5. Must define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE because of no ucode locally. For the slave module, need to finish these processes: 1. Set the boot location to SRIO1 or SRIO2 by RCW. 2. Set a specific TLB entry for the boot process. 3. Set a LAW entry with the TargetID SRIO1 or SRIO2 for the boot. 4. Slave's u-boot image should be generated specifically by make xxxx_SRIOBOOT_SLAVE_config. This will set SYS_TEXT_BASE=0xFFF80000 and other configurations. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
* powerpc/corenet_ds: Master module for boot from SRIOLiu Gang2012-04-24-2/+140
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For the powerpc processors with SRIO interface, boot location can be configured from SRIO1 or SRIO2 by RCW. The processor booting from SRIO can do without flash for u-boot image. The image can be fetched from another processor's memory space by SRIO link connected between them. The processor boots from SRIO is slave, the processor boots from normal flash memory space and can help slave to boot from its memory space is master. They are different environments and requirements: master: 1. NOR flash for its own u-boot image, ucode and ENV space. 2. Slave's u-boot image in master NOR flash. 3. Normally boot from local NOR flash. 4. Configure SRIO switch system if needed. slave: 1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV. 2. Boot location should be set to SRIO1 or SRIO2 by RCW. 3. RCW should configure the SerDes, SRIO interfaces correctly. 4. Slave must be powered on after master's boot. For the master module, need to finish these processes: 1. Initialize the SRIO port and address space. 2. Set inbound SRIO windows covered slave's u-boot image stored in master's NOR flash. 3. Master's u-boot image should be generated specifically by make xxxx_SRIOBOOT_MASTER_config 4. Master must boot first, and then slave can be powered on. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
* powerpc/corenet_ds: Document for the boot from SRIOLiu Gang2012-04-24-0/+103
| | | | | | | | | This document describes the implementation of the boot from SRIO, includes the introduction of envionment, an example based on P4080DS platform, an example of the slave's RCW, and the description about how to use this feature. Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
* powerpc/corenet_ds: Correct the compilation errors about ENVLiu Gang2012-04-24-0/+2
| | | | | | | | | | | | | | | | | | | | | | When defined CONFIG_ENV_IS_NOWHERE, there will be some compilation errors: ./common/env_nowhere.o: In function `env_relocate_spec': ./common/env_nowhere.c:38: multiple definition of `env_relocate_spec' ./common/env_flash.o: ./common/env_flash.c:326: first defined here ./common/env_nowhere.o: In function `env_get_char_spec': ./common/env_nowhere.c:42: multiple definition of `env_get_char_spec' ./common/env_flash.o:./common/env_flash.c:78: first defined here ./common/env_nowhere.o: In function `env_init': ./common/env_nowhere.c:51: multiple definition of `env_init' ./common/env_flash.o:./common/env_flash.c:237: first defined here make[1]: *** [./common/libcommon.o] Error 1 make[1]: Leaving directory `./common' make: *** [./common/libcommon.o] Error 2 Remove the CONFIG_ENV_IS_IN_FLASH if defined CONFIG_ENV_IS_NOWHERE. Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
* powerpc/srio: Rewrite the struct ccsr_rioLiu Gang2012-04-24-160/+270
| | | | | | | Rewrite this struct for the support of two ports and two message units registers. Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
* powerpc/85xx:Fix lds for nand boot debug infoPrabhakar Kushwaha2012-04-24-2/+2
| | | | | | | | | | | | | | | | | | Currently "u-boot", the elf file generated via u-boot-nand.lds does not contain required debug information i.e. .debug_{line, info, abbrev, aranges, ranges} into their respective _global_ sections. The original ld script line arch/powerpc/cpu/mpc85xx/start.o KEEP(*(.bootpg)) is not entirely correct because the start.o file is already processed by the linker,therefore the file wildcard in "KEEP(*(.bootpg))" will not process start.o again for bootpg. So Fix u-boot-nand.lds to generate these debug information. Signed-off-by: Anmol Paralkar <b07584@freescale.com> Signed-off-by: John Russo <John.Russo@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/p2041rdb: add env in NAND supportShaohui Xie2012-04-24-0/+5
| | | | | | | Add env in NAND support when boot from NAND. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/p2041rdb: add NAND and NAND boot supportShaohui Xie2012-04-24-3/+52
| | | | | | | | New P2041RDB board will add a NAND chip, so add support for NAND and NAND boot. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc8xxx: Fix CONFIG_DDR_RAW_TIMING for two boardsYork Sun2012-04-24-7/+7
| | | | | | | | | P1010RDB and p1_pc_rdb_pc has incorrect configuration for CONFIG_DDR_RAW_TIMING. It should be CONFIG_SYS_DDR_RAW_TIMING. Incorrect setting causes DDR failure in case of SPD absent. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/85xx:Avoid vector table compilation for nand_splPrabhakar Kushwaha2012-04-24-0/+6
| | | | | | | | NAND SPL code never compile the vector table. So no need to setup interrupt vector table for NAND SPL. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/85xx:Fix IVORs addr after vector table relocationPrabhakar Kushwaha2012-04-24-0/+33
| | | | | | | | | | | After relocation of vector table in SDRAM's lower address, IVORs value should be updated with new handler addresses. As vector tables are relocated to 0x100,0x200... 0xf00 address in DDR.IVORs are updated with 0x100, 0x200,....f00 hard-coded values. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/85xx:Avoid hardcoded vector address for IVORsPrabhakar Kushwaha2012-04-24-31/+34
| | | | | | | | | | | | For e500 and e500v2 architecturees processor IVPR address should be alinged on 64K boundary. in start.S, CONFIG_SYS_MONITOR_BASE is stored blindly in IVPR assuming it to be 64K aligned. It may not be true always. If it is not aligned, IVPR + IVORs may not point to an exception handler. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/p1023rds: Disable nor flash node and enable nand flash nodeChunhe Lan2012-04-24-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the p1023rds, when system boots from nor flash, kernel only accesses nor flash and can not access nand flash with BR0/OR0; when system boots from nand flash, kernel only accesses nand flash and can not access nor flash with BR0/OR0. Default device tree nor and nand node should have the following structure: Example: nor_flash: nor@0,0 { #address-cells = <1>; #size-cells = <1>; compatible = "cfi-flash"; reg = <0x0 0x0 0x02000000>; bank-width = <2>; device-width = <1>; status = "okay"; partition@0 { label = "ramdisk"; reg = <0x00000000 0x01c00000>; }; } nand_flash: nand@1,0 { #address-cells = <1>; #size-cells = <1>; compatible = "fsl,p1023-fcm-nand", "fsl,elbc-fcm-nand"; reg = <0x2 0x0 0x00040000>; status = "disabled"; u-boot-nand@0 { /* This location must not be altered */ /* 1MB for u-boot Bootloader Image */ reg = <0x0 0x00100000>; read-only; }; } When booting from nor flash, the status of nor node is enabled and the status of nand node is disabled in the default dts file, so do not do anything. But, when booting from nand flash, need to do some operations: o Disable the NOR node by setting status = "disabled"; o Enable the NAND node by setting status = "okay"; Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* sandbox: Use the new run_command()Simon Glass2012-04-23-6/+0
| | | | | | | | Now that run_command() handles both parsers, clean up sandbox to use it. This fixes a build error. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Mike Frysinger <vapier@gentoo.org>
* arm: restore fdt_fixup_ethernet call to do_bootm_linuxStephen Warren2012-04-23-0/+1
| | | | | | | | | | Commit 0a672d4 "arm: Add Prep subcommand support to bootm" re-organized do_bootm_linux for ARM. During the re-organization, the call to fdt_fixup_ethernet() was removed. I assume this was useful, so add it back. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Tom Rini <trini@ti.com>
* arm: fix bootm with device treeStephen Warren2012-04-23-1/+10
| | | | | | | | | | | | Commit 0a672d4 "arm: Add Prep subcommand support to bootm" re-organized do_bootm_linux() for ARM. During the re-organization, the code to pass the device tree to the kernel was removed. Add it back. This restores the ability to boot a kernel using device tree. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Tom Rini <trini@ti.com> Acked-by: Allen Martin <amartin@nvidia.com> Tested-by: Allen Martin <amartin@nvidia.com>
* Fix the behaviour of the 'run' commandTimo Ketola2012-04-23-1/+2
| | | | | | | | | | If one command fails, 'run' command should terminate and not execute any remaining variables. Signed-off-by: Timo Ketola <timo@exertus.fi> Tested-by: Wolfgang Denk <wd@denx.de> Tested-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
* Prepare v2012.04Wolfgang Denk2012-04-21-35/+35
| | | | | | Also tiny style cleanup to tools/patman/README Signed-off-by: Wolfgang Denk <wd@denx.de>
* net: ll_temac: drop obsolete "NAMESIZE" defineStephan Linz2012-04-21-2/+2
| | | | | | | | | | | | | | ... after commit "net/miiphy/serial: drop duplicate NAMESIZE define" (sha1:f6add13) was applied. The building of the new LL TEMAC network driver fails with error below: xilinx_ll_temac.c: In function 'xilinx_ll_temac_initialize': xilinx_ll_temac.c:301: error: 'NAMESIZE' undeclared (first use in this function) xilinx_ll_temac.c:301: error: (Each undeclared identifier is reported only once xilinx_ll_temac.c:301: error: for each function it appears in.) Signed-off-by: Stephan Linz <linz@li-pro.net> Acked-by: Mike Frysinger <vapier@gentoo.org>
* Add 'patman' patch generation, checking and submission scriptSimon Glass2012-04-21-0/+2354
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | What is this? ============= This tool is a Python script which: - Creates patch directly from your branch - Cleans them up by removing unwanted tags - Inserts a cover letter with change lists - Runs the patches through checkpatch.pl and its own checks - Optionally emails them out to selected people It is intended to automate patch creation and make it a less error-prone process. It is useful for U-Boot and Linux work so far, since it uses the checkpatch.pl script. It is configured almost entirely by tags it finds in your commits. This means that you can work on a number of different branches at once, and keep the settings with each branch rather than having to git format-patch, git send-email, etc. with the correct parameters each time. So for example if you put: in one of your commits, the series will be sent there. See the README file for full details. END Signed-off-by: Simon Glass <sjg@chromium.org>
* eb_cpux9k2: add USB host support to boardJens Scharsig2012-04-21-0/+14
| | | | Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de>
* mmc: Fix warning if CONFIG_MMC_TRACE is enabledDirk Behme2012-04-21-1/+1
| | | | | | | | | | | | | | Fix the warning mmc.c: In function 'mmc_send_cmd': mmc.c:87: warning: assignment from incompatible pointer type in case CONFIG_MMC_TRACE is enabled. Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com> CC: Andy Fleming <afleming@freescale.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Marek Vasut <marex@denx.de>
* ehci-omap: fix for enabling the correct usb portJeroen Hofstee2012-04-21-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is just a patch for the problem reported here: http://lists.denx.de/pipermail/u-boot/2012-February/117580.html originally reported by Igor. "Looks like this is copy paste error from my side,(for port2/3 it should have been bypass for port2/3 rather its port1 set in bypass mode)" I only submit the patch since it is missing in 2012.04-rc3 while the twister board depends on it. Maybe it is already somewhere in the reposistory, but I cannot find it. note: the twister boards still needs an additional `usb reset`, don't know why. U-Boot 2012.04-rc3-dirty (Apr 19 2012 - 21:38:38) AM35XX-GP ES1.0, CPU-OPP2, L3-165MHz, Max CPU Clock 600 Mhz TAM3517 TWISTER Board + LPDDR/NAND I2C: ready DRAM: 256 MiB NAND: 512 MiB MMC: OMAP SD/MMC: 0 In: serial Out: serial Err: serial Die ID #746c0000000000000155dc1405011024 Net: DaVinci-EMAC, smc911x-0 Hit any key to stop autoboot: 0 twister => usb start (Re)start USB... USB: Register 1313 NbrPorts 3 USB EHCI 1.00 scanning bus for devices... 1 USB Device(s) found scanning bus for storage devices... 0 Storage Device(s) found twister => usb reset (Re)start USB... USB: Register 1313 NbrPorts 3 USB EHCI 1.00 scanning bus for devices... 1 USB Device(s) found scanning bus for storage devices... 0 Storage Device(s) found twister => usb reset (Re)start USB... USB: Register 1313 NbrPorts 3 USB EHCI 1.00 scanning bus for devices... 1 USB Device(s) found scanning bus for storage devices... 0 Storage Device(s) found twister => usb reset (Re)start USB... USB: Register 1313 NbrPorts 3 USB EHCI 1.00 scanning bus for devices... 1 USB Device(s) found scanning bus for storage devices... 0 Storage Device(s) found Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl> Acked-by: Govindraj.R <govindraj.raja <at> ti.com> Acked-by: Tom Rini <trini@ti.com>
* fdt: avoid bad MAKEALL statusWolfgang Denk2012-04-21-3/+7
| | | | | | | | | | | | | | | | Current versions of dtc always print a message like DTC: dts->dtb on file "dt.dtb.tmp" which cannot even be suppressed with "-qqq". To avoid incorrect MAKEALL status, we manually filter out this message. This is a bit complicated, as we have to make sure to set a correct return code. Also, get rid of the temp file: dtc accepts "-" for stdin. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
* fdt: fix out of tree builds with DT supportWolfgang Denk2012-04-21-1/+1
| | | | | | | | | Fix: FATAL ERROR: Couldn't open "../arch/arm/dts/tegra20.dtsi": No such file or directory Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
* GCC4.6: Squash warnings in onenand_base.cWolfgang Denk2012-04-21-3/+2
| | | | | | | | | | | | Fix gcc 4.6 build warnings: onenand_base.c: In function 'onenand_probe': onenand_base.c:2577:6: warning: variable 'maf_id' set but not used [-Wunused-but-set-variable] Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Kyungmin Park <kyungmin.park@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com>
* Prepare v2012.04-rc3Wolfgang Denk2012-04-18-1/+1
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-shWolfgang Denk2012-04-18-2/+2
|\ | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-sh: sh: ecovec: Change macro from BOARD_LATE_INIT to CONFIG_BOARD_LATE_INIT sh: Fix rsk7264 pin setup for on-board ethernet
| * sh: ecovec: Change macro from BOARD_LATE_INIT to CONFIG_BOARD_LATE_INITNobuhiro Iwamatsu2012-04-18-1/+1
| | | | | | | | | | | | | | | | When calling board_late_init, we need to define CONFIG_BOARD_LATE_INIT. The latest ecovec config defines BOARD_LATE_INIT, board_late_init is not called. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * sh: Fix rsk7264 pin setup for on-board ethernetPhil Edworthy2012-04-18-1/+1
| | | | | | | | | | | | | | This sets up the external ethernet IRQ pin. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | i.MX6: arm2: Add AXI cache and Qos settingDirk Behme2012-04-17-0/+6
|/ | | | | | | | | | | | | | | Do the same AXI cache and Qos settings done already in the SabreLite imximage.cfg for the ARM2 board, too. It fixes a display flash issue caused by low priority of the display IDMA channel. Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com> CC: Jason Chen <b02280@freescale.com> CC: Jason Liu <r64343@freescale.com> CC: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <festevam@gmail.com> Acked-by: Jason Liu <r64343@freescale.com>
* Prepare v2012.04-rc2; minor Coding Style cleanupWolfgang Denk2012-04-16-89/+87
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2012-04-16-364/+530
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-arm: ARM926EJS: Fix cache.c to comply with checkpatch.pl ARM926EJS: Make asm routines volatile in cache ops MX35: mx35pdk: wrong board revision ARM1136: MX35: Make asm routines volatile in cache ops ARM: add u-boot.imx as target for i.MX SOCs M28: Pull out CONFIG_APBH_DMA so it's always enabled DMA: Split the APBH DMA init into block and channel init imx: Return gpio_set_value in gpio_direction_output imx: Use GPIO_TO_PORT macro in the gpio driver instead of (gpio >> 5) imx: Add GPIO_TO_PORT macro in the mxc_gpio driver imx: Remove unneeded/repititive definitions from imx headers i.MX28: Allow coexistence of PIO and DMA mode for SD/MMC MX31: mx31pdk: drop enable_caches from board file i.MX28: Fix initial stack pointer position mx35: mx35pdk: fix when cache functions are linked mx35: flea3: fix when cache functions are linked ARM: 926ejs: use debug() for misaligned addresses ARM1136: add cache flush and invalidate operations mx6qsabrelite: Fix the serial console port mx6qsabrelite: Add boot switch setting information into the README i.MX6: mx6qsabrelite: add cache commands if cache is enabled i.MX6: implement enable_caches() i.MX6: define CACHELINE_SIZE MX53: DDR: Fix ZQHWCTRL field TZQ_CS mx28evk: Add a README file mx28: Split the README into a common part and a m28 specific part tricorder: Load kernel from ubifs tricorder: Add UBIFS cm-t35: fix Ethernet reset timing hawkboard: Add CONFIG_SPL_LIBGENERIC_SUPPORT BeagleBoard: Remove userbutton command and use gpio command instead OMAP: Move omap1510inn to Unmaintained / Orphaned
| * ARM926EJS: Fix cache.c to comply with checkpatch.plMarek Vasut2012-04-16-9/+8
| | | | | | | | | | | | Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
| * ARM926EJS: Make asm routines volatile in cache opsMarek Vasut2012-04-16-1/+1
| | | | | | | | | | | | | | | | | | | | We certainly don't want the compiler to reorganise the code for dcache flushing. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Acked-by: Mike Frysinger <vapier@gentoo.org> Acked-by: Stefano Babic <sbabic@denx.de>
| * MX35: mx35pdk: wrong board revisionStefano Babic2012-04-16-12/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The board revision is detected accessing to the pmic, that is not available before relocation (I2C). This generates the following error: CPU: Freescale i.MX35 rev 2.0 at 532 MHz. Reset cause: WDOG <reg num> = 7 is invalid. Should be less than 0 Board: MX35 PDK 1.0 The revision number is wrong, as a default value is printed (tested on a mx35pdk Rev. 2.0). Move the output in the board_late_init(), when pmic can be accessed. Signed-off-by: Stefano Babic <sbabic@denx.de>
| * ARM1136: MX35: Make asm routines volatile in cache opsStefano Babic2012-04-16-10/+12
| | | | | | | | | | | | | | | | | | | | As well as pushed for ARM926EJS, we certainly don't want the compiler to reorganise the code for dcache flushing Fix checkpatch warnings as well. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Marek Vasut <marex@denx.de> CC: Albert Aribaud <albert.u.boot@aribaud.net>
| * ARM: add u-boot.imx as target for i.MX SOCsStefano Babic2012-04-16-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale SOCs require an header to u-boot.bin The patch adds u-boot.imx to the default targets if the imx file is set (IMX_CONFIG). Signed-off-by: Stefano Babic <sbabic@denx.de> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> CC: Loïc Minier <loic.minier@linaro.org> CC: Mike Frysinger <vapier@gentoo.org> Acked-by: Mike Frysinger <vapier@gentoo.org> Acked-by: Dirk Behme <dirk.behme@de.bosch.com> Tested-by: Dirk Behme <dirk.behme@googlemail.com>
| * M28: Pull out CONFIG_APBH_DMA so it's always enabledMarek Vasut2012-04-16-1/+5
| | | | | | | | | | | | | | | | | | | | | | The ABPH DMA is now used also by the SD card. Therefore it has to be enabled even if NAND is disabled. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
| * DMA: Split the APBH DMA init into block and channel initMarek Vasut2012-04-16-24/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes the issue where mxs_dma_init() was called either twice or never, without introducing any new init hooks. The idea is to allow each and every device using the APBH DMA block to configure and request only the channels it uses, instead of making it call init for all the channels as is now. The common DMA block init part, which only configures the block, is then called from CPUs arch_cpu_init() call. NOTE: This patch depends on: http://patchwork.ozlabs.org/patch/150957/ Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
| * imx: Return gpio_set_value in gpio_direction_outputVikram Narayanan2012-04-16-2/+1
| | | | | | | | | | | | | | | | Return gpio_set_value in gpio_direction_output. Earlier it returned 0 and ignored gpio_set_value's return value. Signed-off-by: Vikram Narayanan <vikram186@gmail.com> Acked-by: Stefano Babic <sbabic@denx.de>
| * imx: Use GPIO_TO_PORT macro in the gpio driver instead of (gpio >> 5)Vikram Narayanan2012-04-16-4/+4
| | | | | | | | | | | | | | Use the defined GPIO_TO_PORT macro. Remove gpio >> 5 references. Signed-off-by: Vikram Narayanan <vikram186@gmail.com> Acked-by: Stefano Babic <sbabic@denx.de>
| * imx: Add GPIO_TO_PORT macro in the mxc_gpio driverVikram Narayanan2012-04-16-0/+1
| | | | | | | | | | | | | | Add GPIO_TO_PORT macro in the mxc_gpio.c driver Signed-off-by: Vikram Narayanan <vikram186@gmail.com> Acked-by: Stefano Babic <sbabic@denx.de>
| * imx: Remove unneeded/repititive definitions from imx headersVikram Narayanan2012-04-16-6/+0
| | | | | | | | | | | | | | Remove gpio related unused/repititive definitions from imx headers. Signed-off-by: Vikram Narayanan <vikram186@gmail.com> Acked-by: Stefano Babic <sbabic@denx.de>
generated by cgit v1.1 at 2024-11-08 21:57:14 +0000