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* mpc83xx: New board support for SIMPC8313Ron Madrid2009-01-23-0/+1186
| | | | | | | | | | | This patch will create a new board, SIMPC8313, from Sheldon Instruments. This board boots from NAND devices and is configureable for either large or small page devices. The board supports non-soldered DDR2, one ethernet port, a Marvell 88E1118 PHY, and PCI host support. The board also has a FPGA connected to the eLBC providing glue logic to a TMS320C67xx DSP. Signed-off-by: Ron Madrid <ron_madrid@sbcglobal.net> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* 83xx: Use the proper sequence for updating IMMR.Scott Wood2009-01-21-3/+15
| | | | | | | | | | | This ensures that subsequent accesses properly hit the new window. The dcbi during the NAND loop was accidentally working around this; it's no longer necessary, as the cache is not enabled. Reported-by: Suchit Lepcha <Suchit.Lepcha@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: Add PCI-E support for MPC837XEMDS boardsAnton Vorontsov2009-01-21-5/+117
| | | | | | | | | | | MPC837XEMDS boards can support PCI-E via "PCI-E riser card". The card provides two PCI-E (x2) ports. Though, only one port can be used in x2 mode. Two ports can function simultaneously in x1 mode. PCI-E x1/x2 modes can be switched via "pex_x2" environment variable. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: Add PCI-E support for MPC8315ERDB boardsAnton Vorontsov2009-01-21-0/+73
| | | | | | | | MPC8315ERDB boards features PCI-E x1 and Mini PCI-E x1 ports. Let's support them. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: Add support for MPC83xx PCI-E controllersAnton Vorontsov2009-01-21-23/+488
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for MPC83xx PCI-E controllers in Root Complex mode. The patch is based on Tony Li and Dave Liu work[1]. Though unlike the original patch, by default we don't register PCI-E buses for use in U-Boot, we only configure the controllers for future use in other OSes (Linux). This is done because we don't have enough of spare BATs to map all the PCI-E regions. To actually use PCI-E in U-Boot, users should explicitly define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES symbol in the board file. And only then U-Boot will able to access PCI-E, but at the cost of disabled address translation. [1] http://lists.denx.de/pipermail/u-boot/2008-January/027630.html Signed-off-by: Tony Li <tony.li@freescale.com> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Acked-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* MPC8349EMDS: do not setup unused PCI clock outputs in PCI agent modeIra Snyder2009-01-21-7/+0
| | | | | | | | | When running in PCI agent mode, the PCI_CLK_OUT signals are not used, so do not enable them. See the MPC8349EA Reference Manual, Section 4.4.2 "Clocking in PCI Agent Mode". Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* 83xx: PCI agent mode fixes for multi-board systemsIra Snyder2009-01-21-0/+6
| | | | | | | | | | | | | | | | | | When running a system with 2 or more MPC8349EMDS boards in PCI agent mode, the boards will lock up the PCI bus by scanning against each other. The boards lock against each other by trying to access the PCI bus before clearing their configuration lock bit. Both boards end up in a loop, sending and receiving "Target Not Ready" messages forever. When running in PCI agent mode, the scanning now takes place after the boards have cleared their configuration lock bit. Also, add a missing declaration to the mpc83xx.h header file, fixing a build warning. Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: Size optimization of start.SRon Madrid2009-01-21-38/+39
| | | | | | | | | | | Currently there are in excess of 100 bytes located at the beginning of the image built by start.S that are not being utilized. This patch moves a few functions into this part of the image. This will create a greater number of *available* bytes that can be used by board specific code in NAND builds and will decrease the size of the assembled code in other builds. Signed-off-by: Ron Madrid <ron_madrid@sbcglobal.net> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* Merge branch 'master' into nextKim Phillips2009-01-21-5566/+27040
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| * Prepare v2009.01v2009.01Wolfgang Denk2009-01-21-1/+11
| | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
| * Prepare 2009.01-rc3v2009.01-rc3Wolfgang Denk2009-01-18-1/+177
| | | | | | | | | | | | Update CHANGELOG Signed-off-by: Wolfgang Denk <wd@denx.de>
| * Merge branch 'master' of /home/wd/git/u-boot/custodiansWolfgang Denk2009-01-18-1/+1
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| | * fdt_resize(): fix actualsize calculations with unaligned blobsPeter Korsgaard2009-01-17-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The code in fdt_resize() to extend the fdt size to end on a page boundary is wrong for fdt's not located at an address aligned on a page boundary. What's even worse, the code would make actualsize shrink rather than grow if (blob & 0xfff) was bigger than the amount of padding added by ALIGN(), causing fdt_add_mem_rsv to fail. Fix it by aligning end address (blob + size) to a page boundary instead. For aligned fdt's this is equivalent to what we had before. Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
| * | build system: treat all Darwin's alikeMike Frysinger2009-01-18-2/+2
| |/ | | | | | | | | | | | | The x86 based version of Darwin behaves the same quirky way as the powerpc Darwin, so only check HOSTOS when setting up Darwin workarounds. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * ncb: use socklen_tMike Frysinger2009-01-16-1/+1
| | | | | | | | | | | | The recvfrom() function takes a socklen_t, not an int. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Merge branch 'master' of git://git.denx.de/u-boot-shWolfgang Denk2009-01-16-1083/+657
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| | * sh: serial: use readx/writex accessorsJean-Christophe PLAGNIOL-VILLARD2009-01-16-23/+23
| | | | | | | | | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| | * sh: serial: coding style cleanupJean-Christophe PLAGNIOL-VILLARD2009-01-16-17/+18
| | | | | | | | | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| | * sh: Fix compile error on lowlevel_init fileNobuhiro Iwamatsu2009-01-16-8/+13
| | | | | | | | | | | | | | | | | | | | | | | | lowlevel_init of SH was corrected to use the write/readXX macro. However, there was a problem that was not able to be compiled partially. This patch corrected this. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| | * sh: Fix up rsk7203 target for out of tree buildKieran Bingham2009-01-16-10/+19
| | | | | | | | | | | | | | | | | | | | | Fix up rsk7203 target to build successfully using out-of-tree build. Signed-off-by: Kieran Bingham <kbingham@mpc-data.co.uk> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| | * sh: use write{8,16,32} in all lowlevel_initJean-Christophe PLAGNIOL-VILLARD2009-01-16-785/+338
| | | | | | | | | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| | * sh: lowlevel_init coding style cleanupJean-Christophe PLAGNIOL-VILLARD2009-01-16-634/+640
| | | | | | | | | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| | * sh: update sh2/sh2a timer coding styleJean-Christophe PLAGNIOL-VILLARD2009-01-16-2/+2
| | | | | | | | | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| | * sh: update sh timer coding styleJean-Christophe PLAGNIOL-VILLARD2009-01-16-13/+13
| | | | | | | | | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk2009-01-16-163/+184
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| | * ppc4xx: Add loadpci command to esd's CPCI4052 and CPCI405AB boardsMatthias Fuchs2009-01-14-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds esd's loadpci BSP command to CPCI4052 and CPCI405AB board. This requires CONFIG_CMD_BSP and CONFIG_PRAM. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> Signed-off-by: Stefan Roese <sr@denx.de>
| | * ppc4xx: Disable pci node in device tree on CPCI405 pci adaptersMatthias Fuchs2009-01-14-0/+24
| | | | | | | | | | | | | | | Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> Signed-off-by: Stefan Roese <sr@denx.de>
| | * ppc4xx: Cleanup CPCI405 board codeMatthias Fuchs2009-01-14-163/+144
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch cleans up CPCI405 board support: - wrap long lines - unification of spaces in function calls - remove dead code Use correct io accessors on peripherals. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> Signed-off-by: Stefan Roese <sr@denx.de>
| | * ppc4xx: Enable auto RS485 mode on PLU405 boardsMatthias Fuchs2009-01-14-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch turns on the auto RS485 mode in the 2nd external uart on PLU405 boards. This is a special mode of the used Exar XR16C2850 uart. Because these boards only have a 485 physical layer connected it's a good idea to turn it on by default. Signed-off-by: Matthias Fuchs <mf@esd.eu> Signed-off-by: Stefan Roese <sr@denx.de>
| * | Prepare 2009.01-rc2v2009.01-rc2Wolfgang Denk2009-01-14-0/+588
| | | | | | | | | | | | | | | | | | Update CHANGELOG. Signed-off-by: Wolfgang Denk <wd@denx.de>
| * | cpu/mpc824x/Makefile: fix warning with parallel buildsWolfgang Denk2009-01-14-1/+1
| |/ | | | | | | | | | | | | | | | | | | Parallel builds would occasionally issue this build warning: ln: creating symbolic link `cpu/mpc824x/bedbug_603e.c': File exists Use "ln -sf" as quick work around for the issue. Signed-off-by: Wolfgang Denk <wd@denx.de>
| * Merge branch 'master' of /home/wd/git/u-boot/custodiansWolfgang Denk2009-01-14-55/+67
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| | * Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2009-01-14-13/+19
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| | | * Some changes of TLB entry setting for MPC8572DSHaiying Wang2009-01-13-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Move the TLB entry of PIXIS_BASE from TLB0 to TLB1[8], because in CAMP mode, all the TLB0 entries will be invalidated after cpu1 brings up kernel, thus cpu0 can not access PIXIS_BASE anymore (any access will cause DataTLBError exception) - Set CONFIG_SYS_DDR_TLB_START to 9 for MPC8572DS board. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
| | | * Change DDR tlb start entry to CONFIG param for 85xxHaiying Wang2009-01-13-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | So that we can locate the DDR tlb start entry to the value other than 8. By default, it is still 8. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
| | | * Change PCIE1&2 deciide logic on MPC8544DS board more readableRoy Zang2009-01-13-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The IO port selection for MPC8544DS board: Port cfg_io_ports PCIE1 0x2, 0x3, 0x4, 0x5, 0x6, 0x7 PCIE2 0x4, 0x5, 0x6, 0x7 PCIE3 0x6, 0x7 This patch changes the PCIE12 and PCIE2 logic more readable. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
| | | * PCIE2 and PCIE3 are decided by corresponing bit in devdisr instead of PCIE1 bitRoy Zang2009-01-13-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | PCIE2 and PCIE3 should be decided by corresponing bit in devdisr instead of PCIE1 bit. On MPC8572DS board, PCIE refers to PCIE1. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
| | | * Fix IO port selection issue on MPC8544DS and MPC8572DS boardsRoy Zang2009-01-13-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The IO port selection is not correct on MPC8572DS and MPC8544DS board. This patch fixes this issue. For MPC8572 Port cfg_io_ports PCIE1 0x2, 0x3, 0x7, 0xb, 0xc, 0xf PCIE2 0x3, 0x7 PCIE3 0x7 For MPC8544 Port cfg_io_ports PCIE1 0x2, 0x3, 0x4, 0x5, 0x6, 0x7 PCIE2 0x4, 0x5, 0x6, 0x7 PCIE3 0x6, 0x7 Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
| | * | mpc8610hpcd: Fix PCI mapping conceptsBecky Bruce2009-01-13-19/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename _BASE to _BUS, as it's actually a PCI bus address, separate virtual and physical addresses into _VIRT and _PHYS, and use each appopriately. This makes the code easier to read and understand, and facilitates mapping changes going forward. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
| | * | sbc8641d: Fix PCI mapping conceptsBecky Bruce2009-01-13-23/+27
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | Rename _BASE to _BUS, as it's actually a PCI bus address, separate virtual and physical addresses into _VIRT and _PHYS, and use each appopriately. This makes the code easier to read and understand, and facilitates mapping changes going forward. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
| * | MPC86xx: fix build warningsWolfgang Denk2009-01-12-3/+1
| |/ | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
| * Merge branch 'master' of git://git.denx.de/u-boot-blackfinWolfgang Denk2009-01-10-61/+93
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| | * bf537-stamp/nand: fix board_nand_init prototypeMike Frysinger2009-01-07-1/+3
| | | | | | | | | | | | | | | | | | The board_nand_init() function should return an int, not void. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| | * Blackfin: drop CONFIG_SPI handling in board initMike Frysinger2009-01-07-7/+0
| | | | | | | | | | | | | | | | | | | | | The eeprom SPI init functions are duplicated as the common code already executes these for us. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| | * Blackfin: fix out-of-tree building with ldscriptsMike Frysinger2009-01-07-16/+20
| | | | | | | | | | | | | | | | | | | | | Many of the Blackfin board linker scripts are preprocessed, so make sure we output the linker script into the build tree rather than the source tree. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| | * Blackfin: fix linker scripts to work with --gc-sectionsMike Frysinger2009-01-07-36/+48
| | | | | | | | | | | | | | | | | | | | | Make sure all .text sections get pulled in and the entry point is properly referenced so they don't get discarded when linking with --gc-sections. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| | * Blackfin: set proper LDRFLAGS for parallel booting LDRsMike Frysinger2009-01-07-1/+22
| | | | | | | | | | | | | | | | | | | | | In order to boot an LDR out of parallel flash, the ldr utility needs a few flags to tell it to generate the right header. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * | at91rm9200: move define from lowlevel_init to headerJean-Christophe PLAGNIOL-VILLARD2009-01-06-48/+49
| | | | | | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
| * | m501sk: move to the common memory setupJean-Christophe PLAGNIOL-VILLARD2009-01-06-202/+33
| | | | | | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
| * | at91rm9200: rename lowlevel init value to CONFIG_SYS_Jean-Christophe PLAGNIOL-VILLARD2009-01-06-203/+203
| | | | | | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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