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| * sunxi: Explicitly cast u32 pointer conversionsAlexander Graf2016-04-01-5/+5
| | | | | | | | | | | | | | | | | | | | | | Some parts of the sunxi code cast explicitly between u32 values and pointers. This is not a problem in practice, because all 64bit SoCs today only use the lower 32 bits for their phyical address space. But we need to make sure that the compiler is sure this is not an accident as well. Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: Depend SPL configs on SUPPORT_SPLAlexander Graf2016-04-01-2/+2
| | | | | | | | | | | | | | | | | | | | We currently depend SPL config options on specific machine types which doesn't scale. Fortunately there's already a kconfig variable that tells us whether we want to build SPL code at all, so just depend them on this. Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: Move cpu independent code to mach directoryAlexander Graf2016-04-01-37/+52
| | | | | | | | | | | | | | | | | | | | | | | | Some of the code in arch/arm/cpu/armv7/sunxi is actually armv7 specific, while most of it is just generic code that could as well be used on an AArch64 SoC. Move all files that are not really tied to armv7 into a new mach-sunxi directory. Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: Enable USB nodes for H8Homlet v2Chen-Yu Tsai2016-04-01-0/+12
| | | | | | | | | | | | | | | | | | This provides the minimal changes to the H8Homlet v2 dts to enable USB in U-boot. It is not what will be submitted to the kernel. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: Enable USB on Cubietruck PlusChen-Yu Tsai2016-04-01-0/+12
| | | | | | | | | | | | | | | | | | This provides the minimal changes to the Cubietruck Plus dts to enable USB in U-boot. It is not what will be submitted to the kernel. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: Add USB and R_PIO nodes to sun8i-a83t.dtsiChen-Yu Tsai2016-04-01-0/+34
| | | | | | | | | | | | | | | | | | This provides the minimal changes to the A83T dtsi to enable USB in U-boot. It is not what will be submitted to the kernel. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: Cubietruck Plus: Enable USB Kconfig options in defconfigChen-Yu Tsai2016-04-01-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The Cubietruck Plus uses all 3 USB controllers: - USB OTG functions are provided by the musb USB OTG controller - Onboard SATA is provied by a USB-SATA bridge connected to USB1 - The USB host ports on the board are provided by an HSIC USB hub FLDO1 is set to 1.2V for HSIC. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: h8_homlet_v2: Enable USB Kconfig options in defconfigChen-Yu Tsai2016-04-01-0/+5
| | | | | | | | | | | | | | | | | | | | | | The h8_homlet_v2 has 2 USB host ports, one connected to the OTG controller, one connected to the EHCI/OHCI pair. Also provide the card detect pin for MMC. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: ohci: Add A83T compatibleChen-Yu Tsai2016-03-31-0/+1
| | | | | | | | | | | | | | | | We have a separate compatible for almost each SoC. Add one for the A83T. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: ehci: Add A83T compatibleChen-Yu Tsai2016-03-31-0/+1
| | | | | | | | | | | | | | | | We have a separate compatible for almost each SoC. Add one for the A83T. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: clk: Fix USB PHY clock macros for A83TChen-Yu Tsai2016-03-31-3/+3
| | | | | | | | | | | | | | | | | | The A83T has 3 PHYs, the last one being HSIC, which has 2 clocks. Also there is only 1 OHCI. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: usb_phy: Add support for A83T USB PHYsChen-Yu Tsai2016-03-31-2/+48
| | | | | | | | | | | | | | | | | | The A83T has 3 USB PHYs: 1 for USB OTG, 1 for standard USB 1.1/2.0 host, 1 for USB HSIC. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: h8_homlet_v2: Set DLDO4 to 3.3VChen-Yu Tsai2016-03-31-0/+1
| | | | | | | | | | | | | | | | | | DLDO4 supplies power to the PD pins, and the AC200 Ethernet PHY / composite video encoder. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: h8_homlet_v2: Set DCDC1 to default voltage (3.3V)Chen-Yu Tsai2016-03-31-1/+0
| | | | | | | | | | | | | | | | | | | | | | The schematics of the h8_homlet_v2 show DCDC1 set to 3.3V. Some Allwinner-based boards set it to 3.0V to conserve power. Since the h8_homlet_v2 is a set-top box board with external power, there is no such requirement. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * power: axp818: Add support for FLDOsChen-Yu Tsai2016-03-31-0/+69
| | | | | | | | | | | | | | | | | | The FLDOs on AXP818 PMIC normally provide power to CPUS and USB HSIC PHY on the A83T/H8. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * power: axp818: Fix DCDC5 default voltageChen-Yu Tsai2016-03-31-3/+1
| | | | | | | | | | | | | | | | | | | | | | DCDC5 is designed to supply VCC-DRAM, which is normally 1.5V for DDR3, 1.35V for DDR3L, and 1.2V for LPDDR3. Also remove CONFIG_AXP_DCDC5_VOLT from h8_homlet_v2_defconfig. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: axp: Support VBUS drive GPIO on AXP818Chen-Yu Tsai2016-03-31-1/+5
| | | | | | | | | | | | | | | | | | AXP818 supports VBUS drive function, even though the manual does not mention it. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: axp: Generalize register macros for VBUS drive GPIOChen-Yu Tsai2016-03-31-15/+18
| | | | | | | | | | | | | | | | | | VBUS drive is supported on AXP221 and later PMICs. Rework the macros so we can support this on later PMICs without too much work. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * musb: sunxi: Add support for A83TChen-Yu Tsai2016-03-31-1/+1
| | | | | | | | | | | | | | | | | | | | Like the Allwinner A33 SoC, the A83T is missing the config register from the musb USB DRD hardware block. Use a known working value for it. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * power: axp818: Remove undefined axp818_init()Chen-Yu Tsai2016-03-31-2/+0
| | | | | | | | | | | | | | | | axp818_init() is declared, but never defined. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: Enable LDO3 and LDO4 at 2.8V on OLinuxIno Lime boardsHans de Goede2016-03-31-0/+6
| | | | | | | | | | | | | | LDO3 and LDO4 are used to power port E resp. port G, which are exposed on gpio headers, so enable them at 2.8V as specified in the schematic. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: A20-OLinuXino-Lime2: Force 8211CL to masterMichael Haas2016-03-31-0/+1
| | | | | | | | | | | | | | | | | | Force master mode on the A20-OLinuXino-Lime2. This change is required to get a reliable link at gigabit speeds. Signed-off-by: Michael Haas <haas@computerlinguist.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: A20-Olimex-SOM-EVB: Force 8211CL to masterMichael Haas2016-03-31-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Force master mode for 1000BASE-T operation on the A20-Olimex-SOM-EVB. Karsten Merker reports that this change is necessary to get a reliable link at gigabit speeds. Signed-off-by: Michael Haas <haas@computerlinguist.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * net: phy: Optionally force master mode for RTL PHYMichael Haas2016-03-31-1/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces CONFIG_RTL8211X_PHY_FORCE_MASTER. If this define is set, RTL8211x PHYs (except for the RTL8211F) will have their 1000BASE-T master/slave autonegotiation disabled and forced to master mode. This is helpful for PHYs like the RTL8211C which produce unstable links in slave mode. Such problems have been found on the A20-Olimex-SOM-EVB and A20-OLinuXino-Lime2. There is no proper way to identify affected PHYs in software as the RTL8211C shares its UID with the RTL8211B. Thus, this fix requires the introduction of an #ifdef. CC: fradav@gmail.com CC: merker@debian.org CC: hdegoede@redhat.com CC: ijc@hellion.org.uk CC: joe.hershberger@ni.com Signed-off-by: Michael Haas <haas@computerlinguist.org> Tested-by: Karsten Merker <merker@debian.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: Print soc-id from sram controller for sun8i boardsHans de Goede2016-03-31-5/+19
| | | | | | | | | | | | | | | | | | As the need for various magic sram pokes has shown this maybe useful info to have. e.g. this shows one of my a23 tablets having an id of 1661 rather then the usual 1650 for the a23. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: Add conditional magic sram poke for A33Hans de Goede2016-03-31-4/+16
| | | | | | | | | | | | | | | | | | I noticed that for certain SoC versions boot0 does a magic poke when build for A33. I'm not aware of this actually being necessary anywhere, but better safe then sorry. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | ARM: uniphier: remove CONFIG_ARP_TIMEOUT defineMasahiro Yamada2016-04-01-8/+0
| | | | | | | | | | | | | | | | | | I no longer see the problem claimed in the comment block. Rather, the 0.5 msec timeout seems too short for some TFTP servers. Drop the CONFIG_ARM_TIMEOUT to fall back to the 5 sec timeout. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | cosmetic: Fix typos "privide"Masahiro Yamada2016-04-01-8/+8
| | | | | | | | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: uniphier: rename function names ph1_* to uniphier_*Masahiro Yamada2016-04-01-193/+197
| | | | | | | | | | | | | | Eliminate the "ph1"_ prefixes from function names because "uniphier_" describes the SoC familiy better. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: uniphier: add pin-mux settings for NAND, eMMC, SD of PH1-sLD3Masahiro Yamada2016-04-01-0/+23
| | | | | | | | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: uniphier: enable eMMC on PH1-sLD3 reference boardMasahiro Yamada2016-04-01-0/+4
| | | | | | | | | | | | | | On PH1-sLD3, eMMC and NAND are assigned to different I/O pins. Both devices can be enabled at the same time. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: uniphier: adjust dram_init() and dram_init_banksize() for ARM64Masahiro Yamada2016-04-01-10/+35
| | | | | | | | | | | | | | | | | | | | | | Currently, these functions assume #address-cells and #size-cells are both one. Fix them to support 64bit DTB. Also, I am fixing a buffer overrun bug while I am here. The array size of gd->bd->bd_dram is CONFIG_NR_DRAM_BANKS. The number of iteration in the loop should be limited by that CONFIG. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: uniphier: drop unneeded defines related to legacy serial driverMasahiro Yamada2016-04-01-6/+0
| | | | | | | | | | | | | | These defined were used for pre-DM ns16550 serial driver. They are unneeded because UniPhier SoCs now use DM serial. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: dts: uniphier: add NAND pinmux nodeMasahiro Yamada2016-04-01-0/+5
| | | | | | | | | | | | This will be used to set up pin-muxing for the NAND controller. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: dts: uniphier: add clock-frequency to serial nodes of LD11/LD20Masahiro Yamada2016-04-01-0/+8
| | | | | | | | | | | | | | | | Since no clock driver is implemented for peripherals in U-Boot yet, this property is needed for the serial driver to set up the divisor register. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | pinctrl: uniphier: support UniPhier PH1-LD11 pinctrl driverMasahiro Yamada2016-04-01-6/+7
| | | | | | | | | | | | | | | | The pinmux of PH1-LD11 is almost a subset of that of PH1-LD20 (as far as used in boot-loader), so this commit makes the driver shared between the two SoCs. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | pinctrl: uniphier: support UniPhier PH1-LD20 pinctrl driverMasahiro Yamada2016-04-01-0/+120
| | | | | | | | | | | | Add pin configuration and pinmux support for UniPhier PH1-LD20 SoC. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | pinctrl: uniphier: support per-pin input enable for new SoCsMasahiro Yamada2016-04-01-1/+28
| | | | | | | | | | | | | | | | Upcoming new pinctrl drivers for PH1-LD11 and PH-LD20 support input signal gating for each pin. (While, existing ones only support it per pin-group.) This commit prepares the core part for that. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | pinctrl: uniphier: introduce capability flagMasahiro Yamada2016-04-01-27/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The core part of the UniPhier pinctrl driver needs to support a new capability for upcoming UniPhier ARMv8 SoCs. This sometimes happens because pinctrl drivers include really SoC-specific stuff. This commit intends to tidy up SoC-specific parameters of the existing drivers before adding new ones. Having flags would be better than adding new members every time a new SoC-specific capability comes up. At this time, there is one flag, UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE. This capability (I'd say rather quirk) was added for PH1-Pro4 and PH1-Pro5 as requirement from our customer. For those SoCs, one pin-mux setting is controlled by the combination of two separate registers; the LSB bits at register offset (8 * N) and the MSB bits at (8 * N + 4). Because it is impossible to update two separate registers atomically, the LOAD_PINCTRL register should be set in order to make the pin-mux settings really effective. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | pinctrl: uniphier: use devm_get_addr() to get base addressMasahiro Yamada2016-04-01-6/+3
| | | | | | | | | | | | | | | | | | Currently, fdtdec_get_addr_size() does not support the address translation, so it cannot handle device trees with non-straight "ranges" properties. (This would be a problem with DTS for UniPhier ARMv8 SoCs.) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | mmc: uniphier: use devm_get_addr() to get base addressMasahiro Yamada2016-04-01-3/+6
| | | | | | | | | | | | | | | | | | Currently, fdtdec_get_addr_size() does not support the address translation, so it cannot handle device trees with non-straight "ranges" properties. (This would be a problem with DTS for UniPhier ARMv8 SoCs.) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | gpio: uniphier: use devm_get_addr() to get base addressMasahiro Yamada2016-04-01-5/+3
| | | | | | | | | | | | | | | | | | Currently, fdtdec_get_addr_size() does not support the address translation, so it cannot handle device trees with non-straight "ranges" properties. (This would be a problem with DTS for UniPhier ARMv8 SoCs.) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | i2c: uniphier: use devm_get_addr() to get base addressMasahiro Yamada2016-04-01-13/+10
| | | | | | | | | | | | | | | | | | Currently, fdtdec_get_addr_size() does not support the address translation, so it cannot handle device trees with non-straight "ranges" properties. (This would be a problem with DTS for UniPhier ARMv8 SoCs.) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | clk: uniphier: use devm_get_addr() to get base addressMasahiro Yamada2016-04-01-6/+3
| | | | | | | | | | | | | | | | | | Currently, fdtdec_get_addr_size() does not support the address translation, so it cannot handle device trees with non-straight "ranges" properties. (This would be a problem with DTS for UniPhier ARMv8 SoCs.) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | serial: uniphier: use devm_get_addr() to get base addressMasahiro Yamada2016-04-01-3/+5
| | | | | | | | | | | | | | | | | | Currently, fdtdec_get_addr_size() does not support the address translation, so it cannot handle device trees with non-straight "ranges" properties. (This would be a problem with DTS for UniPhier ARMv8 SoCs.) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: uniphier: add sramupdate commandMasahiro Yamada2016-04-01-0/+4
| | | | | | | | | | | | This command would be useful to update U-Boot images in SRAM. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: uniphier: make u-boot-with-spl.bin really availableMasahiro Yamada2016-04-01-0/+1
| | | | | | | | | | | | | | | | | | | | | | Commit d085ecd61b99 ("ARM: uniphier: switch to raw U-Boot image") claimed that u-boot-with-spl.bin would be useful in its commit log, but it was not available because the commit missed to define CONFIG_SPL_MAX_SIZE. Without it, CONFIG_SPL_PAD_TO is not defined either (see include/config_fallbacks.h). So, the SPL image is not padded correctly. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | mtd: nand: denali: max_banks calculation changed in revision 5.1Graham Moore2016-04-01-1/+12
|/ | | | | | | | | | | | | | Read Denali hardware revision number and use it to calculate max_banks, The encoding of max_banks changed in Denali revision 5.1. [ Linux commit : 271707b1d817f5104e02b2bd1bab43f0c8759418 ] Signed-off-by: Graham Moore <grmoore@opensource.altera.com> [Brian: parentheses around macro arg] Signed-off-by: Brian Norris <computersforpeace@gmail.com> [Masahiro: import from Linux and adjust ioread32() to readl() ] Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2016-03-29-0/+2
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| * ARM: tegra210: set PLLE_PTS bit when enabling PLLEStephen Warren2016-03-29-0/+2
| | | | | | | | | | | | | | | | This bit needs to be set for system suspend/resume to work. This setting will be documented in an updated TRM at some time in the future. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
generated by cgit v1.1 at 2024-11-05 08:26:15 +0000