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* sunxi: add proper device tree for Orange Pi Zero boardsIcenowy Zheng2017-01-15-0/+144
| | | | | | | | Add a proper device tree file for Orange Pi Zero boards from Xunlong, which come with a Allwinner H2+ SoC (similar to H3). Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Reviewed-by: Jagan Teki <jagan@openedev.com>
* sunxi: enable H3 EMAC for the nanopi neoJelle van der Waa2017-01-15-0/+11
| | | | | | | | | The nanopi already had the CONFIG_SUN8I_EMAC=y enabled in it's defconfig file, but was missing the &emac the device tree entry. Signed-off-by: Jelle van der Waa <jelle@vdwaa.nl> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* Kconfig: CONFIG_OF_PLATDATA doesn't really existTom Rini2017-01-14-3/+2
| | | | | | | There is no CONFIG_OF_PLATDATA, only CONFIG_SPL_OF_PLATDATA, so rename the two references to CONFIG_OF_PLATDATA to CONFIG_SPL_OF_PLATDATA. Signed-off-by: Tom Rini <trini@konsulko.com>
* arm: Re-sync asm/mach-types.h with Linux Kernel v4.9Tom Rini2017-01-14-14765/+486
| | | | | | | | | | | | This re-syncs the MACH_TYPE_xxx values from the Linux Kernel v4.9 release. In addition this removes all of the machine_arch_type and machine_is_xxx logic that is unused in U-Boot. This removal removes a large number of otherwise unused CONFIG values from the list to be converted. Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Tom Rini <trini@konsulko.com> Tested-by: Adam Ford <aford173@gmail.com>
* arm: Remove unregister MACH_TYPE_xxx usesTom Rini2017-01-14-52/+0
| | | | | | | | | | | | | | | | | | | | | | | | Before we can sync with the latest mach-types.h file from the Linux Kernel we need to remove some instances of MACH_TYPE_xxx from our sources. As these values have been removed from the canonical upstream source we should not be using them either, so drop. Cc: Tom Warren <twarren@nvidia.com> Cc: Lucas Stach <dev@lynxeye.de> Cc: Luka Perkov <luka@openwrt.org> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Heiko Schocher <hs@denx.de> Cc: Thomas Weber <weber@corscience.de> Cc: Lucile Quirion <lucile.quirion@savoirfairelinux.com> Cc: Matthias Weisser <weisserm@arcor.de> Cc: Suriyan Ramasami <suriyan.r@gmail.com> Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Cc: Bo Shen <voice.shen@atmel.com> Cc: Nick Thompson <nick.thompson@gefanuc.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Erik van Luijk <evanluijk@interact.nl> Cc: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* omap3_igep00x0: Rework MACH_TYPE and status LED logic slightlyTom Rini2017-01-14-4/+2
| | | | | | | | | | The MACH_TYPE for IGEP0032 was never officially used and has been removed from upstream, so we must not use it. In order to remove this we need to rework the status LED logic. Cc: Enric Balletbo i Serra <eballetbo@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Enric Balletbo i Serra <eballetbo@gmail.com>
* omap3_logic: Rework MACH_TYPE and fdtfile logicTom Rini2017-01-14-34/+20
| | | | | | | | | | | The MACH_TYPE values for the omap37xx based platforms are no longer officially valid, so we must not set and pass them. In order to not reference them but still be able to set the default fdtfile based on the board detection logic we need to combine the two steps into one. Cc: Adam Ford <aford173@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Adam Ford <aford173@gmail.com>
* Merge git://git.denx.de/u-boot-fdtTom Rini2017-01-14-4/+13
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| * cmd/fdt: Make fdt get value endian-safe for single-cell propertiesAndreas Färber2017-01-14-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On a Raspberry Pi 2 disagreements on cell endianness can be observed: U-Boot> fdt print /soc/gpio@7e200000 phandle phandle = <0x0000000d> U-Boot> fdt get value myvar /soc/gpio@7e200000 phandle; printenv myvar myvar=0x0D000000 Fix this by always treating the pointer as BE and converting it in fdt_value_setenv(), like its counterpart fdt_parse_prop() already does. Consistently use fdt32_t, fdt32_to_cpu() and cpu_to_fdt32(). Fixes: bc80295 ("fdt: Add get commands to fdt") Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Gerald Van Baren <gvb@unssw.com> Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Simon Glass <sjg@chromium.org>
| * cmd: fdt: Print error message when fdt application failsStefan Agner2017-01-13-1/+5
| | | | | | | | | | | | | | | | | | | | There are lots of reason why a FDT application might fail, the error code might give an indication. Let the error code translate in a error string so users can try to understand what went wrong. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Simon Glass <sjg@chromium.org>
| * libfdt: Correct fdt handling of overlays without fixups and base trees ↵David Gibson2017-01-13-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | without symbols The fdt_overlay_apply() function purports to support the edge cases where an overlay has no fixups to be applied, or a base tree which has no symbols (the latter can only work if the former is also true). However it gets it wrong in a couple of small ways: * In the no fixups case, it doesn't fail immediately, but will attempt fdt_for_each_property_offset() giving -FDT_ERR_NOTFOUND as the node offset, which will fail. Instead it should succeed immediately, since there's nothing to do. * In the case of no symbols, it again doesn't fail immediately. However if there is an actual fixup it will fail with an unexpected error, because -FDT_ERR_NOTFOUND is passed to fdt_getprop() when attempting to look up the symbols. We should instead return -FDT_ERR_NOTFOUND directly. Both of these errors lead to the code returning misleading error codes in failing cases. [ DTC commit: 7d8ef6e1db9794f72805a0855f4f7f12fadd03d3 ] Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Simon Glass <sjg@chromium.org>
* | Merge branch 'master' of http://git.denx.de/u-boot-mmcTom Rini2017-01-13-6/+6
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| * mmc: sunxi: revive depends on UART0_PORT_FMasahiro Yamada2017-01-13-1/+1
| | | | | | | | | | | | | | | | | | Commit f401e907fcbc ("ARM: sunxi: remove bare default for CONFIG_MMC") dropped "depends on UART0_PORT_F", but it is still needed. Revive it as a prerequisite of CONFIG_MMC_SUNXI. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * mmc: pic32_sdhci: rename {pci->pic}32_sdhci_get_cdMasahiro Yamada2017-01-13-2/+2
| | | | | | | | | | | | I suspect this is a typo. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * mmc: sdhci: fix NULL pointer access when host->ops is not setMasahiro Yamada2017-01-13-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Until recently, sdhci_ops was used only for overriding IO accessors. (so, host->ops was not set by any drivers except bcm2835_sdhci.c) Now, we have more optional callbacks, get_cd, set_control_reg, and set_clock. However, the code if (host->ops->get_cd) host->ops->get_cd(host); ... expects host->ops is set for all drivers. Commit 5e96217f0434 ("mmc: pic32_sdhci: move the code to pic32_sdhci.c") and commit 62226b68631b ("mmc: sdhci: move the callback function into sdhci_ops") added sdhci_ops for pic32_sdhci.c and s5p_sdhci.c, but the other drivers still do not (need not) set host->ops because all callbacks in sdhci_ops are optional. host->ops must be checked to avoid the system crash caused by NULL pointer access. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | Merge git://git.denx.de/u-boot-rockchipTom Rini2017-01-12-37/+404
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| * | rockchip: Drop Ethernet from the TODOSjoerd Simons2017-01-11-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that ethernet support works, it can be dropped from the rockchip TODO Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Simon Glass <sjg@chromium.org>
| * | rockchip: Enable ETH address randomization for the rock2Romain Perier2017-01-11-0/+1
| | | | | | | | | | | | | | | | | | | | | This commit enables ethernet MAC address randomization on the rock2. It removes the error at startup 'ethernet@ff290000 address not set'. Signed-off-by: Romain Perier <romain.perier@collabora.com>
| * | rockchip: Add PXE and DHCP to the default boot targetsSjoerd Simons2017-01-11-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Now that at least on the firefly board we have network support, enable PXE and DHCP boot targets by default. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | Enable DISTRO_DEFAULTS for Rockchip platformsRomain Perier2017-01-11-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | This enables suitable commands needed for booting general purpose Linux distribution. This is required for example if we want to use PXE or DHCP as default boot targets, symbols no longer enabled by config_distro_defaults.h . Signed-off-by: Romain Perier <romain.perier@collabora.com>
| * | rockchip: evb-rk3339: Enable DHCPSimon Glass2017-01-11-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | This is the only RK3399 device without DHCP. Enable it so that we can use a common BOOT_TARGET_DEVICES setting. It is likely useful to be able to use USB networking, at least. Full networking can be enabled when a suitable platform needs it. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | rockchip: Enable networking support on rock2 and fireflySjoerd Simons2017-01-11-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable the various configuration option required to get the ethernet interface up and running on Radxa Rock2 and Firefly. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Signed-off-by: Romain Perier <romain.perier@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: gmac_rockchip: Add Rockchip GMAC driverSjoerd Simons2017-01-11-0/+162
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a new driver for the GMAC ethernet interface present in Rockchip RK3288 SOCs. This driver subclasses the generic design-ware driver to add the glue needed specifically for Rockchip. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Romain Perier <romain.perier@collabora.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: designware: Export the operation functionsSimon Glass2017-01-11-10/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | Export all functions so that drivers can use them, or not, as the need arises. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Romain Perier <romain.perier@collabora.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: designware: Split the link init into a separate functionSimon Glass2017-01-11-2/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With rockchip we need to make adjustments after the link speed is set but before enabling received/transmit. In preparation for this, split these two pieces into separate functions. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Romain Perier <romain.perier@collabora.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: designware: Adjust dw_adjust_link() to return an errorSimon Glass2017-01-11-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | This function can fail, so return the error if there is one. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Romain Perier <romain.perier@collabora.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: designware: Export various functions/struct to allow subclassingSjoerd Simons2017-01-11-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To allow other DM drivers to subclass the designware driver various functions and structures need to be exported. Export these. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Signed-off-by: Romain Perier <romain.perier@collabora.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | rockchip: video: fix mpixelclock in rockchip HDMINickey Yang Nickey Yang2017-01-11-10/+10
| | | | | | | | | | | | | | | | | | Correct mpixelclock errors in rockchip_phy_config[] and rockchip_mpll_cfg[]. Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
| * | rockchip: rk3288: set isp/vop qos priority levelNickey Yang Nickey Yang2017-01-11-0/+40
| | | | | | | | | | | | | | | | | | | | | | | | Isp-camera preview image will be broken when dual screen display mode. This patch set isp/vop qos level higher to solve this problem. We have verified this patch on rk3288-miniarm board. Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
| * | arm64: rk3399: update rockchip_get_cru APIKever Yang2017-01-11-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | rk3399 has two clock-controller: cru and pmucru, update the rockchip_get_crui() API, and rockchip_get_clk() do not used for other module. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
| * | dts: arm64: rk3399: add max-frequency for sdhciKever Yang2017-01-11-0/+1
| | | | | | | | | | | | | | | | | | | | | Add 'max-frequency' for sdhci node for clock init. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
| * | mmc: rockchip_sdhci: add clock init for mmcKever Yang2017-01-11-2/+17
| | | | | | | | | | | | | | | | | | | | | Init the clock rate to max-frequency from dts with clock driver api. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
| * | rockchip: Fix veyron-minnie's Kconfig descriptionMartin Michlmayr2017-01-11-1/+1
| | | | | | | | | | | | | | | | | | | | | The veyron-minnie Kconfig referred to jerry by mistake. Signed-off-by: Martin Michlmayr <tbm@cyrius.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | rockchip: configs: make rk3036 env config same as rk3288Jacob Chen2017-01-11-3/+14
| | | | | | | | | | | | | | | | | | To make rockchip soc keep the same partition map Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
| * | rockchip: configs: correct env offset when enable ↵Jacob Chen2017-01-11-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_ROCKCHIP_SPL_BACK_TO_BROM With CONFIG_ROCKCHIP_SPL_BACK_TO_BROM enabled, the environment is inside u-boot. So solve it by moving environment after u-boot. Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
| * | rockchip: dts: popmetal: add usb host power supply nodeKever Yang2017-01-11-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The popmetal board using a HOST_VBUS_DRV gpio signal to control the USB host port 5V power, add a fix regulator and pinctrl for it, and enable the USB host1 controller with the vbus-supply. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Added rockchip: tag: Signed-off-by: Simon Glass <sjg@chromium.org>
| * | rockchip: config: popmetal: enable the USB host controller and functionKever Yang2017-01-11-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | RK3288 using the dwc2 USB host controller, enable it and other usb host funtion like storage and ether. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Added rockchip: tag: Signed-off-by: Simon Glass <sjg@chromium.org>
| * | rockchip: board: popmetal: de-assert the host rst pin in board initKever Yang2017-01-11-0/+17
| |/ | | | | | | | | | | | | | | | | | | The PopMetal board have a on board FE1.1 usb 2.0 hub which connect to the usb host port, we need to de-assert its reset pin to enable it. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Added rockchip: tag: Signed-off-by: Simon Glass <sjg@chromium.org>
* | cmd: mem: Use memcpy for 'cp' commandFabio Estevam2017-01-12-26/+2
|/ | | | | | | | | | | Simplify the 'cp' command implementation by using the memcpy() function, which brings the additional benefit of performance gain for those who have CONFIG_USE_ARCH_MEMCPY selected. Tested on a mx6qsabreauto board where a 5x gain in performance is seen when reading 10MB from the parallel NOR memory. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
* SPL: Adjust more debug prints for ulong entry_pointTom Rini2017-01-11-2/+2
| | | | | | | | With entry_point now being an unsigned long we need to adapt the last two debug prints to use %lX not %X. Fixes: 11e1479b9e67 ("SPL: make struct spl_image 64-bit safe") Signed-off-by: Tom Rini <trini@konsulko.com>
* power_i2c.c: Fix unused variable warningTom Rini2017-01-11-1/+0
| | | | | | | | The variable ret was added but never set as we did not make calls to other functions that we needed to check the return value on. Fixes: 505cf4750ae5 ("power: change from meaningless value to error number") Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge tag 'xilinx-for-v2017.03' of git://www.denx.de/git/u-boot-microblazeTom Rini2017-01-11-63/+489
|\ | | | | | | | | | | | | | | | | | | Xilinx changes for v2017.03 - ATF handoff - DT syncups - gem: Use wait_for_bit(), add simple clk support - Simple clk driver for ZynqMP - Other small changes
| * ARM64: zynqmp: Move CONFIG_AHCI from board fileMichal Simek2017-01-11-1/+1
| | | | | | | | | | | | Move configuration option from board file to defconfig. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * xilinx_phy: Pass correct pointer to fdtdec_get_int()Kamensky Ivan2017-01-11-2/+2
| | | | | | | | | | | | | | | | | | | | | | This patch fixes incorrect pointer on offset device in device tree blob. When using with the component "Ethernet 1G/2.5G BASE-X PCS/PMA or SGMII" it does not understand what type is XAE_PHY_TYPE_1000BASE_X and trying to change frequency. Signed-off-by: Kamensky Ivan <kamensky.ivan@mail.ru> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * ARM64: zynqmp: Generate handoff structure for ATFMichal Simek2017-01-10-1/+101
| | | | | | | | | | | | | | | | | | | | | | | | | | Xilinx ATF extending options for passing images from BL2(FSBL) to BL31. U-Boot SPL is FSBL replacement that's why it should generate handoff structure the same. Support only one entry which is U-Boot in EL2 itself. When FIT image is adopted structure generate should be data driven. Currently ATF is placing this structure at the beggining of OCM which is rewriting early parts of ATF which should be unused at that time. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * fpga: Use enum for bitstream command typesMichal Simek2017-01-10-9/+11
| | | | | | | | | | | | | | Using enum simplify handling of different bitstream command types. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * ARM: zynqmp: Make SYS_VENDOR configurableMike Looijmans2017-01-10-0/+1
| | | | | | | | | | | | | | Add a string description for SYS_VENDOR to allow configuring boards from other vendors than just "xilinx". Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * ARM64: zynqmp: Fix i2c node's compatible stringMoritz Fischer2017-01-10-2/+2
| | | | | | | | | | | | | | | | | | | | | | The Zynq Ultrascale MP uses version 1.4 of the Cadence IP core which fixes some silicon bugs that needed software workarounds in Version 1.0 that was used on Zynq systems. Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Heiko Schocher <hs@denx.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * i2c: cdns: Add additional compatible string for r1p14 of the IP.Moritz Fischer2017-01-10-0/+1
| | | | | | | | | | | | | | | | | | Adding additional compatible string for version 1.4 of the IP block. Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Heiko Schocher <hs@denx.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * net: zynq_gem: Use clock driver for ZynqMPSiva Durga Prasad Paladugu2017-01-10-0/+20
| | | | | | | | | | | | | | | | | | Enable and use the clock driver routine defined in clock driver toset required clock appropriately. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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