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* arm: socfpga: Add samtec VIN|ING boardMarek Vasut2016-06-01-1/+1833
| | | | | | | | | | | | | | | | | Add support for board based on the popular Altera Cyclone V SoC. This board has the following properties: - 1 GiB of DRAM - 1 Gigabit ethernet - 1 USB gadget port - 1 USB host port with an on-board hub - 2 QSPI NORs connected to the Cadence QSPI core - Multiple I2C EEPROMs and one I2C temperature sensor Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com> --- V2: Update the defconfig as per Tom's request
* spl: fit: Fix load address of fit headerLokesh Vutla2016-06-01-2/+2
| | | | | | | When loading fit header, it should be loaded to a previous address aligned to ARCH_DMA_MINALIGN and not 8. Fixing the same. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mipsTom Rini2016-05-31-204/+1412
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| * mips: ath79: ap143: Reset ethernet on bootWills Wang2016-05-31-0/+2
| | | | | | | | | | | | This patch reset the ethernet controller for ap143 board Signed-off-by: Wills Wang <wills.wang@live.com>
| * mips: ath79: Use AR933X_PLL_SWITCH_CLOCK_CONTROL_REG macro defineWills Wang2016-05-31-1/+2
| | | | | | | | | | | | Add AR933X_PLL_SWITCH_CLOCK_CONTROL_REG define for ar933x chip. Signed-off-by: Wills Wang <wills.wang@live.com>
| * mips: ath79: Add support for ungating USB and ethernet on qca953xWills Wang2016-05-31-0/+50
| | | | | | | | | | | | Add code to ungate USB and ethernet controller on qca953x Signed-off-by: Wills Wang <wills.wang@live.com>
| * mips: ath79: Use 8MB flash profile for mtd partition by defaultWills Wang2016-05-31-5/+5
| | | | | | | | | | | | Change bootm flash address and mtd partition table for 8MB flash profile. Signed-off-by: Wills Wang <wills.wang@live.com>
| * mips: ath79: ap121: Enable ethernetWills Wang2016-05-31-4/+16
| | | | | | | | | | | | | | This patch enable network function for ap121 board. Signed-off-by: Wills Wang <wills.wang@live.com> Acked-by: Marek Vasut <marex@denx.de>
| * mips: ath79: Rename get_bootstrap into ath79_get_bootstrapWills Wang2016-05-31-28/+15
| | | | | | | | | | | | | | | | Add a platform prefix for function name in order to make more readable, and move it into ath79.h Signed-off-by: Wills Wang <wills.wang@live.com> Acked-by: Marek Vasut <marex@denx.de>
| * MIPS: malta: add defconfigs for MIPS64Daniel Schwierzeck2016-05-31-0/+33
| | | | | | | | | | | | | | Add defconfigs for recently introduced MIPS64 support on Malta boards to get more build coverage for MIPS64. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * MIPS: Abstract cache op loops with a macroPaul Burton2016-05-31-41/+18
| | | | | | | | | | | | | | | | | | | | | | The various cache maintenance routines perform a number of loops over cache lines. Rather than duplicate the code for performing such loops, abstract it out into a new cache_loop macro which performs an arbitrary number of cache ops on a range of addresses. This reduces duplication in the existing L1 cache maintenance code & will allow for not adding further duplication when introducing L2 cache support. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * MIPS: Split I & D cache line size configPaul Burton2016-05-31-28/+53
| | | | | | | | | | | | | | | | | | | | | | | | Allow L1 Icache & L1 Dcache line size to be specified separately, since there's no architectural mandate that they be the same. The [id]cache_line_size functions are tidied up to take advantage of the fact that the Kconfig entries are always present to simply check them for zero rather than needing to #ifdef on their presence. Signed-off-by: Paul Burton <paul.burton@imgtec.com> [removed CONFIG_SYS_CACHELINE_SIZE in include/configs/pic32mzdask.h] Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * MIPS: Move cache sizes to KconfigPaul Burton2016-05-31-53/+95
| | | | | | | | | | | | | | | | | | | | | | | | Move details of the L1 cache line sizes & total sizes into Kconfig, defaulting to 0. A new CONFIG_SYS_CACHE_SIZE_AUTO Kconfig entry is introduced to allow platforms to select auto-detection of cache sizes, and it defaults to being enabled if none of the cache sizes are set by the configuration (ie. sizes are all the default 0), and code is adjusted to #ifdef on that rather than on the definition of the sizes (which will always be defined even if 0). Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * MIPS: remove dead code from asm/u-boot-mips.hDaniel Schwierzeck2016-05-31-18/+3
| | | | | | | | | | | | | | | | Those wrappers for linker symbols were once used in the MIPS specific board.c implementation. Since the migration to generic board.c, those wrappers are dead code and can be removed. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * net: Add ag7xxx driver for Atheros MIPSMarek Vasut2016-05-31-0/+990
| | | | | | | | | | | | | | | | | | | | | | | | Add ethernet driver for the AR933x and AR934x Atheros MIPS machines. The driver could be easily extended to other WiSoCs. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Wills Wang <wills.wang@live.com> [fixed Kconfig dependency] Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * MIPS: add tune for MIPS 34kcDaniel Schwierzeck2016-05-31-0/+4
| | | | | | | | | | | | Add tune Kconfig option for MIPS 34kc. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * MIPS: provide a default u-boot-spl.ldsDaniel Schwierzeck2016-05-31-2/+93
| | | | | | | | | | | | | | | | | | | | | | | | Provide a default linker script for SPL binaries. Start address and size of text section and BSS section are configurable. All sections are arranged in a way that only relevant sections are kept in the code section for maximum size reduction. All other sections are kept but moved outside the code section to help with debugging. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Acked-by: Marek Vasut <marex@denx.de>
| * malta: Allow MIPS64 buildsPaul Burton2016-05-31-12/+25
| | | | | | | | | | | | | | | | Both real Malta boards & emulators that mimic Malta (eg. QEMU) can support MIPS64 CPUs. Allow MIPS64 builds of U-Boot for such boards, which enables the user to make use of the whole 64 bit address space. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * net: pcnet: Fix init on big endian 64 bitPaul Burton2016-05-31-3/+3
| | | | | | | | | | | | | | | | | | | | If dev->iobase is 64 bits wide then writing the value of the BAR into a pointer to iobase will not work on big endian systems, where the BAR value will incorrectly get written to the upper 32 bits of the 64 bit variable. Fix this by reading the BAR into a u32, matching the type expected by pci_read_config_dword. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * net: pcnet: Make 64 bit safePaul Burton2016-05-31-8/+10
| | | | | | | | | | | | | | | | Fix the pcnet driver to build safely on 64 bit platforms, in preparation for allowing MIPS64 builds for Malta boards. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * net: pcnet: Stop converting kseg1->kseg0 addressesPaul Burton2016-05-31-9/+6
| | | | | | | | | | | | | | | | Now that MIPS virt_to_phys can handle kseg1 addresses on MIPS32, stop manually converting addresses to their kseg0 equivalents in the pcnet driver. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * MIPS: Use CPHYSADDR to implement mips32 virt_to_physPaul Burton2016-05-31-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use CPHYSADDR to implement the virt_to_phys function for converting from a virtual to a physical address for MIPS32, much as is already done for MIPS64. This allows for virt_to_phys to work regardless of whether the address being translated is in kseg0 or kseg1, unlike the previous subtraction based approach which only worked for addresses in kseg0. This allows for drivers to provide an address to virt_to_phys without needing to manually ensure that kseg1 addresses are converted to equivalent kseg0 addresses first. This patch is equivalent to this Linux patch currently waiting to be reviewed & merged: https://patchwork.linux-mips.org/patch/12564/ Signed-off-by: Paul Burton <paul.burton@imgtec.com>
* | Merge git://www.denx.de/git/u-boot-marvellTom Rini2016-05-31-21/+63
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| * | arm: spear: x600: Remove EFI support to reduce image sizeStefan Roese2016-05-31-0/+1
| | | | | | | | | | | | | | | | | | | | | EFI is not needed on x600. So lets remove the EFI support to make it fit into the 0x60000 image size limit again. Signed-off-by: Stefan Roese <sr@denx.de>
| * | arm: spear: x600: Add support for Micrel KSZ9031 PHYStefan Roese2016-05-31-21/+61
| | | | | | | | | | | | | | | | | | | | | | | | As the old ethernet PHY is not available any more, the x600 board has been redesigned with the Micrel KSZ9031 PHY. This patch adds support to autodetect the PHY and configure the Micrel PHY correctly. Signed-off-by: Stefan Roese <sr@denx.de>
| * | clearfog: add HUSH parserPeter Robinson2016-05-31-0/+1
| |/ | | | | | | | | | | | | | | In the big move of CONFIG_HUSH_PARSER to config files the clearfog somehow missed out. Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | tools/env: allow to pass NULL for environment optionsAndreas Fenkart2016-05-31-3/+24
| | | | | | | | | | | | | | | | | | | | If users of the library are happy with the default, e.g. config file name. They can pass NULL as the opts pointer. This simplifies the transition of existing library users. FIXES a compile error. since common_args has been removed by a previous patch Signed-off-by: Andreas Fenkart <andreas.fenkart@digitalstrom.com>
* | Revert "image.h: Tighten up content using handy CONFIG_IS_ENABLED() macro."Masahiro Yamada2016-05-31-12/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 56adbb38727320375b2f695bd04600d766d8a1b3. Since commit 56adbb387273 ("image.h: Tighten up content using handy CONFIG_IS_ENABLED() macro."), I found my boards fail to boot Linux because the commit changed the logic of macros it touched. Now, IMAGE_ENABLE_RAMDISK_HIGH and IMAGE_BOOT_GET_CMDLINE are 0 for all the boards. As you can see in include/linux/kconfig.h, CONFIG_IS_ENABLE() (and IS_ENABLED() as well) can only take a macro that is either defined as 1 or undefined. This is met for boolean options defined in Kconfig. On the other hand, CONFIG_SYS_BOOT_RAMDISK_HIGH and CONFIG_SYS_BOOT_GET_CMDLINE are defined without any value in arch/*/include/asm/config.h . This kind of clean-up is welcome, but the options should be moved to Kconfig beforehand. Moreover, CONFIG_IS_ENABLED(SPL_CRC32_SUPPORT) looks weird. It should be either CONFIG_IS_ENABLED(CRC32_SUPPORT) or IS_ENABLED(CONFIG_SPL_CRC32_SUPPORT). But, I see no define for CONFIG_SPL_CRC32_SUPPORT anywhere. Likewise for the other three. The logic of IMAGE_OF_BOARD_SETUP and IMAGE_OF_SYSTEM_SETUP were also changed for SPL. This can be a problem for boards defining CONFIG_SPL_OF_LIBFDT. I guess it should have been changed to IS_ENABLED(CONFIG_OF_BOARD_SETUP). In the first place, if we replace the references in C code, the macros IMAGE_* will go away. if (IS_ENABLED(CONFIG_OF_BOARD_SETUP) { ... } Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-x86Tom Rini2016-05-30-32/+685
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| * x86: baytrail: acpi: Fix I/O APIC ID in the MADT tableBin Meng2016-05-30-1/+1
| | | | | | | | | | | | | | | | So far this is hardcoded to 2, but it should really be read from the I/O APIC register. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * x86: galileo: Enable ACPI table generationBin Meng2016-05-30-1/+34
| | | | | | | | | | | | | | Enable ACPI table generation by creating a DSDT table. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * x86: quark: Generate ACPI FADT/MADT tablesBin Meng2016-05-30-0/+164
| | | | | | | | | | | | | | Generate quark platform-specific FADT/MADT tables. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * x86: quark: Add platform ASL filesBin Meng2016-05-30-0/+433
| | | | | | | | | | | | | | | | This adds basic quark platform ASL files. They are intended to be included in dsdt.asl of any board that is based on this platform. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * x86: quark: Prepare device.h for inclusion by ASLBin Meng2016-05-30-6/+15
| | | | | | | | | | | | | | | | | | There is a device.h for quark on-chip devices, mainly for definitions of internal PCI device numbers, but it's not ready to be included by ASL files. Update to use hex numbers for PCI dev and __ASSEMBLY__. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * acpi: Pass -D__ASSEMBLY__ when compiling ASL filesBin Meng2016-05-30-1/+1
| | | | | | | | | | | | | | | | | | | | ASL files may include various U-Boot header files, but IASL compiler does not understand any C language embedded in these header files. To reuse those header files for ASL compiling, use __ASSEMBLY__ in the header files to exclude everything that is not liked by IASL. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * x86: acpi: Make irqroute.asl commonBin Meng2016-05-30-2/+2
| | | | | | | | | | | | | | | | | | | | The irqroute.asl file is already common enough to all x86 platforms. Platform ASL files need only provide a irqroute.h to describe how internal PCI devices and PCIe downstream port devices' INTx pins are routed to which PIRQ pin. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * x86: acpi: Create a common irqlinks ASL fileBin Meng2016-05-30-21/+35
| | | | | | | | | | | | | | | | | | | | | | Move the irqlinks.asl file currently in the BayTrail directory to a common place to be shared among all x86 platforms. As the PIRQ routing control programming interface is common to Intel chipsets, leave the common part in the common file, and move the platform specific part to the platform files. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | Merge git://git.denx.de/u-boot-dmTom Rini2016-05-27-510/+1272
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For odroid-c2 (arch-meson) for now disable designware eth as meson now needs to do some harder GPIO work. Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: lib/efi_loader/efi_disk.c Modified: configs/odroid-c2_defconfig
| * | dm: rockchip: Enable CONFIG_BLKSimon Glass2016-05-27-0/+3
| | | | | | | | | | | | | | | | | | | | | Enable CONFIG_BLK to move to using driver model for block devices. This affects MMC booting in SPL, as well as MMC access in U-Boot proper. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dm: mmc: Use cfg directly in mmc_bind()Simon Glass2016-05-27-1/+1
| | | | | | | | | | | | | | | | | | This small change tidies up the code slightly. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dm: mmc: Fix up mmc_bread/bwrite() prototypes for SPLSimon Glass2016-05-27-0/+14
| | | | | | | | | | | | | | | | | | | | | When these functions are not compiled in, we still need to declare the correct function signature to avoid a build warnings in SPL. Fix this. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dm: rockchip: mmc: Allow use of CONFIG_BLKSimon Glass2016-05-27-0/+31
| | | | | | | | | | | | | | | | | | Allow driver model to be used for block devices in the rockchip mmc driver. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dm: mmc: dwmmc: Support CONFIG_BLKSimon Glass2016-05-27-15/+34
| | | | | | | | | | | | | | | | | | Add support for using driver model for block devices in this driver. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dm: mmc: spl: Add support for CONFIG_BLKSimon Glass2016-05-27-5/+4
| | | | | | | | | | | | | | | | | | Allow driver model to be used for block devices in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dm: efi: Update for CONFIG_BLKSimon Glass2016-05-27-16/+47
| | | | | | | | | | | | | | | | | | | | | | | | This code does not currently build with driver model enabled for block devices. Update it to correct this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Alexander Graf <agraf@suse.de>
| * | dm: mmc: Convert sdhci to support CONFIG_BLKSimon Glass2016-05-27-1/+1
| | | | | | | | | | | | | | | | | | Update sdhci.c so that it works with driver model enabled for block devices. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dm: env: mmc: Convert env_mmc to support CONFIG_BLKSimon Glass2016-05-27-4/+4
| | | | | | | | | | | | | | | | | | | | | Update the MMC environment code so that it works with driver-model enabled for block devices. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | rockchip: Drop SPL GPIO support for rk3288Simon Glass2016-05-27-1/+0
| | | | | | | | | | | | | | | | | | This is not currently used and saves a little over 1KB of SPL image size. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | rockchip: video: Flush the cache when the display is updatedSimon Glass2016-05-27-0/+1
| | | | | | | | | | | | | | | | | | | | | Enable this option to correct display artifacts when a write-back cache is in use. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | rockchip: Drop unnecessary SPL propertiesSimon Glass2016-05-27-1/+1
| | | | | | | | | | | | | | | | | | | | | While we consider whether to drop use of DT in SPL, remove some unwanted properties. This reduces SPL size by about 250 bytes. Signed-off-by: Simon Glass <sjg@chromium.org>
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