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* MLK-12066 imx: mx7: default enable MDIO open drainPeng Fan2015-12-23-0/+22
| | | | | | | | | The management data input/output (MDIO) requires open-drain, i.MX7D TO1.0 ENET MDIO pin has no open drain, but TO1.1 supports this feature. So to TO1.1, need to enable open drain by setting bits GPR0[8:7] for TO1.1. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-11811: imx: mx6qarm2: add new board revision supportAdrian Alonso2015-12-18-0/+301
| | | | | | | | | | | | Add mx6qarm2 new board revision support using mx6q pop SoC Enable DRAM support for imx6q PoP SoC with populated LPDDR2 MT42L128M64D2 DDR calibration script http://sw-stash.freescale.net/projects/IMX/repos/ddr-scripts-rel/commits/e5c6184940486bcbc28978d60ad3cd996c205a08 Test result: Stress test passed. Signed-off-by: Adrian Alonso <aalonso@freescale.com>
* MLK-12034 imx: mx7dsabresd: Add RevB board supportYe.Li2015-12-18-44/+158
| | | | | | | | | | | | | Since i.MX7D SDB revB board has some HW changes, we have modify the BSP file to support new pinmux. 1. OTG2 PWR pin is changed to GPIO1_IO07. 2. A enet2_en pin is added for isolating enet2 signals with EPDC, we also add support for enet2. 3. pin6 of 74LV output is changed for CSI PWDN. Set output to high to power down it. This patch also tries to get the board id and apply changes according with it. Since current RevB board does not burn GP1 fuse for board id, we have to check the TO rev instead even it is not very exact. Will update this if any new way implemented. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-12017 imx: mx6ulevk: Update DDR script for new DDR MT41K256M16TW-107Ye.Li2015-12-17-0/+203
| | | | | | | | | | | | | | | | | | | Current Micron DDR MT41K256M16HA-125 on i.MX6UL will be EOL. Plan is i.MX6UL will use the new 20nm litho 4Gb DDR3L MT41K256M16TW-107. Update DDR script of mx6ul evk board for this new DDR, and use it as default. http://compass.freescale.net/livelink/livelink?func=ll&objId=234910940&objAction=browse&viewType=1 Test result: Stress test passed. Meanwhile add build targets below for old DDR support: mx6ul_14x14_evk_ddr_eol_android_defconfig mx6ul_14x14_evk_ddr_eol_brillo_defconfig mx6ul_14x14_evk_ddr_eol_defconfig mx6ul_14x14_evk_ddr_eol_qspi1_defconfig Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-12030: imx: mx7d: fix the temperature checking for TO1.1Peng Fan2015-12-17-9/+26
| | | | | | | We can rely on finish bit for temperature reading for TO1.1. Also introduce CHIP_REV_xx macros for 7D. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-11995 ARM: imx7: add i.mx7d TO1.1 support for LPSR modeAnson Huang2015-12-16-6/+16
| | | | | | | | i.MX7D TO1.1 changes DDR retension mode control to IOMUXC_GPR, add support to this change for LPSR which needs to exit from DDR retension mode. Signed-off-by: Anson Huang <Anson.Huang@freescale.com>
* MLK-12001 MMC:USDHC: Clear DLL_CTRL delay line settings at driver initYe.Li2015-12-14-0/+3
| | | | | | | | | | | | Clear DLL_CTRL delay line settings at USDHC initialization to eliminate the pre-settings from boot rom. U-boot should re-init the USDHC not reply on the value set by boot from. On MX6DL, the ROM has set the default delay line(DLLCTRL) to 0x1000021, when eMMC works on DDR mode in kernel, it will possibly cause data CRC errors. Even u-boot always use eMMC in SDR mode, for safety sake, it is better to clear it too. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-11991 arm: config: change imx7d arm2 nand rootfs mtd partition indexHan Xu2015-12-09-1/+1
| | | | | | | change the imx7d arm2 nand rootfs partition index from 3 to 4 since the weim nor was enabled by default and took the first mtd partition. Signed-off-by: Han Xu <b45815@freescale.com>
* MLK-11952 Video: IPU: Fix dereferencing NULL pointer problemYe.Li2015-12-04-0/+4
| | | | | | | | By Coverity check, the clk_set_rate function dereferences the clk pointer without checking whether it is NULL. This may cause problem when clk is NULL. Fix the problem by adding NULL check. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-11951 pfuze: Fix unsigned variable for less-than-zero comparisonYe.Li2015-12-04-1/+2
| | | | | | | | According to the Coverity result, a unsigned int variable is used fo less- than-zero comparison, the result is never true. Need to fix the variable type to signed int. Signed-off-by: Ye.Li <B37916@freescale.com>
* MA-7330-1 change tool chain to gcc4.9 for android kernel and ubootZhang Sanshan2015-12-04-0/+3
| | | | | | | | uboot will fail when loader zImage which is larger than 9M. Increasing CONFIG_SYS_BOOTM_LEN from 8 MB to 16 MB is necessary to support uncompressing images larger than 8 MB. Signed-off-by: Zhang Sanshan <b51434@freescale.com>
* MLK-11946 arm: config: disable pic when compiling codePeng Fan2015-12-03-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Android's tool chain enable the -mandroid at default. This option will enable the -fpic, which cause uboot compilation failure: " LD u-boot u-boot contains unexpected relocations: R_ARM_ABS32 R_ARM_RELATIVE " In my testcase, arm-linux-androideabi-gcc-4.9 internally enables '-fpic', so when compiling code, there will be relocation entries using type R_ARM_GOT_BREL and .got section. When linking all the built-in.o using ld, there will be R_ARM_ABS32 relocation entry and .got section in the final u-boot elf image. This can not be handled by u-boot, since u-boot only expects R_ARM_RELATIVE relocation entry. arm-poky-linux-gnueabi-gcc-4.9 default does not enable '-fpic', so there is not .got section and R_ARM_GOT_BREL in built-in.o. And in the final u-boot elf image, all relocation entries are R_ARM_RELATIVE. we can pass '-fno-pic' to xxx-gcc to disable pic. whether the toolchain internally enables or disables pic, '-fno-pic' can work well. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-11897 video: ipu: fix out of bounds accessPeng Fan2015-11-27-2/+3
| | | | | | | | | We need to access reg stp_rep9, but not stp_rep[(9 - 1) / 2]. If using "__raw_writel(0, DI_STP_REP(disp, 9))", this will exceeds the size of stp_rep array. Acked-by: Liu Ying <Ying.Liu@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-11892 imx: boards: fix variable typePeng Fan2015-11-24-7/+15
| | | | | | | ret should not use unsigned integer. Should use signed interger to compare against 0. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MA-7291 - [evk6ul-brillo] - In brillo, need enlarge CONFIG_SYS_BOOTM_LENfang hui2015-11-20-0/+2
| | | | | | | birllo use gcc-4.9 to compile kernel, zImage is large then 8M. set CONFIG_SYS_BOOTM_LEN to 16M Signed-off-by: fang hui <b31070@freescale.com>
* Revert "MA-7053 when I add selinux=disable in the cmdline, the board do OTA ↵zhang sanshan2015-11-17-34/+2
| | | | | | | | | update will fail" This reverts commit 24356fe059abbc9eae1b192f7af8a46f204a36f4. Conflicts: common/image-android.c
* MA-7251 - [evk_6ul]: Support boot conctrol for brillofang hui2015-11-13-24/+607
| | | | | | | | | brillo need bootlader support boot control. bootlader can choose which slot(partition) to boot based on it's tactic. The commit support boot control for evk6ul Signed-off-by: fang hui <b31070@freescale.com>
* MLK-11837 mfgtool: add dummy fat file to avoid windows popup format dialogFrank Li2015-11-11-0/+9
| | | | | | | | | Windows DeviceIoControl SCSI_PASSTHROUGH is not stable when report media is not ready. Use dummy fat file to workaround this issue and avoid windows popup format dialog. Signed-off-by: Frank Li <Frank.Li@freescale.com>
* MLK-11825 imx: mx6dqp: update ddr script to 1.13Peng Fan2015-11-09-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | http://sw-stash.freescale.net/projects/IMX/repos/ddr-scripts-rel/commits/8111e4d0cd81226899be637013048281e3c097b4 http://compass.freescale.net/livelink/livelink?func=ll&objId=234753630&objAction=browse&viewType=1 arik_r2_sabre_ddr3_528_1.13.inc is for sabre-AI arik_r2_sdb_ddr3_528_1.13.inc is for sabresd 1.13<-1.12: Change log: 1. Remove 20c4080 1.12<-1.10 Change log: 1. NoC register DDRCONF change to 0 which is compatible for only CS0 is used on board 2. Change 2 values to compatible with our DDR aid script, these two registers doesn’t have any effect on current system tRPA = 0; //this bit only used in DDR2 mode tAOFPD/tAONPD=0x4; //These register only works when MDPDC. SLOW_PD = 1 which is 0 in script Test results: One mx6qp-sdb and one mx6qp-ard board and one mx6qp-ard board passed 60 hours memtester stress teset. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MA-7157 Check the error log in fastboot flashzhang sanshan2015-11-06-0/+2
| | | | | | | | The fastboot.exe will get var partition-type:* firstly when "fastboot flash * *". The uboot did not support get var partition-type: default. This patch mask info the error when gat cat partition-type. Signed-off-by: zhang sanshan <b51434@freescale.com>
* MA-7053 when I add selinux=disable in the cmdline, the board do OTA update ↵zhang sanshan2015-11-06-3/+34
| | | | | | | | | | | will fail The ota update script will set selinux label with set_metadata when do nand ota update. The root cause is set_metadata will fail if disable selinux in recovery mode. This patch is a workaround which will enable selinux in recovery mode, even if have disable selinux in commandline. Signed-off-by: zhang sanshan <b51434@freescale.com>
* MLK-11823 USB:gadget Fix USB port interface issue in ci_udc driverYe.Li2015-11-04-1/+1
| | | | | | | | | | | | | The ci_udc driver tries to use the ULPI interface for the USB OTG controller, but this type is not supported by all i.MX6 and i.MX7 platforms. When setting to ULPI, other platforms except the 6UL refuse the settings and keep default value. But on 6UL, the PTW bit of PORTSC1 register which is documented as RO can change. This cause the interface setting problem with USB PHY. Fix the issue by removing the ULPI setting for i.MX6 and i.MX7. All will use default UTMI setting. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-11784 imx: mx7: uboot plugin change for mfgtoolYe.Li2015-11-02-0/+19
| | | | | | | | | | Fixed the issue that mfgtool failed to download u-boot with plugin enabled. The u-boot plugin common codes should not call rom___pu_irom_hwcnfg_setup when using serial download mode. rom___pu_irom_hwcnfg_setup will load the IVT2 image from boot media, but this is invalid for USB serial download mode. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-11795-02 imx: upate the pmic standby voltage for imx6qpBai Ping2015-10-30-28/+47
| | | | | | | | | | According to the latest datasheet(Rev. B, 07/2015), the VDD_SOC_IN standby voltage should be 1.05V and on i.MX6QP, we can use the PMIC 'APS' mode in standby. we add a 25mV margin to cover the IR drop and board tolerance, so the standby voltage of VDD_SOC_IN should be setting to 1.075V. Signed-off-by: Bai Ping <b51503@freescale.com>
* MLK-11795-01 imx: correct the vdd_arm regulator setting on imx6qpBai Ping2015-10-30-45/+101
| | | | | | | | | on i.MX6QP SDB board, the SW1A/B/C regulator is used by VDD_SOC_IN, the regulator of VDD_ARM_IN is SW2, the voltage setting for VDD_ARM_IN should be corresponding to SW2. So fix the regulator mismatch issue on i.MX6QP SDB board. Signed-off-by: Bai Ping <b51503@freescale.com>
* MLK-11799 imx: mx6qpsdb: update ddr script to 1.10Peng Fan2015-10-30-4/+4
| | | | | | | | | | | | | http://sw-stash.freescale.net/projects/IMX/repos/ddr-scripts-rel/commits/963fbc75ef6d36e12819e81de23410749754e5ef http://compass.freescale.net/livelink/livelink?func=ll&objId=234709279&objAction=browse&viewType=1 Main change: (SDB board ddr density is different) 1. tRFC is different with density, tXS/tXPR refers tRFC Test Results: 2 MX6DP-SDB and 2 MX6QP-SDB boards passed overnight stress test. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-11767:imx: Modify the u-boot ENV offset for NAND storageYe.Li2015-10-27-7/+7
| | | | | | | | The current 36M offset will conflict with NAND FCB firmware2 when the nand chip block is 1MB size. This patch change it to 36M + 1M offset, so the redundant u-boot at firmware2 will not be broken. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-11753 imx: mx6dqp: update ddr script to v1.09Peng Fan2015-10-23-7/+17
| | | | | | | | | | | | | | | | | | | | | | ddr script update to 1.09: http://compass.freescale.net/livelink/livelink?func=ll&objId= 234694528&objAction=browse&viewType=1 arik_r2_sabre_ddr3_528_1.09.inc is for sabre-auto board. arik_r2_sdb_ddr3_528_1.09.inc is for sabre-sd board. Changelog: 1. Optimize DQS duty cycle setting 2. Optimize ZQ PU/PD value Test results: 2 ARD boards. 2 6QP-SDB boards. 1 6DP-SDB board. All passed overnight memtester stress test. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit ba8dcef9d8e10e46130559ce6defe4411bd1d1a6)
* MLK-11721 imx: mx6q/dl/solo: default support SPI-NOR for sdb boardsPeng Fan2015-10-16-5/+5
| | | | | | | | 1. Default support SPI-NOR for imx6q/dl/solo sabresd board. 2. Fix bug for mx6soloxxx_spinor_defconfig. "nosmp" should be \"nosmp\". Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-11706: imx6sx: SabreSD: Expand malloc pool to 32MSandor Yu2015-10-16-1/+1
| | | | | | | | | | | Same issue as ENGR00321137, commit 3695635. GIS module need total 3M+3M+1.5M+1.5M=9M video memory. and sys reserved 16M memory for malloc. When gis module enabled, malloc may failed to allocate memory for other modules, that may cause system hang. Expand malloc pool to 32M. Signed-off-by: Sandor Yu <R01008@freescale.com>
* MLK-11718-3: imx: change the NAND env setting addressHan Xu2015-10-15-8/+8
| | | | | | | | The previous 8M address for NAND env might conflict with other boot parameters as the NAND block size increasing, change it to 36M to avoid it. Signed-off-by: Han Xu <b45815@freescale.com>
* MLK-11718-2: mtd: nand: change the BCH layout setting for large oob NANDHan Xu2015-10-15-23/+113
| | | | | | | | | | | | | | | | | | | | | | | | | | The cod change updated the NAND driver BCH ECC layout algorithm to support large oob size NAND chips(oob > 1024 bytes). Current implementation requires each chunk size larger than oob size so the bad block marker (BBM) can be guaranteed located in data chunk. The ECC layout always using the unbalanced layout(Ecc for both meta and Data0 chunk), but for the NAND chips with oob larger than 1k, the driver cannot support because BCH doesn’t support GF 15 for 2K chunk. The change keeps the data chunk no larger than 1k and adjust the ECC strength or ECC layout to locate the BBM in data chunk. General idea for large oob NAND chips is 1.Try all ECC strength from the minimum value required by NAND spec to the maximum one that works, any ECC makes the BBM locate in data chunk can be chosen. 2.If none of them works, using separate ECC for meta, which will add one extra ecc with the same ECC strength as other data chunks. This extra ECC can guarantee BBM located in data chunk, of course, we need to check if oob can afford it. Signed-off-by: Han Xu <b45815@freescale.com>
* MLK-11718-1: mtd: nand: change the maximum nange page size and oob sizeHan Xu2015-10-15-2/+2
| | | | | | | enlarge the maximum nand page size and oob size to 16k byte and 1280byte. Signed-off-by: Han Xu <b45815@freescale.com>
* MLK-11675 ARM: imx: change the VDD_SOC normal voltage to 0.975VBai Ping2015-10-13-0/+37
| | | | | | | | | According to the latest datasheet(Rev. C Draft 1, 10/2015) of i.MX7D, change the VDD_SOC voltage to 0.95V in run mode, and add a 25mV margin to cover the IR drop and board tolerance. So setting VDD_SOC voltage to 0.975V. Signed-off-by: Bai Ping <b51503@freescale.com>
* MLK-11682 imx: mx6ul: Update DDR script of 14x14 EVK board to 1.2 revYe.Li2015-10-10-21/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | IC team releases new DDR script "EVK_IMX6UL_DDR3L_400MHz_16bit_V1.2.inc", update it to DCD and plugin for i.MX6UL 14x14 EVK board. Updated items: Removed: 0x020c4084 0x021B0858 Value changed: 0x020E027C 0x020E0280 0x021B0008 0x021B000C 0x021B0010 0x021B0018 0x021B08C0 The script versions of EVK board and Validation Board from the following link: http://compass.freescale.net/livelink/livelink?func=ll&objId=234191407&obj Action=browse&viewType=1 Test Results: Two boards passed overnight memtester stress test. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-11662-2 imx: mx6ul: Modify the MMDC automatic Power saving timerYe.Li2015-09-30-1/+1
| | | | | | | | The PST bit can't be set too small which will cause performance drop. Refer the commit for same issue on MX6UL 9x9 EVK, now fix it for 14x14 LPDDR2 ARM2 commit e1ca547d198dde94c4d8278c99499ec2d2008880 Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-11662-1 imx: mx6ul: Change 14x14 LPDDR2 ARM2 memory size to 256MBYe.Li2015-09-30-2/+10
| | | | | | | The actual memory size is 256MB not 512MB, otherwise it has a wrap problem in memory and will cause memtester failed. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-11622 imx6dqp-sabresd: update ddr script to v1.08Robby Cai2015-09-24-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | enable bank interleave feature to improve the performance downloaded from http://compass.freescale.net/livelink/livelink?func=ll&objId=234609508&objAction=browse&viewType=1 Before: $ /opt/fsl-samples/g2d/g2d_test Width 1920, Height 1088, Format RGBA, Bpp 32 ---------------- g2d blit performance ---------------- g2d blit time 15566us, 64fps, 134Mpixel/s ........ g2d blending time 20672us, 48fps, 101Mpixel/s ........ g2d blend-dim time 13616us, 73fps, 153Mpixel/s ........ ---------------- g2d clear performance ---------------- g2d clear time 8433us, 118fps, 247Mpixel/s ........ ---------------- g2d rotation performance ---------------- 90 rotation time 15366us, 65fps, 135Mpixel/s ........ 180 rotation time 15374us, 65fps, 135Mpixel/s ........ 270 rotation time 15373us, 65fps, 135Mpixel/s ........ g2d flip-h time 15373us, 65fps, 135Mpixel/s ........ g2d flip-v time 15372us, 65fps, 135Mpixel/s ........ ... After: $ /opt/fsl-samples/g2d/g2d_test Width 1920, Height 1088, Format RGBA, Bpp 32 ---------------- g2d blit performance ---------------- g2d blit time 2810us, 355fps, 743Mpixel/s ........ g2d blending time 4025us, 248fps, 518Mpixel/s ........ g2d blend-dim time 2740us, 364fps, 762Mpixel/s ........ ---------------- g2d clear performance ---------------- g2d clear time 1846us, 541fps, 1131Mpixel/s ........ ---------------- g2d rotation performance ---------------- 90 rotation time 5234us, 191fps, 399Mpixel/s ........ 180 rotation time 3176us, 314fps, 657Mpixel/s ........ 270 rotation time 5248us, 190fps, 398Mpixel/s ........ g2d flip-h time 2765us, 361fps, 755Mpixel/s ........ g2d flip-v time 3179us, 314fps, 657Mpixel/s ........ ... Signed-off-by: Robby Cai <r63905@freescale.com>
* MLK-11616 imx: mx6qpsabresd: Add defconfig filesPeng Fan2015-09-24-0/+14
| | | | | | Add android and sata defconfig file. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-11554 imx: mx6ulevk: Modify the mtest memory end to half of PHYS_SDRAM_SIZEYe.Li2015-09-16-1/+1
| | | | | | | Since the mx6ul 9x9 evk has different DDR size with 14x14 evk, change to use the half of PHYS_SDRAM_SIZE for mtest end. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-11551 imx: mx6qpsabresd: Update DDR initialization in pluginYe.Li2015-09-16-0/+180
| | | | | | The DDR initialization in plugin needs to update conformably with DCD. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-11553 imx: mx7 fix typo for showclocksPeng Fan2015-09-15-2/+2
| | | | | | | This piece of code is for mx7, we should not use do_mx6_showclocks. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-11549 imx: imx6ul: enlarge MMDC_MAPSR.PST to 16Anson Huang2015-09-15-1/+1
| | | | | | | | | MMDC auto power saving timer can NOT be too small, as enter/exit auto self-refresh mode too frequently may introduce too many latency for MMDC access, set it to 0x10, same as previous value on i.MX6. Signed-off-by: Anson Huang <b20788@freescale.com>
* MLK-11548 imx: imx6qp: add SabreSD board supportAnson Huang2015-09-15-1/+174
| | | | | | Add i.MX6QP SabreSD board support. Signed-off-by: Anson Huang <b20788@freescale.com>
* MLK-11528 imx: mx6ul check fuse before init beePeng Fan2015-09-10-1/+14
| | | | | | | | | | | Need to check fuse bit 25 of bank 0 word 4 before initialize bee. The bit: 0 means bee enabled, 1 means bee disabled. If disabled, continuing initialize bee will cause system hang, so need to check this bit before initialize bee. Add macro to enable BEE in header file, default disabled. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-11505 imx: mx6ul: Disable the LCDIF before system resetYe.Li2015-09-08-0/+9
| | | | | | | | | | We meet reset failure on mx6ul 9x9 evk. The internal reset logic between MMDC and functional modules seems relate with the issue. Turn off the LCDIF to stop DDR access before reset to avoid this possible internal reset problem. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-11486 imx: mx6ul 9x9 evk correct CS0_ENDPeng Fan2015-09-04-2/+2
| | | | | | | The lpddr2 memsize of mx6ul_9x9_evk is 256MB, not 512M, so the CS0_END should be 0x47, but not 0x4F. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-11490 ARM: imx: imx6ul: disable pfuze3000 low power modeAnson Huang2015-09-02-0/+5
| | | | | | | Disable PFuze3000 low power mode during standby mode, otherwise, if the power consumption exceed the threshold, PFuze will reboot. Signed-off-by: Anson Huang <b20788@freescale.com>
* MLK-11478 imx: mx6ul: Add QSPINOR boot support on mx6ul 9x9 evk boardYe.Li2015-09-01-0/+5
| | | | | | Add new build target: mx6ul_9x9_evk_qspi1_config Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-11427 imx: mx7d: Update DDR script for mx7d sabresd boardYe.Li2015-09-01-23/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Updated items: memory set 0x307a0000 32 0x03040001 --> memory set 0x307a0000 32 0x01040001 This is just enable when LPDDR4 is enabled . memory set 0x307a0064 32 0x0040005e --> memory set 0x307a0064 32 0x00400046 T_RFC_MIN this should be: RU(260ns*528Mhz)/2=69 (0x45) memory set 0x307a00d0 32 0x00020001 --> memory set 0x307a00d0 32 0x00020083 PRE_CKE_X1024 be (500us*528Mhz/2)/1024 = 129, or 0x81 memory set 0x307a00d4 32 0x00010000 --> memory set 0x307a00d4 32 0x00690000 DRAM_RSTN_X1024 (200us*528Mhz)/1024=104, or 0x68 memory set 0x307a00e4 32 0x00090004 --> memory set 0x307a00e4 32 0x00100004 DEV_ZQINIT_X32 . Should be 16 clocks memory set 0x307a0100 32 0x0908120a --> memory set 0x307a0100 32 0x09081109 T_FAW=(40ns*528Mhz)/2)=11 memory set 0x307a0104 32 0x0002020e --> memory set 0x307a0104 32 0x0007020d tXPDLL=24ns*528Mhz=13clocks File: MX7D_EVK_DDR3_1GB_32bit.ds Test result: 3 boards pass 2 days stress test. Signed-off-by: Ye.Li <B37916@freescale.com>
generated by cgit v1.1 at 2024-12-18 16:00:40 +0000