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| | * common: lcd.c: fix data abort exception when try to access bmp headerPrzemyslaw Marczak2014-02-03-14/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Changes: - le16_to_cpu() to get_unaligned_le16() - le32_to_cpu() to get_unaligned_le32() when access fields in struct bmp header. This changes avoids data abort exception caused by unaligned data access. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Acked-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * samsung: common: Add file for common functions, draw_logo() cleanup.Przemyslaw Marczak2014-02-03-29/+91
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Changes: new file: - board/samsung/common/misc.c depends on: CONFIG_MISC_COMMON - move draw_logo() to misc.c configs: trats, trats2, universal: - enable CONFIG_MISC_COMMON, - enable CONFIG_MISC_INIT_R, - add misc_init_r() and call draw_logo() in it. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * trats2: Code cleanup.Przemyslaw Marczak2014-02-03-11/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove wrong and unused env variables Trats2 is not as GT-I8800. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Cc: Piotr Wilczek <p.wilczek@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * s5p: gpio: change gpio coding method for s5p gpio.Przemyslaw Marczak2014-02-03-203/+132
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Old s5p gpio coding method was not clean and was not working properly for all parts and banks. New method is clean and easy to extend. Gpio coding mask: 0x000000ff - pin number 0x00ffff00 - bank offset 0xff000000 - part number Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * smdk5250: Remove 'board_usb_vbus_init()' functionVivek Gautam2014-02-03-19/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously as a part of moving the VBUS gpio support to device tree following patch removed this and added relevant support in driver: 4a271cb exynos: usb: Switch USB VBUS GPIOs to be device tree configured Recent changes for common board file migration for exynos platform added it again. So removing it now. Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> Cc: Julius Werner <jwerner@chromium.org> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Marek Vasut <marex@denx.de> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * exynos5250: usb: Fix VBus gpio numbers for ehci and xhci controllersVivek Gautam2014-02-03-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The gpio_*() apis require the exact gpio line number to deduce the gpio bank and the gpio pin addresses. So fix the gpio number for VBUS used for EHCI ports as well as XHCI ports on exynos5250 boards. Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> Cc: Julius Werner <jwerner@chromium.org> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Marek Vasut <marex@denx.de> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | ARM: tegra: fix "bootp" issue for Tegra124 tooJim Lin2014-02-03-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the timeout issue after running "bootp" command in U-Boot console. TXFIFOTHRES bits of TXFILLTUNING register should be set to 0x10 after a controller reset and before RUN bit is set (per technical reference manual). Signed-off-by: Jim Lin <jilin@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: add Venice2 (Tegra124) boardTom Warren2014-02-03-0/+672
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These are the board files for Venice2 (Tegra124), plus the AS3722 PMIC files. PMIC init will be moved to pmic_common_init later. This builds/boots on Venice2, SPI/MMC/USB/I2C all work. Audio, display and WB/LP0 are not supported yet. Signed-off-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: add DT files for Tegra124 and Venice2Tom Warren2014-02-03-0/+334
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These are fairly complete, and near-clones of Tegra114 Venice, with an additional I2C port, and MMC address changes for Tegra124. Signed-off-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: add common (shared) CPU filesTom Warren2014-02-03-12/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | These files are used by both SPL and main U-Boot. Signed-off-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: Add CPU (armv7) files for Tegra124Tom Warren2014-02-03-0/+1651
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These files are for code that runs on the CPU (A15) on Tegra124 boards. At this time, there is no A15-specific code here. The warmboot/LP0 files aren't included as that code hasn't been ported yet. Signed-off-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: add SPL/AVP (arm720t) CPU files for Tegra124Tom Warren2014-02-03-2/+318
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This provides SPL support for Tegra124 boards - AVP early init, plus CPU (A15) init/jump to main U-Boot. Signed-off-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: add/edit headers for Tegra124Tom Warren2014-02-03-28/+2419
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These headers define the Tegra124 hardware. Add them to the usual place. Add Tegra124 chip ID/SKU ID definitions to common headers. There's no real HW change on Tegra124 for 90% of the toys, so it might make sense for a future patch to unify some of the content of these files in a common location. Signed-off-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: fix a typo in the tegra114.dtsiStephen Warren2014-02-03-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | The reg property for node spi@7000d800 was wrong. Fix it to match the HW. This change was verified against the Linux kernel. Signed-off-by: Stephen Warren <swarren@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: only build __pinmux_nand() when it's neededTom Warren2014-02-03-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | __pinmux_nand() won't compile if PERIPH_ID_NDFLASH isn't defined. Prevent this from causing build problems on newer SoCs without NAND support (or without SW support for NAND yet), but preventing compilation unless the function will actually be used, i.e. when CONFIG_TEGRA_NAND is defined. Signed-off-by: Tom Warren <twarren@nvidia.com> [swarren, rewrote commit description, moved ifdef around whole function rather than just body] Signed-off-by: Stephen Warren <swarren@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: remove a conditional for CSITE rateStephen Warren2014-02-03-14/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There's already an SoC-specific conditional in cpu.h to determine the PLLP rate. Define the CSITE clock rate inside the same conditional, so that we can remove a conditional from clock_enable_coresight(). This means one less place to update the code for new SoCs. Signed-off-by: Stephen Warren <swarren@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: enable PLLX only once it's been fully configuredStephen Warren2014-02-03-4/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | This programming sequence is correct per Jimmy Zhang, and makes sense too! Signed-off-by: Stephen Warren <swarren@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: pass just partition ID to power_partition()Stephen Warren2014-02-03-18/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pass just the partition ID to power_partition(), rather than also passing the partition's status register mask too. This makes it simpler to get call-sites correct, since they don't need to pass two different values that define the same thing and must match. Consequently, we can remove the mask definitions from pmc.h. Suggested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: misc cleanups triggered by Tegra124 reviewStephen Warren2014-02-03-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use a named constant for the PLL lock bit in enable_cpu_clocks(). Construct the complete value of pmc_pwrgate_toggle, rather than doing a read-modify-write; the register is simple enough and doesn't need to maintain state between operations. Signed-off-by: Stephen Warren <swarren@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | mmc: tegra: support Tegra124Stephen Warren2014-02-03-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra124's MMC controller is very similar to earlier SoC generations, and can be supported by the same driver. However, there are some non-backwards-compatible HW differences, and hence a new DT compatible value must be used to describe the HW. This patch updates the driver to support that new compatible value. That said, the HW differences are only relevant when enabling certain high-performance transfer modes. Since the driver is currently very simple and doesn't enable those modes, we don't actually need to address any of these HW differences in the code yet, hence the simple nature of this patch. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: don't exceed AVP limits when configuring PLLPJimmy Zhang2014-02-03-87/+118
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on the Tegra TRM, the system clock (which is the AVP clock) can run up to 275MHz. On power on, the default sytem clock source is set to PLLP_OUT0. In function clock_early_init(), PLLP_OUT0 will be set to 408MHz which is beyond system clock's upper limit. The fix is to set the system clock to CLK_M before initializing PLLP, and then switch back to PLLP_OUT4, which has an appropriate divider configured, after PLLP has been configured Implement this logic in new function tegra30_set_up_pllp(), which sets up PLLP and all PLLP_OUT* dividers, and handles the AVP clock switching. Remove the duplicate PLLP setup from pllx_set_rate() and adjust_pllp_out_freqs(). Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> [swarren, significantly refactored the change] Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: amend pmc.h for Tegra114+Stephen Warren2014-02-03-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra114 and later's PMC module removes the pwrgate_timer_on register and replaces it with a clamp_status register. Adjust pmc.h to reflect this, and update any code affected by the change. The cpu.c change in this patch was extracted from a much larger patch by Jimmy Zhang. The pmc.h change was written from scratch, but inspired by related changes made by Tom Warren. There could well be other differences in the PMC register set for chips after Tegra20/30. However, they don't affect the code in U-Boot at present, so I haven't attempted an exhaustive update of pmc.h. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: implement MASK_BITS_31_29Tom Warren2014-02-03-4/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some clock sources have 3-bit muxes in bits 31:29. Implement core support for this mux field. Signed-off-by: Tom Warren <twarren@nvidia.com> [swarren, extracted from a larger patch by Tom] Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: MASK_BITS_ no longer needs specific valuesStephen Warren2014-02-03-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since all code that sets or interprets MASK_BITS_* now uses the enums to define/compare the values, there is no need for MASK_BITS_* to have a specific integer value. In fact, having a specific integer value may encourage people to hard-code those values, or interpret the values in incorrect ways. As such, remove the logic that assigns a specific value to the enum values in order to make it completely clear that it's just an enum, not something that directly represents some integer value. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: use MASK_BITS_* macros everywhereStephen Warren2014-02-03-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Not all code that set or interpreted "mux_bits" was using the named macros, but rather some was simply using hard-coded integer constants. This makes it hard to determine which pieces of code are affected by changes to those constants. Replace the integer constants with the equivalent macro definitions so that everything is nicely tied together. Note that I'm not convinced all the code was using the correct integer constants, and hence I'm not convinced that all the code is now using the desired macros. However, this change is a purely mechanical replacement and should have no functional change. Fixing any bugs will come later, separately. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: rename OUT_CLK_SOURCE_*Stephen Warren2014-02-03-12/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | OUT_CLK_SOURCE_ are currently named after the number of bits the mask they represent includes. However, bit count is not the only possible variable; bit position may also vary. Rename OUT_CLK_SOURCE_ to OUT_CLK_SOURCE_31_30_ and OUT_CLK_SOURCE4_ to OUT_CLK_SOURCE_31_28 to more completely describe exactly what they represent, without having to go look up the definitions. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: rename MASK_BITS_29_28 to MASK_BITS_31_28Stephen Warren2014-02-03-3/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The only place where the MASK_BITS_* values are used is in adjust_periph_pll(), which interprets the value 4 (old MASK_BITS_29_28, new MASK_BITS_31_28) as being associated with mask OUT_CLK_SOURCE4_MASK, i.e. bits 31:28. Rename the MASK_BITS_ macro to reflect how it's actually implemented. Note that no Tegra clock register actually uses all of bits 31:28 as the mux field. Rather, bits 30:28, 29:28, or 28 are used. However, in those cases, nothing is stored in the bits above the mux field, so it's safe to pretend that the mux field extends all the way to the end of the register. As such, the U-Boot clock driver is currently a bit lazy, and doesn't distinguish between 31:28, 30:28, 29:28 and 28; it just lumps them all together and pretends they're all 31:28. This patch doesn't cause this issue; it was pre-existing. Hopefully, future patches will clean this up. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: deduplicate MASK_BITS_xxx clock mux enumTom Warren2014-02-03-12/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The enum used to define the set of register bits used to represent a clock's input mux, MUX_BITS_*, is defined separately for each SoC at present. Move this definition to a common location to ease fixing up some issues with the definition, and the code that uses it. Signed-off-by: Tom Warren <twarren@nvidia.com> [swarren, extracted from a larger patch by Tom] Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: clear $usb_need_init each bootStephen Warren2014-02-03-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | $usb_need_init prevents "usb start" from being run multiple times for each boot attempt, i.e. once for USB storage, another for PXE, and another for DHCP. However, the flag that's used to determine when to run "usb start" is never cleared, so a subsequent "boot" command will never probe for a freshly plugged in USB device. Fix this so that new USB devices will be probed once per boot attempt. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: set env vars to indicate Cardhu A04 supportStephen Warren2014-02-03-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The U-Boot "cardhu" build supports only revision 4 of the Cardhu board and later compatible revisions. Hence, set $board_name in the default environment to "cardhu-a04" rather than just "cardhu". The Linux kernel has separate DTs for Cardhu A02 and A04, although the former isn't really supported any more. Consequently, the kernel DT file that matches the U-Boot cardhu build is "tegra30-cardhu-a04.dtb" rather than "tegra30-cardhu.dtb". Set the $fdtfile default environment variable to reflect this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: accept any SKU ID for most chipsStephen Warren2014-02-03-0/+2
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For Tegra20, the SKU ID actually impacts how U-Boot programs the chip, and hence we need to explicitly know about each and every SKU ID in order to operate correctly. However, for Tegra30/114, this isn't the case. Rather than forcing each new user with a different SKU to manually add their SKU ID into the code, simply accept any SKU ID. If U-Boot ever starts e.g. programming maximal CPU clocks etc., we'll need to undo this, or make the default case map to conservative defaults, but for now it's likely the path to least support cost. Reported-by: Olof Johansson <olof@lixom.net> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'Albert ARIBAUD2014-01-29-1144/+157
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| | * am43xx_evm.h: Correct SPL max sizeTom Rini2014-01-24-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Upon further inspection of relevant parts of the architecture, the maximum SPL binary size is 220KiB. Cc: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tom Rini <trini@ti.com>
| | * DRA7: add ABB setup for MPU voltage domainNishanth Menon2014-01-24-3/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | Patch adds modification to shared omap5 abb_setup() function, and proper registers definitions needed for ABB setup sequence. ABB is initialized for MPU voltage domain at OPP_NOM. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
| | * DRA7: Add support for ES1.1 silicon ID codeNishanth Menon2014-01-24-3/+13
| | | | | | | | | | | | | | | | | | | | | | | | ES1.1 silicon is a very minor variant of ES1.0. Add priliminary support for ES1.1 IDCODE change. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
| | * ARM: AM335x: Enable DDR dynamic IO power downSatyanarayana, Sandhya2014-01-24-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch enables dynamically powering down the IO receiver when not performing a read on boards using DDR3. This optimizes both active and standby power consumption. This bit is not set on EVM SK and EVM 1.5 and later boards. Setting the same. This has been tested on PG2.0 EVM1.5, EVM1.2, EVM-SK, BBB. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Satyanarayana, Sandhya <sandhya.satyanarayana@ti.com>
| | * ARM: AM43xx: Enable DDR dynamic IO power down for DDR3Lokesh Vutla2014-01-24-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch enables dynamically powering down the IO receiver when not performing a read on DDR3 board. This optimizes both active and standby power consumption. This is derived from a patch that is done on AM335x[1] [1] http://arago-project.org/git/projects/?p=u-boot-am33x.git;a=commit;h=6a9ee4bc72ece53fabf01825605fba3d71d5feb2 Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| | * OMAP3: igep00x0: Convert to ti_omap3_common.h.Enric Balletbò i Serra2014-01-24-180/+9
| | | | | | | | | | | | | | | | | | To reduce code duplication update omap3_igep00x0.h to use ti_omap3_common.h. Signed-off-by: Enric Balletbo i Serra <eballetbo@gmail.com>
| | * TI: OMAP3: Create common config files for TI OMAP3 platforms.Enric Balletbò i Serra2014-01-24-0/+73
| | | | | | | | | | | | | | | | | | | | | | | | Create a new file, include/configs/ti_omap3_common.h, for everything common to the OMAP3 SoC leaving just the board specific part to board configuration file. Signed-off-by: Enric Balletbo i Serra <eballetbo@gmail.com>
| | * ARM: OMAP3: Rename OMAP3_PUBLIC_SRAM_* to NON_SECURE_SRAM_*Enric Balletbò i Serra2014-01-24-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Other TI processors like am33xx, omap4 and omap5 have called these variables as NON_SECURE_SRAM_*, shouldn't be a big problem rename these variables to be coherent. One reason more to rename these variables is to have the possibility of any OMAP3 board to use the ti_armv7_common.h include as the NON_SECURE_SRAM_END is used to define the CONFIG_SYS_INIT_SP_ADDR variable. Signed-off-by: Enric Balletbo i Serra <eballetbo@gmail.com>
| | * TI: armv7: Do not define the number DRAM banks if is already defined.Enric Balletbò i Serra2014-01-24-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If CONFIG_NR_DRAM_BANKS is not defined, we say (for simplicity) that we have 1 bank, but for some boards should be interesting that we can define CONFIG_NR_DRAM_BANKS. To handle this possibility just define the number of DRAM banks if is not already defined. This is useful for some OMAP3 boards where the DRAM initialitzation is only at u-boot level. Signed-off-by: Enric Balletbo i Serra <eballetbo@gmail.com>
| | * TI: armv7: Move ELM support to SoC configuration file.Enric Balletbò i Serra2014-01-24-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | The ELM hardware engine wihich is used for ECC error detections is not present on OMAP3 SoC, so move the CONFIG_SPL_NAND_AM33XX_BCH from ti_armv7_common.h to SoC configuration file. Signed-off-by: Enric Balletbo i Serra <eballetbo@gmail.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
| | * ARM: OMAP5: Rename to ti_omap5_common.hEnric Balletbò i Serra2014-01-24-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | Follow the pattern ti_<processor family>_common.h used by other TI processors to be coherent. So just rename omap5_common.h to ti_omap5_common.h. Signed-off-by: Enric Balletbo i Serra <eballetbo@gmail.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
| | * ARM: OMAP4: Rename to ti_omap4_common.hEnric Balletbò i Serra2014-01-24-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | Follow the pattern ti_<processor family>_common.h used by other TI processors to be coherent. So just rename omap4_common.h to ti_omap4_common.h. Signed-off-by: Enric Balletbo i Serra <eballetbo@gmail.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
| | * feature-removal-schedule.txt: Drop CONFIG_SYS_ENABLE_PADS_ALL/CLOCKS_ENABLE_ALLTom Rini2014-01-24-16/+0
| | | | | | | | | | | | Signed-off-by: Tom Rini <trini@ti.com>
| | * ARM: OMAP4/5: Remove dead code against CONFIG_SYS_ENABLE_PADS_ALLJassi Brar2014-01-24-688/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | The commit f3f98bb0 : "ARM: OMAP4/5: Do not configure non essential pads, clocks, dplls" removed the config option aimed towards moving that stuff into kernel, which renders some code unreachable. Remove that code. Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
| | * ARM: OMAP4/5: Remove dead code against CONFIG_SYS_CLOCKS_ENABLE_ALLJassi Brar2014-01-24-227/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | The commit f3f98bb0 : "ARM: OMAP4/5: Do not configure non essential pads, clocks, dplls" removed the config option aimed towards moving that stuff into kernel, which renders some code unreachable. Remove that code. Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
| * | Merge branch 'u-boot-arm/next' into 'u-boot-arm/master'Albert ARIBAUD2014-01-28-1/+6
| |\ \
| | * | ARM: versatile: pass console setting to the kernelLinus Walleij2014-01-13-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Versatiles come up with the primary UART set to ttyAMA0 at 38400 baud, and unless we pass this to the kernel it will assume it is set to 9600 baud which will be quite awkward for the terminal, let's try to be helpful and inform the kernel what setting is used. Cc: Stefano Babic <sbabic@denx.de> Cc: Marek Vasut <marex@denx.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| | * | ARM: versatile: pass correct machine type for Versatile ABLinus Walleij2014-01-13-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When U-Boot is configured for Versatile AB, it will still pass the machine ID of Versatile PB to the kernel. After this simple fix the system boots correctly. Cc: Stefano Babic <sbabic@denx.de> Cc: Marek Vasut <marex@denx.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
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