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* image: Use fit_image_load() to load FDTSimon Glass2013-06-04-202/+34
| | | | | | | | Use the new common code to load a flat device tree. Also fix up a few casts so that this code works with sandbox. Other than that the functionality should not change. Signed-off-by: Simon Glass <sjg@chromium.org>
* image: Use fit_image_load() to load ramdiskSimon Glass2013-06-04-169/+16
| | | | | | | Use the new common code to load a ramdisk. The functionality should not change. Signed-off-by: Simon Glass <sjg@chromium.org>
* image: Introduce fit_image_load() to load images from FITsSimon Glass2013-06-04-2/+326
| | | | | | | | | | | At present code to load an image from a FIT is duplicated in the three places where it is needed (kernel, fdt, ramdisk). The differences between these different code copies is fairly minor. Create a new function in the fit code which can handle any of the requirements of those cases. Signed-off-by: Simon Glass <sjg@chromium.org>
* mkimage: Add map_sysmem() and IH_ARCH_DEFAULT to simplfy buildingSimon Glass2013-06-04-0/+12
| | | | | | | | | | | | | These are not actually used in mkimage itself, but the image code (which is common with mkimage) does use them. To avoid #ifdefs in the image code just for mkimage, define dummy version of these here. The compiler will eliminate the dead code anyway. A better way to handle this might be to split out more things from common.h so that mkimage can include them. At present any file that mkimage uses has to be very careful what headers it includes. Signed-off-by: Simon Glass <sjg@chromium.org>
* bootstage: Introduce sub-IDs for use with image loadingSimon Glass2013-06-04-0/+22
| | | | | | | | Loading a ramdisk, kernel or FDT goes through similar stages. Create a block of IDs for each task, and define a consistent numbering within the block. This will allow use of common code for image loading. Signed-off-by: Simon Glass <sjg@chromium.org>
* main: Add debug_bootkeys to avoid #ifdefsSimon Glass2013-06-04-12/+12
| | | | | | | | Define a simple debug condition at the top of the file, to avoid using lots of #ifdefs later on. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
* main: Add debug_parser() to avoid #ifdefsSimon Glass2013-06-04-35/+23
| | | | | | | | Define a simple debug condition at the top of the file, to avoid using lots of #ifdefs later on. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
* main: Correct header orderSimon Glass2013-06-04-15/+4
| | | | | | The headers are a bit out of order, so fix them. Signed-off-by: Simon Glass <sjg@chromium.org>
* main: Fix typos and checkpatch warnings in command line readingSimon Glass2013-06-04-11/+11
| | | | | | | | There are a few over-long lines and other checkpatch problems in this area of the code. Prepare the ground for the next patch by tidying these up. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
* main: Use get/setenv_ulong()Simon Glass2013-06-04-6/+2
| | | | | | | These functions are now available, so use them to avoid extra code here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
* main: Move boot_delay code into its own functionSimon Glass2013-06-04-67/+70
| | | | | | Move this code into its own function, since it clutters up main_loop(). Signed-off-by: Simon Glass <sjg@chromium.org>
* main: Separate out the two abortboot() functionsSimon Glass2013-06-04-11/+11
| | | | | | | | | | | | | There are two implementations of abortboot(). Turn these into two separate functions, and create a single abortboot() which calls either one or the other. Also it seems that nothing uses abortboot() outside main, so make it static. At this point there is no further use of CONFIG_MENU in main.c. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
* net: Add prototype for update_tftpSimon Glass2013-06-04-6/+4
| | | | | | | This function should be declared in net.h. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
* at91: Correct CONFIG_AUTOBOOT_PROMPT definition for pm9263Simon Glass2013-06-04-1/+1
| | | | | | | | This is not currently used, since autoboot is not enabled for this board, but the string is missing a parameter. Add it. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
* Merge branch 'master' of git://git.denx.de/u-boot-nand-flashTom Rini2013-05-31-1731/+2307
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| * mtd: resync with Linux-3.7.1Sergey Lapin2013-05-31-1706/+2208
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is essentially an update of u-boot MTD subsystem to the state of Linux-3.7.1 with exclusion of some bits: - the update is concentrated on NAND, no onenand or CFI/NOR/SPI flashes interfaces are updated EXCEPT for API changes. - new large NAND chips support is there, though some updates have got in Linux-3.8.-rc1, (which will follow on top of this patch). To produce this update I used tag v3.7.1 of linux-stable repository. The update was made using application of relevant patches, with changes relevant to U-Boot-only stuff sticked together to keep bisectability. Then all changes were grouped together to this patch. Signed-off-by: Sergey Lapin <slapin@ossfans.org> [scottwood@freescale.com: some eccstrength and build fixes] Signed-off-by: Scott Wood <scottwood@freescale.com>
| * nand/fsl_ifc: Convert to self-initPrabhakar Kushwaha2013-05-22-6/+39
| | | | | | | | | | | | Convert NAND IFC driver to support CONFIG_SYS_NAND_SELF_INIT. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
| * mtd: nand: use ssize_t instead of size_t to prevent infinite loophtbegin2013-05-22-1/+2
| | | | | | | | | | | | | | | | | | | | | | When a all 0xFF buffer is passed to drop_ffs, the no-0xFF check loop will loop forever. After the fix, If ssize_t i = -1 and size_t l = i + 1, the value of l will still be 0 as expected. Signed-off-by: Tao Hou <hotforest@gmail.com> Cc: Ben Gardiner <bengardiner@nanometrics.ca> Cc: Scott Wood <scottwood@freescale.com>
| * mtd: nand: fix the partial page write conditionhtbegin2013-05-22-1/+1
| | | | | | | | | | | | | | When writelen is mtd->writesize - 1, it is still a partial page write Signed-off-by: Tao Hou <hotforest@gmail.com> Cc: Scott Wood <scottwood@freescale.com>
| * nand: adjust erase/read/write partition/chip size for bad blocksHarvey Chapman2013-05-22-0/+35
| | | | | | | | | | | | | | | | Adjust the sizes calculated for whole partition/chip operations by removing the size of bad blocks so we don't try to erase/read/write past a partition/chip boundary. Signed-off-by: Harvey Chapman <hchapman@3gfp.com>
| * nand/fsl_elbc: detect page size at runtimeScott Wood2013-05-22-17/+22
| | | | | | | | | | | | | | | | | | | | | | This avoids needing a separate U-Boot config when some revisions of a board have small-page NAND and other revisions have large-page NAND (except for NAND SPL targets). CONFIG_FSL_ELBC_FMR is removed -- it was never used nor documented, and it gets in the way of this change. Signed-off-by: Scott Wood <scottwood@freescale.com>
* | arm: factorize relocate_code routineAlbert ARIBAUD2013-05-30-992/+124
| | | | | | | | | | | | | | | | | | | | | | Replace all relocate_code routines from ARM start.S files with a single instance in file arch/arm/lib/relocate.S. For PXA, this requires moving the dcache unlocking code from within relocate_code into c_runtime_cpu_setup. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Tested-by: Simon Glass <sjg@chromium.org>
* | arm: do not compile relocate_code() for SPL buildsAlbert ARIBAUD2013-05-30-81/+55
| | | | | | | | | | | | Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Tested-by: Simon Glass <sjg@chromium.org>
* | tx25: copy SPL directly, not using relocate_code.Albert ARIBAUD2013-05-30-1/+15
| | | | | | | | | | | | Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Tested-by: Simon Glass <sjg@chromium.org>
* | mx31pdk: copy SPL directly, not using relocate_code.Albert ARIBAUD2013-05-30-1/+15
| | | | | | | | | | | | Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Tested-by: Simon Glass <sjg@chromium.org>
* | Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2013-05-30-15424/+8271
|\ \ | | | | | | | | | | | | | | | Conflicts: common/cmd_fpga.c drivers/usb/host/ohci-at91.c
| * | powerpc/mpc85xx: Clear L1 D-cache lockYork Sun2013-05-24-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | dcbi instruction has been used to clear D-cache lock. However, the cache lock is persistent for e6500 core. Use dcblc to clear the lock explicitly. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | SECURE BOOT - Removed deletion of TLB entries codeRuchika Gupta2013-05-24-17/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Boot ROM code creates TLB entries for 3.5G space before entering the u-boot. Earlier we were deleting these entries after early initialization of CPU. In recent past, code has been added to invalidate all these entries before relocation of u-boot code. So this code to delete TLB entries after CPU initialization is no longer required. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Acked-by: Matthew McClintock <msm@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | powerpc/b4860qds: Add LAW Target ID and Create LAW entry for MapleShaveta Leekha2013-05-24-0/+14
| | | | | | | | | | | | | | | Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | powerpc/p5040: fix mdio mux for 10G portShaohui Xie2013-05-24-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current driver of p5040 assumes 10G port follows 1G port DTSEC5 in eth port enum structure, it will assign mdio mux depend on this assumption. This is not true with Fman V3, which added more 1G ports after port DTSEC5 in eth port enum structure, then 10G ports on p5040 will have wrong mdio mux. So we use dynamic index for 10G ports instead of hardcoded enum value when doing mdio mux for 10G ports. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | powerpc/B4: Merge B4420 and B4860 in config_mpc85xx.hPoonam Aggrwal2013-05-24-24/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | B4420 is a subset of B4860. Merge them in config_mpc85xx.h to simplify the defines. - Removed #define CONFIG_SYS_FSL_NUM_CLUSTERS as this is used nowhere. - defined CONFIG_SYS_NUM_FM1_10GEC to 0 for B4420 as it does not have 10G. Also move CONFIG_E6500 out of B4860QDSds.h into config_mpc85xx.h. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | sf: spansion: Add support for S25FL128SXie Xiaobo2013-05-24-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | SPANSION recommend S25FL128S supersedes S25FL129P, and the two flash memory have the same device ID and Memory architecture. So they can use the same config parameters. Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | powerpc/p2041: fix serdes reference clock frequency display for PC boardShaohui Xie2013-05-24-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PC board has different serdes clock setting with PB board, it uses same serdes frequency setting on bank2 as on bank1. PC board can be distingushed from PB board by checking CPLD version, if running on PC board, then fix the serdes reference clock frequency of bank2. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | powerpc/b4860: fix for Serdes connectivity to SFP'sShaveta Leekha2013-05-24-12/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Crossbar switches were wrongly programmed to route the CPRI lanes to SFP as the connectivity table was not correct. Modified it correctly for SFPs connections. Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | powerpc/t4240qds: fix PHY reset timeout issueShengzhou Liu2013-05-24-2/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | QSGMII card has different PHY address against previous SGMII card. We check the type of card in slots and set correct PHY address to avoid complainning "PHY reset timed out" during u-boot booting up. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | powerpc/t4qds: Add SW7[4] in the DIP switch displayYork Sun2013-05-24-2/+3
| | | | | | | | | | | | | | | | | | | | | SW7[4] is the new bit which controls the mapping of eMMC vs SDHC. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | Enable XAUI interface for B4860QDSSuresh Gupta2013-05-24-3/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Added SERDES2 PRTCLs = 0x98, 0x9E - Default Phy Addresses for Teranetics PHY on XAUI card The PHY addresses of Teranetics PHY on XAUI riser card are assigned based on the slot it is in. Switches SW4[2:4] and SW6[2:4] on AMC2PEX-2S On B4860QDS, AMC2PEX card decide the PHY addresses on slot1 and slot2 - Configure MDIO for 10Gig Mac Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | board/t4240qds, b4860qds: LAW/TLB for DCSR set to size 32MStephen George2013-05-24-7/+9
| | | | | | | | | | | | | | | | | | | | | Debug trace buffers are memory mapped in DCSR space beyond 4M. Signed-off-by: Stephen George <stephen.george@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | powerpc/p5040: enable PBL tool supportShaohui Xie2013-05-24-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | Provided a default RCW for P5040, then it can use PBL to build ramboot image. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | powerpc/t4qds: use clock measurement for sysclk and ddr clockEd Swarthout2013-05-24-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use QIXIS measurement registers to obtain sysclk and ddr clock. This allows using non-standard clock speeds, set by directly writing to clock chip or store the values in qixis clock data eeprom. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | powerpc/qixis: add clock measurement registersEd Swarthout2013-05-24-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | QIXIS includes frequency measurement functions for each major processor clock input. After reset (and after clocks are stable), QIXIS measures the clocks against a reference frequency and stores the results in CLK_FREQ registers. A base register supplies a multiplier which allows directly obtaining the measured value, without requiring knowledge of the target system or QIXIS core frequency. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | powerpc/mpc8xxx: Allow DDR overclockYork Sun2013-05-24-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allow DDR clock runs faster than SPD specifes. This may cause memory failure, but the user should know what is going to happen when using higher than expected DDR clock. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | powerpc/chassis2: Change core numbering schemeYork Sun2013-05-24-58/+92
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To align with chassis generation 2 spec, all cores are numbered in sequence. The cores may reside across multiple clusters. Each cluster has zero to four cores. The first available core is numbered as core 0. The second available core is numbered as core 1 and so on. Core clocks are generated by each clusters. To identify the cluster of each core, topology registers are examined. Cluster clock registers are reorganized to be easily indexed. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | powerpc/mpc8xxx: Add T1040 and variant SoCsYork Sun2013-05-24-0/+282
| | | | | | | | | | | | | | | | | | | | | | | | | | | T1040 and variants have e5500 cores and are compliant to QorIQ Chassis Generation 2. The major difference between T1040 and its variants is the number of cores and the number of L2 switch ports. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | powerpc/T4160: Merge T4160 and T4240 in config_mpc85xx.hYork Sun2013-05-24-33/+10
| | | | | | | | | | | | | | | | | | | | | | | | T4160 is a subset of T4240. Merge them in config_mpc85xx.h to simplify the defines. Also move CONFIG_E6500 out of t4qds.h into config_mpc85xx.h. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | powerpc/p5040: enable NAND, SD, SPI boot supportShaohui Xie2013-05-24-0/+3
| | | | | | | | | | | | | | | Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | Add e6500 L2 replacement policy selectionJames Yang2013-05-24-1/+11
| | | | | | | | | | | | | | | | | | | | | This is compile-time config. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | T4240/ramboot: enable PBL tool for T4240Shaohui Xie2013-05-24-0/+45
| | | | | | | | | | | | | | | | | | | | | | | | Added a default RCW(1_28_6_12) and PBI configure file for T4240, so it can use PBL tool to produce the ramboot image. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | powerpc/t4240qds: Add VDD overrideYork Sun2013-05-24-2/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allow VDD voltage overriding with a command. This is an add-on feasture of VID. To override VDD, use command vdd_override with the value of voltage in mV, for example vdd_override <voltage in mV, eg. 1050> The above example will set the VDD to 1.050 volt. Any wrong value out of range of 0.8188 to 1.2125 volt or invalid string is ignored. In addition to the command, if overriding VDD is needed earlier in booting process, save an variable and reboot: setenv t4240qds_vdd_mv <voltage in mV> saveenv Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | powerpc/mpc85xx: check if core is disabled for showing statusYork Sun2013-05-24-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | "cpu <num> status" should check if core is disabled before printing the spin table location. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
generated by cgit v1.1 at 2024-11-09 15:07:38 +0000