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| * fsl/usb: Increase TXFIFOTHRESH value for usb write in T4 Rev 2.0Nikhil Badola2014-04-22-0/+27
| | | | | | | | | | | | | | | | | | | | | | Increase TXFIFOTHRES field value in TXFILLTUNING register of usb for T4 Rev 2.0. This decreases data burst rate with which data packets are posted from the TX latency FIFO to compensate for latencies in DDR pipeline during DMA. This avoids Tx buffer underruns and leads to successful usb writes Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * board/t104xrdb: Add support of CPLDPrabhakar Kushwaha2014-04-22-0/+174
| | | | | | | | | | | | | | | | | | | | | | T1040RDB and T1042RDB_PI has CPLD. Here CPLD controls board mux/features. This support of CPLD includes - files and register defintion - Commands to swtich alternate bank and default bank Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * powerpc/cpu/mpc85xx: Add MAC address for layer 2 switchCodrin Ciubotariu2014-04-22-0/+29
| | | | | | | | | | | | | | | | | | | | | | T1040RDB and T1040QDS boards have an integrated l2 switch. The switch needs a MAC address for Layer 2 protocols (MSTP, LLDP, LACP, etc). Setting a MAC address on l2switchaddr will add a MAC in device-tree, under node l2switch. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Cc: York Sun <yorksun@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * powerpc/T1040: add mtdparts suppport for T104xRDB and T1040QDSPrabhakar Kushwaha2014-04-22-0/+34
| | | | | | | | | | | | | | | | We use dynamical mtdparts partition instead of directly puting mtd partitions nodes in device tree. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * powerpc/T208xRDB: add mtdparts suppportShengzhou Liu2014-04-22-0/+16
| | | | | | | | | | | | | | | | We use dynamical mtdparts partition instead of directly puting mtd partitions nodes in device tree. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * powerpc/T208xQDS: add mtdparts suppportShengzhou Liu2014-04-22-0/+17
| | | | | | | | | | | | | | | | We use dynamical mtdparts partition instead of directly puting mtd partitions nodes in device tree. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * powerpc/t104xrdb: Unification of T104xRDB header filesvijay rai2014-04-22-722/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | T1040RDB, T1042RDB header files are very similar so merged into new header file T104xRDB. T104xRDB header file can support both T1040RDB and T1042RDB_PI header. Patch makes following changes -Update Boards.cfg file for T1040RDB and T1042RDB_PI -Add new T104xRDB header file -Delete T1040RDB, T1042RDB_PI header file Signed-off-by: Vijay Rai <vijay.rai@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * driver/mmc: fix compile warningsPrabhakar Kushwaha2014-04-22-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix following compile warnings fsl_esdhc_spl.c: In function 'mmc_boot': fsl_esdhc_spl.c:35:10: warning: unused variable 'byte_num' [-Wunused-variable] fsl_esdhc_spl.c:35:7: warning: unused variable 'i' [-Wunused-variable] fsl_esdhc_spl.c:34:8: warning: unused variable 'val' [-Wunused-variable] fsl_esdhc_spl.c:33:6: warning: unused variable 'blklen' [-Wunused-variable] fsl_esdhc_spl.c:105:7: warning: 'tmp_buf' may be used uninitialized in this function [-Wuninitialized] Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * powerpc/mpc85xx: Add workaround for erratum A007212York Sun2014-04-22-0/+99
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Erratum A007212 for DDR is about a runaway condition for DDR PLL oscilliator. Please refer to erratum document for detail. For this workaround to work, DDR PLL needs to be disabled in RCW. However, u-boot needs to know the expected PLL ratio. We put the ratio in a reserved field RCW[18:23]. U-boot will skip this workaround if DDR PLL ratio is set, or the reserved field is not set. Workaround for erratum A007212 applies to selected versions of B4/T4 SoCs. It is safe to apply the workaround to all versions. It is helpful for upgrading SoC without changing u-boot. In case DDR PLL is disabled by RCW (part of the erratum workaround), we need this u-boot workround to bring up DDR clock. Signed-off-by: York Sun <yorksun@freescale.com>
| * powerpc/t208xqds: fix nor chip selection when nand bootShengzhou Liu2014-04-22-10/+18
| | | | | | | | | | | | | | | | NOR flash is on CS1 instead of CS2 when NAND boot. So correct NOR chip selection to CS1 from CS2. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * fsl/usb: Workaround for USB erratum-A007075Nikhil Badola2014-04-22-0/+33
| | | | | | | | | | | | | | | | | | | | | | | | Put a delay of 5 millisecond after reset so that ULPI phy gets enough time to come out of reset. Erratum A007075 applies to following SOCs and their variants, if any P1010 rev 1.0 B4860 rev 1.0, 2.0 P4080 rev 2.0, 3.0 Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * mpc85xx/T1040QDS_D4: Add DDR4 supportYork Sun2014-04-22-28/+31
| | | | | | | | | | | | | | T1040QDS_D4 is a variant of T1040QDS, with additional circuit to support DDR4 memory. Tested with MTA9ASF51272AZ-2G1AYESZG. Signed-off-by: York Sun <yorksun@freescale.com>
| * driver/ddr/fsl: Add DDR4 support to Freescale DDR driverYork Sun2014-04-22-321/+2378
| | | | | | | | | | | | | | Mostly reusing DDR3 driver, this patch adds DDR4 SPD handling, register calculation and programming. Signed-off-by: York Sun <yorksun@freescale.com>
| * powerpc/85xx: Fix e6500 L2 cache stash IDsScott Wood2014-04-22-4/+8
| | | | | | | | | | | | | | | | The value written to L2CSR1 didn't match the value written to the device tree. Signed-off-by: Scott Wood <scottwood@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * net/phy: Fix PHY id for VSC8514Codrin Ciubotariu2014-04-22-1/+1
| | | | | | | | | | | | | | | | | | | | In the current Datasheet for VSC8514 there is a mistake, saying that the PHY id is 0x70570. The real value in the identifier registers is 0x70670. Linux PHY driver uses 0x70670 also. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Cc: York Sun <yorksun@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * driver/fsl_ifc: Add a function to finalize CS0 address bindingYork Sun2014-04-22-0/+8
| | | | | | | | | | | | | | | | | | For fsl-lsch3 NOR flash boot, IFC CS0 needs to be binded with address within 32-bit at fist. After u-boot relocates to DDR, CS0 can be binded to higher address to support large space. Signed-off-by: York Sun <yorksun@freescale.com> CC: Prabhakar Kushwaha <prabhakar@freescale.com>
| * board/b4860qds:Slow MDC clock to comply IEEE specs in PBI configPrabhakar Kushwaha2014-04-22-0/+3
| | | | | | | | | | | | | | | | | | | | The MDC generate by default value of MDIO_CLK_DIV is too high i.e. higher than 2.5 MHZ. It violates the IEEE specs. So Slow MDC clock to comply IEEE specs Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * t1040rdb/qe: add QE support for T1040RDBZhao Qiang2014-04-22-0/+4
| | | | | | | | | | | | | | | | add CONFIG_QE, CONFIG_U_QE and CONFIG_SYS_QE_FW_ADDR into "include/configs/T1040RDB.h" Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * QE/U-QE: Add U-QE supportZhao Qiang2014-04-22-5/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | Modify code to adapt to both u-qe and qe. U_QE is a kind of cutted QE. the differences between U_QE and QE 1. UCC: U_QE supports 2 UCCs while QE supports up to 8 UCCs. 2. IMMR: have different immr base addr. 3. iopin: U_QE doesn't need to config iopin. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * QE/FMAN: modify CONFIG_SYS_QE_FMAN_FW_ADDR to CONFIG_SYS_FMAN_FW_ADDR and ↵Zhao Qiang2014-04-22-61/+66
| | | | | | | | | | | | | | | | | | | | | | CONFIG_SYS_QE_FW_ADDR CONFIG_SYS_QE_FMAN_FW_ADDR is used to both Fman and QE for microcode address. Now using CONFIG_SYS_FMAN_FW_ADDR for Fman microcode address, and CONFIG_SYS_QE_FW_ADDR for QE microcode address. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T1040QDS and T1040RDBAneesh Bansal2014-04-22-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | Secure Boot Target is added for T1040QDS and T1040RDB Changes: For Secure boot, CPC is configured as SRAM and used as house keeping area which needs to be disabled. So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T1040QDS and CONFIG_T1040RDB Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T2080QDSAneesh Bansal2014-04-22-1/+4
| | | | | | | | | | | | | | | | | | | | | | Secure Boot Target is added for T2080QDS Changes: For Secure boot, CPC is configured as SRAM and used as house keeping area which needs to be disabled. So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T2080QDS. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T4240QDS and T4160QDSAneesh Bansal2014-04-22-1/+3
| | | | | | | | | | | | | | | | | | | | | | Secure Boot Target is added for T4240QDS and T4160QDS Changes: For Secure boot, CPC is configured as SRAM and used as house keeping area which needs to be disabled. So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T4240QDS. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * powerpc/mpc85xx: SECURE BOOT- Add secure boot target for B4860QDSAneesh Bansal2014-04-22-6/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Changes: 1. L2 cache is being invalidated by Boot ROM code for e6500 core. So removing the invalidation from start.S 2. Clear the LAW and corresponding configuration for CPC. Boot ROM code uses it as hosekeeping area. 3. For Secure boot, CPC is configured as SRAM and used as house keeping area. This configuration is to be disabled once in uboot. Earlier this disabling of CPC as SRAM was happening in cpu_init_r. As a result cache invalidation function was getting skipped in case CPC is configured as SRAM.This was causing random crashes. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * powerpc/mpc85xx: SECURE BOOT- Add NAND secure boot target for BSC9132QDSAneesh Bansal2014-04-22-1/+10
| | | | | | | | | | | | | | | | | | | | In case of secure boot from NAND, the DDR is initialized by the BootROM using the config words (CF_WORDS) in the CF_HEADER and u-boot image is copied from NAND to DDR by the BootROM. So, CONFIG_SYS_RAMBOOT has been defined for Secure Boot from NAND Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * powerpc/mpc85xx: SECURE BOOT- Add secure boot target for BSC9132QDSAneesh Bansal2014-04-22-7/+12
| | | | | | | | | | | | | | | | | | | | Add NOR, SPI and SD secure boot targets for BSC9132QDS. Changes: - Debug TLB entry is not required for Secure Boot Target. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * powerpc/mpc8xxx: SECURE BOOT- Disable law 0 for non PBL platformsAneesh Bansal2014-04-22-0/+10
| | | | | | | | | | | | | | | | | | ISBC creates a LAW 0 entry for non PBL platforms, which is not disabled before transferring the control to uboot. The LAW 0 entry has to be disabled. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * powerpc/p1010rdb: SECURE BOOT- enable workaround for IFC errata A003399Aneesh Bansal2014-04-22-2/+1
| | | | | | | | | | | | | | | | | | The workaround for IFC errata A003399 was not enabled in case of secure boot. So, secure boot from NOR was not working. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * powerpc/p1010rdb: SECURE BOOT enabled for NANDAneesh Bansal2014-04-22-1/+2
| | | | | | | | | | | | | | | | | | | | In case of secure boot from NAND, the DDR is initialized by the BootROM using the config words (CF_WORDS) in the CF_HEADER and u-boot image is copied from NAND to DDR by the BootROM. So, CONFIG_SYS_RAMBOOT has been defined for Secure Boot from NAND. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * fsl/usb: Fix phy type for Second USB controllerNikhil Badola2014-04-22-2/+6
| | | | | | | | | | | | | | | | | | Set correct phy_type value for second USB controller. This is required for supporting SOCs having 2 USB controllers working simultaneously, one with UTMI phy and other with ULPI phy Signed-off-by: Nikhil Badola <B46172@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * PPC 85xx: Add qemu-ppce500 machineAlexander Graf2014-04-22-4/+592
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For KVM we have a special PV machine type called "ppce500". This machine is inspired by the MPC8544DS board, but implements a lot less features than that one. It also provides more PCI slots and is supposed to be enumerated by device tree only. This patch adds support for the generic ppce500 machine and tries to rely solely on device tree for device enumeration. Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Scott Wood <scottwood@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * PPC 85xx: Add ELF entry pointAlexander Graf2014-04-22-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | We want to be able to directly execute the ELF binary without going through the u-boot.bin one. To know where we have to start executing this ELF binary we have to tell the linker where our entry point is. Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Scott Wood <scottwood@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * PPC: 85xx: Generalize DDR TLB mapping functionAlexander Graf2014-04-22-15/+40
| | | | | | | | | | | | | | | | | | | | The DDR mapping function really is just a generic virtual -> physical mapping function. Generalize it so it can support any virtual starting offset and IO maps just the same. Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Scott Wood <scottwood@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * PPC: 85xx: Remove IVOR resetAlexander Graf2014-04-22-101/+5
| | | | | | | | | | | | | | | | | | | | | | There is no need to set IVORs to anything but their default values, so let's leave them where they are. Suggested-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Scott Wood <scottwood@freescale.com> [York Sun: Add back $(obj)start.S section in mpc8572ds/Makefile] Reviewed-by: York Sun <yorksun@freescale.com>
| * fdt_support: Add helper function to read "ranges" propertyAlexander Graf2014-04-22-0/+96
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a helper function that can be used to interpret most "ranges" properties in the device tree. It reads the n'th range out of a "ranges" array and returns the node's virtual address of the range, the physical address that range starts at and the size of the range. Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Scott Wood <scottwood@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * fdt_support: split fdt_getprop_u32_defaultAlexander Graf2014-04-22-6/+34
| | | | | | | | | | | | | | | | | | | | We already have a nice helper to give us a property cell value with default fall back from a path. Split that into two helpers - one for the old path based lookup and one to give us a value based on a node offset. Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Scott Wood <scottwood@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mipsTom Rini2014-04-23-6119/+83
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| * | MAKEALL: remove hard-coded MIPS boardsDaniel Schwierzeck2014-04-20-39/+1
| | | | | | | | | | | | | | | | | | | | | Remove all MIPS boards and use $(targets_by_arch mips) for filling list_MIPS. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | MIPS: drop incaip boardDaniel Schwierzeck2014-04-20-5201/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | This is dead hardware and no one is interested in making the necessary changes for upcoming features like generic board or driver model. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Wolfgang Denk <wd@denx.de>
| * | MIPS: Malta: convert to generic boardPaul Burton2014-04-20-0/+3
| | | | | | | | | | | | | | | | | | | | | This patch converts the MIPS Malta development board to make use of the generic board code now that it is supported on MIPS. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * | MIPS: allow use of generic boardPaul Burton2014-04-20-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | This patch allows MIPS boards to make use of generic board, replacing arch/mips/lib/board.c with common/board_{f,r}.c and struct bd_info with the asm-generic version. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * | board_f: call timer_init on MIPSPaul Burton2014-04-20-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | MIPS needs a call to timer_init to preserve its current behaviour ensuring that the cop0 compare register is initialised appropriately. Reported-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * | board_f: call init_func_ram on MIPSPaul Burton2014-04-20-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Assigning gd->ram_size the return value of initdram matches the existing MIPS board behaviour. Suggested-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * | MIPS: define __init_end in u-boot.ldsPaul Burton2014-04-20-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | The generic board code uses the __init_end symbol to calculate monitor_flash_len. Define said symbol for MIPS, equivalent to __image_copy_end which is used for the same purpose in arch/mips/lib/board.c. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * | MIPS: move mips_io_port_base out of board.cPaul Burton2014-04-20-6/+14
| | | | | | | | | | | | | | | | | | | | | | | | Move the definition of this variable out of arch/mips/lib/board.c in preparation for allowing use of generic board on MIPS, which will lead to this file not being compiled. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * | MIPS: stub interrupt_init functionPaul Burton2014-04-20-0/+10
| | | | | | | | | | | | | | | | | | | | | interrupt_init is called unconditionally by the generic board code. Define a stub for it on MIPS like the enable & disable functions. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * | cosmetic: README: add some entries to Directory HierarchyMasahiro Yamada2014-04-20-0/+5
| | | | | | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | mips: xburst: remove remainders of dead boardMasahiro Yamada2014-04-20-843/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 54e458de deleted qi_lb60 board support because of the incompatible license issue. There is no board with XBurst CPU. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | MIPS: always keep all sections in u-boot ELF binary.Daniel Schwierzeck2014-04-20-27/+32
| |/ | | | | | | | | | | | | | | Always keep all sections in u-boot ELF binary. Move all unneeded sections after _end to avoid allocating space in the final binary. Also remove .deadcode section which is now obsolete. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* | Revert "build: Use filechk rules to create and update u-boot.lds"Masahiro Yamada2014-04-23-5/+4
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit a8b993eb81c142a439c24b871a2317f765fe5397. Commit a8b993eb claims it fixes u-boot.lds rule by replacing $(call if_changed) with $(call filechk). But the problem had already been fixed by commit 395e60cd a few days before commit a8b993eb was posted. There is no reason to apply commit a8b993eb. What is worse is $(call filechk) is too strong to fix the problem and looks weird. Date of the two patches: [1] commit 395e60cdc292dc0183c6867d34b43f14a373df55 Author: Masahiro Yamada <yamada.m@jp.panasonic.com> AuthorDate: Wed Apr 9 20:10:43 2014 +0900 Commit: Tom Rini <trini@ti.com> CommitDate: Fri Apr 11 10:08:42 2014 -0400 replaces $(call if_changed) -> $(call if_changed_dep) [2] commit a8b993eb81c142a439c24b871a2317f765fe5397 Author: Jon Loeliger <jon.loeliger@oracle.com> AuthorDate: Tue Apr 15 16:09:37 2014 -0500 Commit: Tom Rini <trini@ti.com> CommitDate: Fri Apr 18 16:14:16 2014 -0400 replaces $(call if_changed) -> $(call filechk) A conflict must have happened when applying [2], but somehow it was applied, sadly. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Jon Loeliger <jon.loeliger@oracle.com> Cc: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Tom Rini <trini@ti.com>
generated by cgit v1.1 at 2024-10-13 11:24:34 +0000