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| * | ARM: DRA7xx: Enable GMAC clock controlMugunthan V N2013-07-26-1/+12
| | | | | | | | | | | | | | | | | | Enabling CPSW module by enabling GMAC clock control Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
| * | ARM: DRA7xx: Lock DPLL_GMACLokesh Vutla2013-07-26-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | Locking DPLL_GMAC [mugunthanvnm@ti.com:Configure only if CPSW is selected] Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
| * | drivers: net: cpsw: Enable statistics for all portMugunthan V N2013-07-26-0/+1
| | | | | | | | | | | | | | | | | | Enable hardware statistics for all ports, enabling only to host port is useless Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
| * | drivers: net: cpsw: remove hard coding bd ram for cpswMugunthan V N2013-07-26-3/+4
| | | | | | | | | | | | | | | | | | | | | BD ram address may vary in various SOC, so removing the hardcoding and passing the same information through platform data Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
| * | am335x_evm: Add basic READMETom Rini2013-07-26-0/+113
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add a README for the family of boards the am335x_evm covers, and include instructions on preparing and using falcon mode, for various media. Signed-off-by: Tom Rini <trini@ti.com> Reviewed-by: Peter Korsgaard <jacmet@sunsite.dk> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
| * | am335x_evm: Correct CONFIG_CMD_SPL_WRITE_SIZETom Rini2013-07-26-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | We use CONFIG_CMD_SPL_WRITE_SIZE when reading/writing the args portion of falcon mode to NAND. Previously it was half the size of the eraseblock which is too small, increase to eraseblock size. Signed-off-by: Tom Rini <trini@ti.com>
| * | am335x_evm: Update eMMC falcon mode locationsTom Rini2013-07-26-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The previous location used for the "args" portion of falcon mode was too small to allow for a device tree to be saved there, so move the location slightly and increase the size. In addition, our previous kernel location was part of the area we set aside for U-Boot itself, so move it up a bit higher. Signed-off-by: Tom Rini <trini@ti.com> Reviewed-by: Peter Korsgaard <jacmet@sunsite.dk>
| * | am335x_evm: Correct DFU ALT settings for falcon modeTom Rini2013-07-26-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that we have falcon mode enabled, the partiton numbers for NAND have changed, and we need to list entries for updating these parts of the system. While adding falcon mode entires for eMMC (raw), we round up the limit on U-Boot for ease of math later. Signed-off-by: Tom Rini <trini@ti.com> Reviewed-by: Peter Korsgaard <jacmet@sunsite.dk>
| * | README.falcon: Note how we determine if we can boot the OS or notTom Rini2013-07-26-0/+2
| | | | | | | | | | | | | | | Reviewed-by: Peter Korsgaard <jacmet@sunsite.dk> Signed-off-by: Tom Rini <trini@ti.com>
| * | omap3/sys_info: fix printout of OMAP36XX L3 freqencyAndreas Bießmann2013-07-26-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | The OMAP36xx/OMAP37xx family uses L3 frequency of 200MHz instead of 165MHz used by OMAP34xx/OMAP35xx. Also fix checkpatch warning about alignment. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | spl_mmc.c: Detect missing kernel image in RAW MMCTom Rini2013-07-26-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, we assume that if we can read from MMC correctly, we have found a valid image. This is not the case as an empty area will read just fine. Add a check for a valid IH_MAGIC. Signed-off-by: Tom Rini <trini@ti.com> Reviewed-by: Peter Korsgaard <jacmet@sunsite.dk>
| * | da850evm: Use clrbits function with correct endianessChristian Riesch2013-07-26-11/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current code uses clrbits_be32 which is incorrect since we are on a little endian machine here. This patch fixes this issue and also removes some unnecessary code: Reading the current GPIO bank state is not required if we are using the SET and CLEAR GPIO registers for setting/clearing bits. Signed-off-by: Christian Riesch <christian.riesch@omicron.at> Cc: Nagabhushana Netagunte <nagabhushana.netagunte@ti.com> Cc: Rajashekhara, Sudhakar <sudhakar.raj@ti.com>
| * | arm: omap3: spl: Fix problem with 8bit NAND devicesStefan Roese2013-07-26-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | Currently in OMAP3 SPL, the GPMC for NAND is configured for 16bit access. This patch adds support for 8bit NAND devices as well. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Tom Rini <trini@ti.com>
| * | Merge branch 'u-boot/master' into u-boot-arm/masterAlbert ARIBAUD2013-07-25-94824/+11753
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| * | | socfpga: Move board/socfpga_cyclone5 to board/socfpgaDinh Nguyen2013-07-25-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Because the SOCFPGA platform will include support for Cyclone V and Arria V FPGA parts, renaming socfpga_cyclone5 folder to socfpga to be more generic. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Reviewed-by: Pavel Machek <pavel@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Wolfgang Denk <wd@denx.de> CC: Pavel Machek <pavel@denx.de> Cc: Tom Rini <trini@ti.com> v2: - Add Reviewed-by: Pavel Machek - Cc: Tom Rini
| * | | highbank: enable keyed autoboot stopRob Herring2013-07-25-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Restrict autoboot interruption to "s" or "d" keys. This will prevent some unwanted stopping and also allow disabling the reset on command timeout. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
| * | | ARM: highbank: compile misc_init_r only if CONFIG_MISC_INIT_RRob Herring2013-07-25-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Compile misc_init_r only if CONFIG_MISC_INIT_R is enabled. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
| * | | ARM: highbank: setup peripherals based on power domain statusRob Herring2013-07-25-2/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Accessing powered down peripherals will hang the bus, so check power domain status before initializing SATA and fixup the FDT to disable unused peripherals. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
| * | | ARM: highbank: enable reset on command timeoutRob Herring2013-07-25-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable resetting on command timeout. The timeout is set with environment setting bootretry. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
| * | | ARM: highbank: avoid bss write in timer_initRob Herring2013-07-25-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The timer_init function is called before relocation and writes to bss data were corrupting relocation data. Fix this by removing the call to reset_timer_masked. The initial timer count should be 0 or near 0 anyway, so initializing the variables are not needed. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
| * | | ARM: highbank: set timer prescaler to 256Rob Herring2013-07-25-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The 150MHz clock rate gives u-boot time functions problems and there's no benefit to a fast clock, so lower the rate. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
| * | | ARM: highbank: fix get_tbclk value to timer rateRob Herring2013-07-25-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | get_tbclk should return the timer's frequency, not CONFIG_SYS_HZ. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
| * | | ARM: highbank: update config optionsRob Herring2013-07-25-2/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Various changes to highbank config: Enable EFI partitions Enable ext4 and FAT filesystems Enable bootz command and raw initrd Increase cmd and print buffer size to 1K Change serial baudrate to 115200 Enable hush shell Signed-off-by: Rob Herring <rob.herring@calxeda.com>
| * | | net: calxedaxgmac: enable rx cut-thruRob Herring2013-07-25-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no reason to wait for the entire frame to start DMA on receive, so enable rx cut-thru for better performance. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
| * | | ARM: move interrupt_init to before relocationRob Herring2013-07-25-2/+1
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | interrupt_init also sets up the abort stack, but is not setup before relocation. So any aborts during relocation will hang and not print out any useful information. Fix this by moving the interrupt_init to after the stack setup in board_init_f. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
* | | gpio: pca953x: Use ARRAY_SIZE instead of reinventing itAxel Lin2013-08-16-4/+1
| | | | | | | | | | | | | | | | | | Signed-off-by: Axel Lin <axel.lin@ingics.com> Reviewed-by: Thierry Reding <thierry.reding@gmail.com> Acked-by: Marek Vasut <marex@denx.de>
* | | tools/Makefile: Move _GNU_SOURCE to MakefileYork Sun2013-08-16-21/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 669dfc2e adds libfdt_env.h to HOSTCPPFLAGS. It causes stdio.h to be included before _GNU_SOURCE is defined in C files. On some old hosts some prototypes are protected by #ifdef __USE_GNU, which is set when _GNU_SOURCE is defined. Signed-off-by: York Sun <yorksun@freescale.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | image: Display FIT timestamp when bootingSimon Glass2013-08-16-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The timestamp is shown in fit_print_contents() but for some reason not in fit_image_print(). This seems to be an oversight, since it is the latter which is used by bootm. Add timestamp printing in this case. (There is code duplication in these two function, for looking at in a future patch). Signed-off-by: Simon Glass <sjg@chromium.org>
* | | bootm: fix conditional controlling call to fixup_silent_linuxPaul B. Henson2013-08-16-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | This function is only defined if CONFIG_SILENT_CONSOLE is set and CONFIG_SILENT_U_BOOT_ONLY is not set, the call to it should be based on the same conditions. Signed-off-by: Paul B. Henson <henson@acm.org> Acked-by: Simon Glass <sjg@chromium.org>
* | | RFC: bootm: Add silent_linux environment variableSimon Glass2013-08-16-2/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present the console for linux is silent if the U-Boot console is silent, unless CONFIG_SILENT_U_BOOT_ONLY is set. I wonder if a better way would be to have an environment variable to control this? Then we can control the verbosity from scripts, and set the variable to 'no' for those boards that want Linux to boot with console output. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | SPL: Limit image name print lengthTaras Kondratiuk2013-08-16-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | If image name is longer than 32 bytes, then it will be truncated. This will remove '\0' at the end of the line, so printf will go out of string limit. Signed-off-by: Taras Kondratiuk <taras@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* | | Enable xmodem supportAngus Ainslie2013-08-16-4/+20
| | | | | | | | | | | | | | | | | | | | | This is a trivial patch that just enables xmodem downloads using the existing ymodem framework. Signed-off-by: Angus Ainslie <angus@akkea.ca>
* | | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2013-08-14-73/+188
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| * | | include/fsl_usb.h: Cleanup license headerYork Sun2013-08-14-17/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace license header with SPDX license identifier. Replace GPL-2.0 with GPL-2.0+. Signed-off-by: York Sun <yorksun@freescale.com> Acked-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
| * | | powerpc/c29xpcie: add readme document for c29xpciePo Liu2013-08-14-0/+100
| | | | | | | | | | | | | | | | Signed-off-by: Po Liu <Po.Liu@freescale.com>
| * | | powerpc/usb: Depricate usb_phy_type and usb_dr_mode uboot env variablesramneek mehresh2013-08-14-22/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove getting values of usb mode and phy_type from "usb_dr_mode" and "usb_phy_type" uboot env variables. Now, these are determined only from hwconfig string Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
| * | | fsl/usb: Move USB internal phy definitions to fsl_usb.hramneek mehresh2013-08-14-51/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | fsl_usb.h file created to share data bewteen usb platform code and usb ip driver. Internal phy structure definitions moved to this file Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
| * | | powerpc/mpc85xx:Avoid hardcoded init for serdes block 1 & 2Prabhakar Kushwaha2013-08-14-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is not necessary for all processor to have serdes block 1 & 2. They may have only one serdes block. So, put serdes block 1 & 2 related code under defines Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* | | | tegra: Avoid using I2C prior to relocationSimon Glass2013-08-13-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra recently moved to the new I2C framework, which sets up I2C prior to relocation, and prior to calling i2c_init_board(). This causes a crash on Tegra boards. Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org>
* | | | Merge branch 'dcc' of git://www.denx.de/git/u-boot-microblazeTom Rini2013-08-13-24/+25
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| * | | serial: arm_dcc: Register with serial coreJagannadha Sutradharudu Teki2013-08-13-6/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Register arm_dcc with drivers/serial/serial.c Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | serial: arm_dcc: Remove stdio structure supportJagannadha Sutradharudu Teki2013-08-13-22/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Removed stdio structure ops support on arm_dcc driver, and need to register with serial core so-that it can access like remianing serial drivers. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2013-08-13-814/+4027
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| * | | | powerpc/mpc85xx: Cleanup license header in source filesYork Sun2013-08-12-232/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the license header introduced by the following patches Add TWR-P10xx board support Add T4240EMU target IDT8T49N222A configuration code Add C29x SoC support Add support for C29XPCIE board Signed-off-by: York Sun <yorksun@freescale.com>
| * | | | 83xx/pcie: fix build error for 83xx pcieRoy Zang2013-08-09-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the following build error caused by patch "powerpc/pcie: add PCIe version 3.x support": pcie.c:302:34: error: 'PCI_LTSSM' undeclared (first use in this function) pcie.c:303:15: error: 'PCI_LTSSM_L0' undeclared (first use in this function) Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
| * | | | powerpc/mpc8xxx: Fix TIMING_CFG_3[EXT_ACTTOPRE]James Yang2013-08-09-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The TIMING_CFG_3[EXT_ACTTOPRE] register field is 2 bits wide, but the mask omitted the LSB. This patch provides a 2-bit wide mask. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
| * | | | powerpc/c29xpcie: add support for C29XPCIE boardMingkai Hu2013-08-09-0/+1030
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | C29XPCIE board is a series of Freescale PCIe add-in cards to perform as public key crypto accelerator or secure key management module. It includes C293PCIE board, C293PCIE board and C291PCIE board. - 512KB platform SRAM in addition to 512K L2 Cache/SRAM - 512MB soldered DDR3 32bit memory - CPLD System Logic - 64MB x16 NOR flash and 4GB x8 NAND flash - 16MB SPI flash Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Singed-off-by: Po Liu <Po.Liu@freescale.com> [yorksun: Fixup include/configs/C29XPCIE.h] Signed-off-by: York Sun <yorksun@freescale.com>
| * | | | powerpc/85xx: Add C29x SoC supportMingkai Hu2013-08-09-0/+109
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Freescale C29x family is a high performance crypto co-processor. It combines a single e500v2 core with necessary SEC engine. There're three SoC types(C291, C292, C293) with the following features: - 512K L2 Cache/SRAM and 512 KB platform SRAM - DDR3/DDR3L 32bit DDR controller - One PCI express (x1, x2, x4) Gen 2.0 Controller - Trust Architecture 2.0 - SEC6.0 engine Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Po Liu <Po.Liu@freescale.com>
| * | | | powerpc/pcie: remove PCIe version 3.x define for B4860 and B4420Zang Roy-R619112013-08-09-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | B4860 and B4420 has PCIe version 2.4 IP instead of 3.x Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
| * | | | powerpc/pcie: add PCIe version 3.x supportZang Roy-R619112013-08-09-15/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T4240 PCIe IP is version 3.0 and has some update comparing previous QorIQ products. 1. Move Freescale specific register define to arch/powerpc/include/asm/fsl_pci.h and update the register offset define for T4240. 2. add the status/control register define use status/control register to judge the link status 3. The original code uses 'Programming Interface' field to judge if PCIE is EP or RC mode, however, T4240 does not support this functionality. According to PCIE specification, 'Header Type' offset 0x0e is used to indicate header type, so for PCIE controller, the patch changes code to use 'Header Type' field to identify if the PCIE is RC or EP mode. This patch fixes the PCIe card link up issue on T4240QDS. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
generated by cgit v1.1 at 2024-11-14 03:25:19 +0000