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* arm: ls102xa: Add SystemID EEPROM support for LS1021ATWR boardAlison Wang2014-11-24-2/+13
| | | | | | | | | | | | | | | SystemID information could be read through I2C1 from EEPROM on LS1021ATWR board. As LS1 is a little-endian processor, getting the version ID by be32_to_cpu() is wrong. Fix it by using e.version directly. This change will be compatible for both ARM and PowerPC. As there is an errata that I2C1 could not work in SD boot, reading EEPROM through I2C1 is disabled too in SD boot. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* ls102xa: ifc: nor: fix the write issue when bytes unalignedYuan Yao2014-11-24-0/+2
| | | | | | | | | | | | | Add define CONFIG_SYS_WRITE_SWAPPED_DATA. For LS1021AQDS and LS1021QTWR nor flash write should swap the bytes when handle unaligned tail bytes. Because of the ending, if the date bus width is 16-bits and the number of bytes is odd, we should swap the byte when write the last one. Signed-off-by: Yuan Yao <yao.yuan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* arm: ls102xa: Remove bit reversing for SCFG registersAlison Wang2014-11-24-9/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | SCFG_SCFGREVCR is SCFG bit reverse register. This register must be written with 0xFFFFFFFF before writing to any other SCFG register. Then other SCFG register could be written in big-endian mode. Address: 157_0000h base + 200h offset = 157_0200h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15|16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 W/R SCFGREV Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0-31 SCFGREV SCFG Bit Reverse Control Filed 32'h 0000_0000 - No bit reverse is applied 32'h FFFF_FFFF - Bit reverse is applied; so 31:0 will be stored/read as 0:31 This patch removes the bit reversing for SCFG registers in u-boot. It will be implemented through PBI commands in RCW .pbi write 0x570200, 0xffffffff .end So other SCFG register could be written in big-endian mode in u-boot or kernel directly. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* arm: ls102xa: Add snoop disable for slave port 0, 1 and 2Jason Jin2014-11-24-0/+18
| | | | | | | | | Disable the snoop for slave interface 0, 1 and 2 to avoid the interleaving on the CCI400 BUS. Signed-off-by: Jason Jin <Jason.Jin@freescale.com> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* ls1: config: Enable USB EHCI Host on LS1021AQDSNikhil Badola2014-11-24-0/+17
| | | | | | | Enable USB EHCI Host on LS1021AQDS Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* drivers: usb: fsl: Define USB configs for LS102XANikhil Badola2014-11-24-0/+7
| | | | | | | | Define USB configs for LS1021XA such as CONFIG_SYS_FSL_USB1_ADDR, CONFIG_USB_MAX_CONTROLLER_COUNT Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* drivers : usb: fsl: Implement usb Erratum A007798 workaroundNikhil Badola2014-11-24-2/+17
| | | | | | | | Set TXFIFOTHRESH to adjust ddr pipeline delay for successful large usb writes Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* drivers: usb: fsl: Move USB Errata checking codeNikhil Badola2014-11-21-56/+68
| | | | | | | | | | Move USB Errata checking code from "arch/powerpc" to architecture independent file "fsl_usb.h" so that errata(s) become independent of the architecture. For each erratum checking function for PPC arch, define a nop function for non PPC arch for successful compilation in either case Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* u_qe: add u_qe_upload_firmware for u_qeZhao Qiang2014-11-19-2/+131
| | | | | Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* arm: ls102xa: Fixed a register definition errorTang Yuantian2014-11-19-1/+1
| | | | | | | There are 8 SCFG_SPARECR registers in SCFG memory block, not one. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* qe: add qe support for ls1021a-twr boardZhao Qiang2014-11-19-0/+14
| | | | | Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* qe: add qe support to ls1021aqdsZhao Qiang2014-11-19-0/+15
| | | | | | | add qe support to ls1021aqds Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* qe: add u-qe support to arm boardZhao Qiang2014-11-19-1/+33
| | | | | | | | | ls1021 is arm-core and support qe which is u-qe. add u-qe init for arm board. Signed-off-by: Zhao Qiang <B45475@freescale.com> [York Sun: Fix compiling error caused by u_qe_init()] Reviewed-by: York Sun <yorksun@freescale.com>
* ARM: atmel: add sama5d4 xplained ultra board supportBo Shen2014-11-17-0/+583
| | | | | | | | | | | The code for this board supports following features: - Boot media support: NAND flash/SD card/SPI flash - Support LCD display (optional, disabled by default) - Support ethernet - Support USB mass storage Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* ARM: atmel: add sama5d4ek board supportBo Shen2014-11-17-9/+868
| | | | | | | | | | | The code for this board supports following features: - Boot media support: NAND flash/SD card/SPI flash - Support LCD display - Support ethernet - Support USB mass storage Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* net: macb: enable GMAC IP without GE feature supportBo Shen2014-11-17-1/+7
| | | | | | | | | | The User Register in GMAC IP is used to select interface type. When with GE feature, it is used to select interface between RGMII and GMII. If without GE feature, it is used to select interface between MII and RMII. Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* mtd: atmel_nand: runtime to build gf table for pmeccJosh Wu2014-11-17-1/+78
| | | | | | | | | | | | | | | As in SAMA5D4 SoC, the gf table in ROM code can not be seen. So, when we try to use PMECC, we need to build it when do initialization. Add a macro NO_GALOIS_TABLE_IN_ROM in soc header file. If it is defined we will build gf table runtime. The PMECC use the BCH algorithm, so based on the build_gf_tables() function in lib/bch.c, we can build the Galois Field lookup table. Signed-off-by: Josh Wu <josh.wu@atmel.com> Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* arm, spl, at91: add spl support for the corvus boardHeiko Schocher2014-11-17-18/+151
| | | | | | | | | | | | | | replaces the at91bootstrap code with SPL code. make the spl image with: ./tools/mkimage -T atmelimage -d spl/u-boot-spl.bin spl/boot.bin this writes the length of the spl image into the 6th execption vector. This is needed from the ROM bootloader. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Bo Shen <voice.shen@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* arm, at91, spl: add spl support for the taurus boardHeiko Schocher2014-11-17-13/+127
| | | | | | | | | | | | | | replaces the at91bootstrap code with SPL code. make the spl image with: ./tools/mkimage -T atmelimage -d spl/u-boot-spl.bin spl/boot.bin this writes the length of the spl image into the 6th execption vector. This is needed from the ROM bootloader. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* arm, spl, at91: add at91sam9260 and at91sam9g45 spl supportHeiko Schocher2014-11-17-97/+430
| | | | | | | | | | | add support for using spl code on at91sam9260 and at91sam9g45 based boards. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Bo Shen <voice.shen@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> [adopt Bo's change in spl.c] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* spl, mtd, nand, atmel_nand: invert device ready pin logicHeiko Schocher2014-11-17-3/+3
| | | | | | | | | | | device ready pin is signalling that the device is ready on state 1 not on 0. Simmiliar as it is in drivers/mtd/nand/nand_spl_simple.c Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Reviewed-by: Bo Shen <voice.shen@atmel.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* spl, nand, atmel_nand: add erase one block functionHeiko Schocher2014-11-17-0/+34
| | | | | | | | | | | erase one nand block in spl code. keep it simple, as size matters This is used on the upcoming taurus spl support. Signed-off-by: Heiko Schocher <hs@denx.de> Acked-by: Scott Wood <scottwood@freescale.com> Reviewed-by: Bo Shen <voice.shen@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* mtd: atmel_nand: add missing includeHeiko Schocher2014-11-17-0/+1
| | | | | | | | | | | using this driver in SPL code with CONFIG_SPL_NAND_ECC configured leads in an compileerror. Fix this. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Reviewed-by: Bo Shen <voice.shen@atmel.com> [fix subject] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* spl, nand: add option to boot raw u-boot.bin image onlyHeiko Schocher2014-11-17-5/+28
| | | | | | | | | | | enable to boot only a raw u-boot.bin image from nand with the CONFIG_SPL_NAND_RAW_ONLY define. This option saves space on boards where spl space is low. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Reviewed-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* arm, at91: add missing ddr2 cr register MPDDRC_CR_EBISHARE defineHeiko Schocher2014-11-17-0/+1
| | | | | | Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* arm, at91: compile mpddrc ram init code also for AT91SAM9M10G45Heiko Schocher2014-11-17-2/+15
| | | | | | | | | | | | - compile mpddrc ram init code also for AT91SAM9M10G45 based boards. - in CONFIG_SAMA5D3 case, look for the ATMEL_MPDDRC_CR_DECOD_INTERLEAVED in the cr configuration Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Reviewed-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* arm, at91, mpddrc: fix typo in ddr2_init()Heiko Schocher2014-11-17-1/+1
| | | | | | | | | | | use the configure value for computing the ba_off value not the value from the cr register. This leaded in a wrong ram configuration on the upcoming corvus spl board support. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* arm, at91: add spi dataflash support for the taurus boardHeiko Schocher2014-11-17-0/+28
| | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Bo Shen <voice.shen@atmel.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* spi, atmel: move CONFIG_SYS_SPI_WRITE_TOUT into common headerHeiko Schocher2014-11-17-13/+4
| | | | | | | | | | | | move CONFIG_SYS_SPI_WRITE_TOUT into drivers/spi/atmel_spi.h and define a default value. Delete this define in the board config files, where it is possible (all boards use currently the same value). Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* arm, at91: generate boot.bin file for all atmel SoCHeiko Schocher2014-11-17-3/+5
| | | | | | | | | | generate the boot.bin file for all atmel SoC (arm920, arm926, armv7) Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com> [fix subject] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* ARM: atmel: spl: make css field configurableBo Shen2014-11-17-2/+4
| | | | | | | | | The clock source for master clock can be slow clock, main clock, plla clock or upll clock. So, make the clock source selection field in mckr can be configured. Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* ARM: atmel: spl: make initialization more stableBo Shen2014-11-17-0/+4
| | | | | | | | We need to make sure the main clock ready field in MCFR is set after switch to main crystal oscillator. Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* ARM: at91 series: convert to generic boardBo Shen2014-11-17-0/+6
| | | | | | Signed-off-by: Bo Shen <voice.shen@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* net: macb: write mac address when initializationBo Shen2014-11-17-0/+9
| | | | | | | | | | | | | | | | | When boot up without mac address setting, it will give the warning message like: "Warning: failed to set MAC address", however when execute network related command, it still execute them without any warning information. With this patch, it will exit directly with following information: "gmac0: mac address is not valid" It also solve the problem after bootup then set mac address and the mac address won't set to net device issue. Signed-off-by: Bo Shen <voice.shen@atmel.com> Tested-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini2014-11-17-107/+93
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| * sh: Move SH_32BIT to KconfigNobuhiro Iwamatsu2014-11-17-4/+13
| | | | | | | | | | | | | | This moves SH_32BIT to Kconfig, and removes SH_32BIT from config files. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * sh: define CONFIG_CPU_SH4A for some boardsMasahiro Yamada2014-11-13-7/+7
| | | | | | | | | | | | | | | | Precisely, these boards are SH4A rather than SH4. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * sh: consolidate CONFIG_SYS_CPU definesMasahiro Yamada2014-11-13-66/+8
| | | | | | | | | | | | | | | | | | | | Now each board selects one of CONFIG_CPU_SH2, CONFIG_CPU_SH3, CONFIG_CPU_SH4, so let's move CONFIG_SYS_CPU definition to arch/sh/Kconfig. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * sh: move CONFIG_{SH2, SH2A, SH3, SH4} to KconfigMasahiro Yamada2014-11-13-18/+53
| | | | | | | | | | | | | | | | | | | | | | This commit moves CONFIG_SH2, CONFIG_SH2A, CONFIG_SH3, CONFIG_SH4 to Kconfig renaming into CONFIG_CPU_SH2, CONFIG_CPU_SH2A, CONFIG_CPU_SH3, CONFIG_CPU_SH4, respectively because arch/sh/Kconfig of Linux uses CONFIG_CPU_SH* convention. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * sh: use more descriptive prompts for board select menuMasahiro Yamada2014-11-13-19/+19
| | | | | | | | | | | | | | | | | | | | | | | | The current prompts were added by a conversion tool based on board directory names when switching to Kconfig. Use better prompts mostly taken from from arch/sh/boards/* of Linux Kernel. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * board/renesas/ecovec/ecovec.c: fix buffer overflowWolfgang Denk2014-11-10-1/+1
| | | | | | | | | | | | | | | | | | | | | | Fix error detected by cppcheck: [board/renesas/ecovec/ecovec.c:66]: (error) Buffer is accessed out of bounds. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | Merge branch 'rmobile' of git://git.denx.de/u-boot-shTom Rini2014-11-17-331/+4052
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| * | arm: rmobile: replacement of common parts of config by rcar-gen2-common.hNobuhiro Iwamatsu2014-11-17-363/+18
| | | | | | | | | | | | | | | | | | | | | | | | Common part of config for lager, koelsch, alt and gose board will be able to replace rcar-gen2-common.h. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | arm: rmobile: configs: Collect up common part of config for R-Car SoCsNobuhiro Iwamatsu2014-11-17-0/+95
| | | | | | | | | | | | | | | | | | | | | | | | | | | The lager, koelsch, alt, gose board supported in rmobile is distinguished as the R-Car Gen2 series and has much common setting. This collect up the common part of config as rcar-gen2-common.h. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | arm: rmobile: gose: Remove dram_init_banksize functionNobuhiro Iwamatsu2014-11-17-7/+1
| | | | | | | | | | | | | | | | | | | | | | | | Gose board is defined CONFIG_SYS_SDRAM_BASE, and this can use a basic function of dram_init_banksize instead. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | arm: rmobile: lager: Remove dram_init_banksize functionNobuhiro Iwamatsu2014-11-17-7/+1
| | | | | | | | | | | | | | | | | | | | | | | | Lager board is defined CONFIG_SYS_SDRAM_BASE, and this can use a basic function of dram_init_banksize instead. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | arm: rmobile: koelsch: Remove dram_init_banksize functionNobuhiro Iwamatsu2014-11-17-7/+1
| | | | | | | | | | | | | | | | | | | | | | | | Koesch board is defined CONFIG_SYS_SDRAM_BASE, and this can use a basic function of dram_init_banksize instead. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | arm: rmobile: alt: Remove dram_init_banksize functionNobuhiro Iwamatsu2014-11-17-7/+1
| | | | | | | | | | | | | | | | | | | | | | | | Alt board is defined CONFIG_SYS_SDRAM_BASE, and this can use a basic function of dram_init_banksize instead. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | arm: rmobile: alt: Change clock of SCIF to external clockNobuhiro Iwamatsu2014-11-10-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | Change clock of SCIF for Alt board is used to external clock. This changes to using external clock. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | arm: rmobile: kconfig: Remove '+S:' prefix from defconfig filesNobuhiro Iwamatsu2014-11-10-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | '+S' is unnecessary because boards of rmobile do not use SPL. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> CC: Masahiro Yamada <yamada.m@jp.panasonic.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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