| Commit message (Collapse) | Author | Age | Lines |
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Abstracted the CSF size in imximage from a hardcoded value to a config
setting CONFIG_CSF_SIZE. This configuration is only enabled for secure
boot.
Increased the size of the CSF default allocation to 0x4000. This size
covers the event the worst case of 4906-bits keys.
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Since the 6ul does not enable the CONFIG_LDO_BYPASS_CHECK, but have
to use the set_wdog_reset function. Need to move the funciton out of
CONFIG_LDO_BYPASS_CHECK to resolve build issue.
Signed-off-by: Ye.Li <B37916@freescale.com>
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When using watchdog timeout in kernel, the reset does not output the
WDOG_B signal, so the power supply won't be reset. To solve the problem,
we enable it in u-boot.
Signed-off-by: Ye.Li <B37916@freescale.com>
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Change L2 prefetch offset to 0 to make system stable.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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From temp sensor guys:
"
I confirmed the math with him(had do the accuracy study) today.
The new, final equation is:
Tmeas = (Nmeas - n1) / slope + t1 + offset
n1= fused room count
t1= 25
offset=3.580661
slope= 0.4148468 – 0.0015423*n1
"
87723f903454aaf17336e0fe9098ea7911c19f3c update the thermal with not
accurate slope parameters. This patch fix it.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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The mx6ul ddr3 arm2 board needs rework to enable the emmc. Since the pin
used by emmc are multiplexed with SD1 and QSPI, the SD1 and QSPI can't work.
The u-boot build target for emmc is: mx6ul_14x14_ddr3_arm2_emmc_config
Signed-off-by: Ye.Li <B37916@freescale.com>
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To resolve USB camera bandwidth issue, the patch sets recommended AQoS
setting from IC team value for peripheral and only on imx6qp.
The address is: 0xbb0608, the value is: 0x80000201
Signed-off-by: Ye.Li <B37916@freescale.com>
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For nand boot, the mtdpart info are needs to load kernel and rootfs.
Signed-off-by: Ye.Li <B37916@freescale.com>
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Configure the PMIC_STBY_REQ pin as open drain 100K according to
the design team's requirement for the PMIC_STBY_REQ pin.
Signed-off-by: Bai Ping <b51503@freescale.com>
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Update the DDR script for i.MX7D 12x12 LPDDR3 ARM2 board and
i.MX7D 19x19 LPDDR3 ARM2 board to file "7D_lpddr3_0_3.ds5"
Updated items:
Changes DRAMTMG2 WR2RD from 7 to 8.
Compass link for this script:
http://compass.freescale.net/livelink/livelink?func=ll
&objid=233861153&objAction=browse&sort=name
Test results:
Passed overnight test on two MX7D 12x12 LPDDR3 ARM2 board
Passed overnight test on one MX7D 19x19 LPDDR3 ARM2 board
Signed-off-by: Ye.Li <B37916@freescale.com>
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Since directory name changed, need to change it in imximage.cfg, or
we will get "Can't stat board/freescale/mx6ulevk/plugin.bin".
Since this commit 7331a4cc0853722b4c3addf1927a2797f39f5de2
missed to update ddr, here update the plugin code.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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updated DDR Script of 6UL EVK Board to avoid a calibration error
when using “DDR_Stress_Tester_V1.04.exe”.
Updated items:
[Modified] setmem /32 0x020E027C = 0x00000008
[Modified] setmem /32 0x020E0280 = 0x00000038
[Modified] setmem /32 0x021B080C = 0x00070007
[Added ] setmem /32 0x021B0858 = 0x00000F00
The script versions of EVK board and Validation Board from the following link:
http://compass.freescale.net/livelink/livelink?func=ll&objId=234191407&obj
Action=browse&viewType=1
Test Results:
Tested on two boards, both passed overnight memtester stress test.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Since the flash blocks are locked at default , need to set
"CONFIG_SYS_FLASH_PROTECTION" to unlock them before write/erase.
The patch also add the pinmux for LBA (ADV) pin and set eimnor enabled at
default.
Signed-off-by: Ye.Li <B37916@freescale.com>
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1. There is conflict when building secure boot, because some common
codes for MPC are included by using same configuration. So modify the
makefile to get rid of them.
2. The 6UL arch config is missed in hab.h. Fix this issue by using
the CONFIG_ROM_UNIFIED_SECTIONS.
Signed-off-by: Ye.Li <B37916@freescale.com>
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There is a hole in shadow registers address map of size 0x100
between bank 5 and bank 6 on iMX6QP, iMX6DQ, iMX6SDL, iMX6SX and iMX6UL.
Bank 5 ends at 0x6F0 and Bank 6 starts at 0x800. When reading the fuses,
we should account for this hole in address space.
Similar hole exists between bank 14 and bank 15 of size
0x80 on iMX6QP, iMX6DQ, iMX6SDL and iMX6SX.
Note: iMX6SL has only 0-7 banks and there is no hole.
Note: iMX6UL doesn't have this one.
When reading, we use register offset, so need to account for holes
to get the correct address.
When writing, we use bank/word index, there is no need to account
for holes, always use bank/word index from fuse map.
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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i2c_pad_info3's i2c index should 2, but not 1. Correct it.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Add SION bit for all i2c pin mux settings.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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This patch is to support Bus Encryption Engine(BEE) for i.MX 6UL.
Supported feature:
1. SNVS key and soft key
2. CTR and ECB mode
3. Specify address region to bee.
Two commands are included:
bee init [key] [mode] [start] [end] - BEE block initial
"Example: bee init 1 1 0x80000000 0x80010000\n"
bee test [region]
"Example: bee test 1\n"
Mapping:
[0x10000000 - (0x10000000 + size - 1)] : [start - (start + size - 1)]
[0x30000000 - (0x30000000 + IRAM_SIZE - 1)] : [IRAM_BASE_ADDR -
(IRAM_BASE_ADDR + IRAM_SIZE - 1)]
Whatever start is, start - (start + size -1) will be fixed mapping to
0x10000000 - (0x10000000 + size - 1)
Since default AES region's protected size is SZ_512M, so
on mx6ul evk board, you can not simply run 'bee init', it will
overlap with uboot execution environment, you can use
'bee init 0 0 0x80000000 0x81000000'.
If want to use bee, Need to define CONFIG_CMD_BEE in board configuration
header file, since CONFIG_CMD_BEE default is not enabled.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Since there is another 9x9 package for mx6ul, modify the BSP names
of ddr3 arm2 board and evk board to add 14x14 package info.
Also modify the loaded dtb file to align with kernel.
After the change, the build target for mx6ul ddr3 arm2 board is:
mx6ul_14x14_ddr3_arm2_config
and the build target for mx6ul evk board is:
mx6ul_14x14_evk_config
Signed-off-by: Ye.Li <B37916@freescale.com>
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Add the default TSOP NAND support and build target.
New build target for nand boot: mx7d_19x19_lpddr3_arm2_nand_config
Signed-off-by: Ye.Li <B37916@freescale.com>
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On mx7d 12x12 lpddr3 arm2 board, POR_B reset in uboot will fail stress
reset test, and hangs in rom code. Rom log buffer show thats wrong
hab_image_entry and runs into serial download mode. Also there is no
time delay reset circuit for this board.
We found when disable CONFIG_VIDEO, all seems fine. Actually,
only the following piece of code can make stress reset ok,
"
writel(LCDIF_CTRL1_VSYNC_EDGE_IRQ, ®s->hw_lcdif_ctrl1_clr);
while (--timeout) {
if (readl(®s->hw_lcdif_ctrl1) & LCDIF_CTRL1_VSYNC_EDGE_IRQ)
break;
udelay(1);
}
"
Here we use lcdif_power_down API which is better to shutdown lcdif same as
the way used in arch_preboot_os.
Implement reset_misc for mx7, since it does not hurt for others boards.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Include fb.h in mxsfb.h.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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On MX7D, boot rom can provide some boot information such as boot device,
arm freq, axi freq, etc. (see the structure below)
Offset Byte4 | Byte3 | Byte2 | Byte1
0x0 Reserved | Boot Device Type | Boot Device Instance | Reserved
0x4 ARM core frequency(in Hz)
0x8 AXI bus frequency(in Hz)
0x0C DDR frequency(in Hz)
0x10 GPT1 input clock frequency(in Hz)
0x14 Reserved
0x18
0x1C
The boot information can be accessed by get the pointer at 0x1E8. This patch
changes the u-boot to use the new approach. When manufacture boot, the info
recorded is the actual SD port, not the failed device.
Signed-off-by: Ye.Li <B37916@freescale.com>
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Set wdog WCR register SRS bit to turn off internal reset signal WDOG_RESET_B_DEB
for mx7d. So that the warm reset is disabled.
Signed-off-by: Ye.Li <B37916@freescale.com>
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This config was missed when porting to 2015.04 u-boot.
Signed-off-by: Han Xu <b45815@freescale.com>
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If no epdc pannel is plugged into mx6slevk board, no need to
do the elan init operation for each i2c init transfer which
will slow the i2c speed.
If epdc panned is plugged into mx6slevk board, all works as the
original patch: "b6ba68516b681a38025252bd0ef6a6ed3e8adfa0" -
"MLK-10215 Add elan init in i.MX6SL-EVK board"
This patch also fix a bug that setup_elan_pads should be called in
board_init, but not board_late_init where too late to setup_elan_pads.
And align pad property with linux kernel, value is 0x17000.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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* Add mx7d_19x19_lpddr3_arm2 target board supprt
* Enable i2c, spinor, usb, usdhc, qspi, enet, uart
* Build targets
mx7d_19x19_lpddr3_arm2_defconfig
mx7d_19x19_lpddr3_arm2_eimnor_defconfig
- Set EIMNOR settings for Intel Sibley Asynchronous mode
- Set flash sector size for 256kb (erase block size)
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
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The iomuxc structure has changed to add 0x4000 offset for i.MX6SX and UL,
so when using this structure to access gpr registers needs to change
the base address to IOMUXC_BASE_ADDR.
Signed-off-by: Ye.Li <B37916@freescale.com>
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This piece of code will never be compiled and used,
since we use pmic framework. So remove the code block.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Use pmic framework to simplify code and make code clean.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Get the Unique ID of the chip from the fuse TESTER0 and TESTER1.
Signed-off-by: Ye.Li <B37916@freescale.com>
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Add android features booti, fastboot and recovery to i.MX6UL EVK board.
Since there is no user button on the board, we can't implement
the recovery by using button.
Signed-off-by: Ye.Li <B37916@freescale.com>
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Correct USDHC Port Selection bits in bmode value for SD1 and SD2.
Signed-off-by: Ye.Li <B37916@freescale.com>
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Since the NAND has two pins conflict with SD2, when NAND is enabled, we
must disable SD2. So the CONFIG_SYS_FSL_USDHC_NUM needs configure to 1
and should be moved to under defining CONFIG_SYS_USE_NAND.
New build target for NAND boot:
mx6ul_ddr3_arm2_nand_config
Signed-off-by: Ye.Li <B37916@freescale.com>
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Correct the EIMNOR settings to non-mux mode and set the environment
variables configuration to FLASH when using WEIMNOR boot.
New target is added for build WEIMNOR boot u-boot:
mx6ul_ddr3_arm2_eimnor_config
Signed-off-by: Ye.Li <B37916@freescale.com>
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Add maximum ecc strength for each platfrom to avoid the calculated ecc
exceed the limitation.
Signed-off-by: Han Xu <b45815@freescale.com>
(cherry picked from commit fdc5bac6ae8b699924c4e84b86e38aa73f694827)
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This patch adds enable/disable hooks support for ldb_di[0/1] clocks
and enables/disables them when necessary.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit 839a1da941be48baf27c9cb28939cc6b2030424a)
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The LDB is found in MX6 variants and MX53, so this patch makes the ldb_di clock
relevant code be built only for them.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit c0dc175a9780505ec8939bda5dda9c2ec549a7f0)
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Move CONFIG_IMX_THERMAL to mx6_common.h
Make CONFIG_MXC_OCOTP only depends on CONFIG_CMD_FUSE, since when
THERMAL is not implemented, we may use fuse.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Change MXC_CCM_CCGR6_I2C4_xx to MXC_CCM_CCGR6_I2C4_SERIAL_xx
Remove duplicated mxs_set_vadcclk
Correct enable_pll_video usage
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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From IC guys:
"
After a thorough accuracy study of the Temp sense circuit,
we found that with our current equation, an average part can
read 7 degrees lower than a known forced temperature.
We also found out that the standard variance was around 2C;
which is the tightest distribution that we could create.
We need to change the temp sense equation to center the average
part around the target temperature.
Old Equation:
Temp = Troom,cal – slope*(Count measured – Count room fuse)
Where
Troom,cal = 25C and
Slope = 0.4297157 – (0.0015974 * Count room fuse)
New Equation:
Temp = Troom,cal – slope*(Count measured – Count room fuse) +offset
Where
Troom,cal = 25C and
Slope = 0.4445388 – (0.0016549 * Count room fuse)
Offset = 3.580661
"
According the new equation, update the thermal driver.
c1 and c2 changed to u64 type and update comments.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Add board code for mx6ul ddr3 arm2 board.
QSPI, USDHC, ENET, USB, VIDEO, SPINOR, EIMNOR
Add sd1, qspi and spinor boot support
DDR script is 1.02 version.
Signed-off-by: Fugang Duan <b38611@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Add BSP codes to support modules on the board:
I2C, SD/eMMC, NAND, QSPI, FEC1/FEC2, USB, LCDIF, 74LV, Serial
DDR version: 1.0
Build target: mx6ulevk_config
mx6ulevk_qspi1_config
Signed-off-by: Ye.Li <B37916@freescale.com>
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register
Add platform check to avoid to access the reserved register
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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i.MX6UL qspi controller also needs at least 16 bytes when writing.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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comment out GPIO6/7 for MX6UL
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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PAD_CTL_SPEED_LOW for mx6ul same with mx6sx.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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add i.MX6UL clock related settings/macros/apis
When using TFT43AB, its pixel size is 480x272 which needs a
slow pix clock. Without apply the test_div in PLL video, we can't
get the pix clock in the rate.
So change the LCDIF clock calculation to use the test_div.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
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I2C4 support for i.MX
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Remove PCIe, xPU power, PL310 L2 Cache for MX6UL.
Update FEC MAC address, WDOG settings, USDHC clock rate.
Signed-off-by: Ye.Li <B37916@freescale.com>
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