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* | | mpc8xx: remove qs850, qs860t board supportMasahiro Yamada2014-07-07-3876/+3
| | | | | | | | | | | | | | | | | | These boards are old enough and have no maintainers. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | | tpm: don't use unneeded double bracketsJeroen Hofstee2014-07-07-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | clang is tempted to inteprete such a condition as a assignment as well. Since it isn't don't use double brackets. cc: Tom Wai-Hong Tam <waihong@chromium.org> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
* | | vcma9/lowlevel_init.S: trivial: terminate commentJeroen Hofstee2014-07-07-1/+1
| | | | | | | | | | | | Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
* | | README: document CONFIG_ENV_IS_IN_SPI_FLASHWu, Josh2014-07-07-0/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The option can be used to save the environment in spi flash. Implementation code is already exist in command/env_sf.c. But the documentation is missing. This patch add the details for this option to the README file. Signed-off-by: Josh Wu <josh.wu@atmel.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* | | env_fat: use get_device_and_partition() during env save and loadWu, Josh2014-07-07-60/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use get_device_and_partition() is better since: 1. It will call the device initialize function internally. So we can remove the mmc intialization code to save many lines. 2. It is used by fatls/fatload/fatwrite. So saveenv & load env should use it too. 3. It can parse the "D:P", "D", "D:", "D:auto" string to get correct device and partition information by run-time. Also we remove the FAT_ENV_DEVICE and FAT_ENV_PART. We use a string: FAT_ENV_DEVICE_AND_PART. For at91sam9m10g45ek, it is "0". That means use device 0 and if: a)device 0 has no partition table, use the whole device as a FAT file system. b)device 0 has partittion table, use the partition #1. Refer to the commit: 10a37fd7a4 for details of device & partition string. Signed-off-by: Josh Wu <josh.wu@atmel.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* | | am43xx: Tune the system to avoid DSS underflowsCooper Jr., Franklin2014-07-07-10/+111
| | | | | | | | | | | | | | | * This is done by limiting the ARM's bandwidth and setting DSS priority in the EMIF controller to ensure underflows do not occur.
* | | am43xx: Update EMIF DDR3 Configuration for AM43x GPFranklin S. Cooper Jr2014-07-07-0/+114
| | | | | | | | | | | | | | | | | | | | | | | | | | | * Boot failures have been discovered due to a combination of routing issues and non optimal ddr3 timings in the EMIF * Since ddr3 timings are different after significant board layout changes different timings are required for alpha, beta and production boards. Signed-off-by: Franklin S. Cooper Jr <fcooper@ti.com>
* | | doc/README.falcon: Clarify steps slightly.Tom Rini2014-07-07-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | Make it clear that we need to load a legacy-formatted (aka uImage) kernel into memory as well as the DT if used before using "spl export". Cc: Yebio Mesfin <ymesfin@ti.com> Signed-off-by: Tom Rini <trini@ti.com>
* | | board: ti: dra7xx: add mux data for UART3Felipe Balbi2014-07-07-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | J6 EVM can be built with UART3 as console, but currently there's nothing muxing UART3 correctly. Likely this only works because, based on commit log, author was only testing with UART3 boot and - I assume - ROM code leave UART3 correctly muxed in that case. If we want to boot from MMC and still use UART3 as console, then we need to mux those signals correctly. Signed-off-by: Felipe Balbi <balbi@ti.com>
* | | build: define CPU only when arch/${ARCH}/cpu/${CPU} existsMasahiro Yamada2014-07-07-60/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The directory arch/${ARCH}/cpu/${CPU} does not exist in avr32, blackfin, microblaze, nios2, openrisc, sandbox, x86. These architectures have only one CPU type. Defining CPU should not be required for such architectures. This commit allows cpu field (= the 3rd field of boards.cfg) to be kept blank. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Simon Glass <sjg@chromium.org> Cc: Sonic Zhang <sonic.zhang@analog.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Thomas Chou <thomas@wytron.com.tw> Cc: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
* | | README: document the CONFIG_ENV_IS_IN_FAT optionWu, Josh2014-07-07-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | In README file, add document for the missing configuration option: CONFIG_ENV_IS_IN_FAT. Signed-off-by: Josh Wu <josh.wu@atmel.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* | | Makefile: drop arch/*/include/asm/proc from make mrproper patternMasahiro Yamada2014-07-07-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 7d89982b stopped creating symbolic link arch/${arch}/include/asm/proc. We do not need to delete it by "make mrproper" any more. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Vasili Galka <vvv444@gmail.com>
* | | ARM: emif4: wait for CM_DLL_READYST to be setJeroen Hofstee2014-07-07-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | The code intends for the CM_DLL_READYST to be set, but actually polls till any bit is set since the logical AND is used instead of the bitwise one is used. Fix it. cc: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
* | | Avoid using gawk-specific strtonum()Simon Glass2014-07-07-1/+2
|/ / | | | | | | | | | | | | | | We need to subtract two hex numbers. Avoid using strtonum() by doing the subtraction in bc with a suitable input base. Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Vasili Galka <vvv444@gmail.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-i2cTom Rini2014-07-07-17/+29
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| * | i2c: tegra: dump alen in debug statementsStephen Warren2014-07-03-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | Since tegra_i2c_{read,write}'s debug() call dumps the chip address, dump the address length (alen) too, so the address value can be correctly interpreted. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Yen Lin <yelin@nvidia.com>
| * | i2c: tegra: write clean data to TX FIFOStephen Warren2014-07-03-5/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Tegra I2C controller's TX FIFO contains 32-bit words. If the final FIFO entry of a transaction contains fewer than 4 bytes, the driver currently fills the unused FIFO bytes with uninitialized data. This can be confusing when reading back the FIFO content for debugging purposes. Solve this by explicitly initializing the variable containing FIFO data before filling it (partially) with data. With this change, send_recv_packets()'s loop's if (is_write) code mirrors the else (i.e. read) branch. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Yen Lin <yelin@nvidia.com>
| * | i2c: tegra: use repeated start for readsStephen Warren2014-07-03-8/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I2C read transactions are typically implemented as follows: START(write) address REPEATED_START(read) data... STOP However, Tegra's I2C driver currently implements reads as follows: START(write) address STOP START(read) data... STOP This sequence confuses at least the AS3722 PMIC on the Jetson TK1 board, leading to corrupted read data in some cases. Fix the driver to chain the transactions together using repeated starts to solve this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Yen Lin <yelin@nvidia.com>
* | | socfpga: Relocate arch common functions away from boardChin Liang See2014-07-05-23/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To move the arch common function away from board folder to arch/arm/cpu/armv7/socfpga folder. Its to avoid code duplication for other non Altera dev kit which is using socfpga device. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Dinh Nguyen <dinguyen@altera.com> Acked-by: Detlev Zundel <dzu@denx.de>
* | | integrator: switch to generic boardLinus Walleij2014-07-05-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Turn on generic board for the integrators, as per the request in the startup message. Everything just works, tested on the Integrator/AP and Integrator/CP. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Simon Glass <sjg@chromium.org>
* | | ARM: rpi_b: enable GENERIC_BOARDStephen Warren2014-07-05-0/+1
| | | | | | | | | | | | | | | | | | | | | Serial port, SD card, and LCD all work. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Acked-by: Simon Glass <sjg@chromium.org>
* | | arm, calimain: Add CONFIG_SYS_GENERIC_BOARDChristian Riesch2014-07-05-1/+2
| | | | | | | | | | | | Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
* | | arm: Fix armv8 compilation errorShaibal.Dutta2014-07-05-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix following compilation error when CONFIG_ARM64 is defined Error: unknown or missing system register name at operand 2 -- `mrs x0,daifmsr daifset,#3' Signed-off-by: Shaibal.Dutta <shaibal.dutta@broadcom.com> Signed-off-by: Darwin Rambo <drambo@broadcom.com> Reviewed-by: Darwin Rambo <drambo@broadcom.com>
* | | arm:board:h2200: Add CONFIG_SYS_GENERIC_BOARDŁukasz Dałek2014-07-05-0/+1
| | | | | | | | | | | | | | | | | | | | | Enable 'generic board init' for H2200 palmtop. Signed-off-by: Lukasz Dalek <luk0104@gmail.com> Acked-by: Marek Vasut <marex@denx.de>
* | | arm: spl: fix include guardJeroen Hofstee2014-07-05-2/+2
| | | | | | | | | | | | | | | cc: Tom Rini <trini@ti.com> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
* | | Reformat boards.cfgAlbert ARIBAUD2014-07-05-10/+10
| | | | | | | | | | | | | | | Run tools/reformat.py -i -d '-' -s 8 to reorder boards as header comments suggest
* | | socfpga: Adding Scan Manager driverChin Liang See2014-07-05-1/+980
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Scan Manager driver will be called to configure the IOCSR scan chain. This configuration will setup the IO buffer settings Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Wolfgang Denk <wd@denx.de> CC: Pavel Machek <pavel@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
* | | socfpga: Adding DesignWare watchdog supportChin Liang See2014-07-05-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To enable the DesignWare watchdog support at SOCFPGA Cyclone V dev kit. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Anatolij Gustschin <agust@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Heiko Schocher <hs@denx.de> Cc: Tom Rini <trini@ti.com>
* | | watchdog/denali: Adding DesignWare watchdog driver supportChin Liang See2014-07-05-0/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To add the DesignWare watchdog driver support. It required information such as register base address and clock info from configuration header file within include/configs folder. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Anatolij Gustschin <agust@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Heiko Schocher <hs@denx.de> Cc: Tom Rini <trini@ti.com>
* | | arm: ep9315: Return back Cirrus Logic EDB9315A board supportSergey Kostanbaev2014-07-04-27/+1636
| | | | | | | | | | | | | | | | | | | | | This patch returns back support for old ep93xx processors family Signed-off-by: Sergey Kostanbaev <sergey.kostanbaev@gmail.com> Cc: albert.u.boot@aribaud.net
* | | gpio: spear_gpio: Fix gpio_set_value() implementationAxel Lin2014-07-04-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In current gpio_set_value() implementation, it always sets the gpio control bit no matter the value argument is 0 or 1. Thus the GPIOs never set to low. This patch fixes this bug. The address bus is used as a mask on read/write operations, so that independent software drivers can set their GPIO bits without affecting any other pins in a single write operation. Thus we don't need a read-modify-write to update the register. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Stefan Roese <sr@denx.de> Reviewed-by: Vipin Kumar <vipin.kumar@st.com> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
* | | ARM: cache_v7: use __weakJeroen Hofstee2014-07-04-55/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is not only more readable but also prevents a warning about a missing prototype. The prototypes which are actually missing are added. cc: Albert Aribaud <albert.u.boot@aribaud.net> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl> Reviewed-by: Tom Rini <trini@ti.com>
* | | ARMv8/ls2085a_emu: Add LS2085A emulator and simulator board supportYork Sun2014-07-04-2/+622
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS2085A is an ARMv8 implementation. This adds board support for emulator and simulator: Two DDR controllers UART2 is used as the console IFC timing is tightened for speedy booting Support DDR3 and DDR4 as separated targets Management Complex (MC) is enabled Support for GIC 500 (based on GICv3 arch) Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com> Signed-off-by: J. German Rivera <German.Rivera@freescale.com> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
* | | armv8/fsl-lsch3: Add support to load and start MC FirmwareJ. German Rivera2014-07-03-3/+383
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adding support to load and start the Layerscape Management Complex (MC) firmware. First, the MC GCR register is set to 0 to reset all cores. MC firmware and DPL images are copied from their location in NOR flash to DDR. MC registers are updated with the location of these images. Deasserting the reset bit of MC GCR register releases core 0 to run. Core 1 will be released by MC firmware. Stop bits are not touched for this step. U-boot waits for MC until it boots up. In case of a failure, device tree is updated accordingly. The MC firmware image uses FIT format. Signed-off-by: J. German Rivera <German.Rivera@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com> Signed-off-by: Shruti Kanetkar <Shruti@Freescale.com>
* | | ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoCYork Sun2014-07-03-4/+944
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
* | | ARMv8: Adjust MMU setupYork Sun2014-07-03-30/+44
| | | | | | | | | | | | | | | | | | | | | Make MMU function reusable. Platform code can setup its own MMU tables. Signed-off-by: York Sun <yorksun@freescale.com> CC: David Feng <fenghua@phytium.com.cn>
* | | Added 64-bit MMIO accessors for ARMv8J. German Rivera2014-07-03-0/+8
| | | | | | | | | | | | | | | | | | | | | This is needed for accessing peripherals with 64-bit MMIO registers, from ARMv8 processors. Signed-off-by: J. German Rivera <German.Rivera@freescale.com>
* | | arm: Add support for semihosting for armv8 fastmodel targets.Darwin Rambo2014-07-03-12/+462
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The armv8 ARM Trusted Firmware (ATF) can be used to load various ATF images and u-boot, and does this for virtual platforms by using semihosting. This commit extends this idea by allowing u-boot to also use semihosting to load the kernel/ramdisk/dtb. This eliminates the need for a bootwrapper and produces a more realistic boot sequence with virtual models. Though the semihosting code is quite generic, support for armv7 in fastmodel is less useful due to the wide range of available silicon and the lack of a free armv7 fastmodel, so this change contains an untested armv7 placeholder for the service trap opcode. Please refer to doc/README.semihosting for a more detailed description of semihosting and how it is used with the armv8 virtual platforms. Signed-off-by: Darwin Rambo <drambo@broadcom.com> Cc: trini@ti.com Cc: fenghua@phytium.com.cn Cc: bhupesh.sharma@freescale.com
* | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-07-02-1078/+4245
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| * \ Merge remote-tracking branch 'u-boot-samsung/master'Albert ARIBAUD2014-07-01-256/+717
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: boards.cfg Conflict was trivial between goni maintainer change and lager_nor removal.
| | * | Samsung: Goni: change maintainer to Robert BaldygaPrzemyslaw Marczak2014-06-30-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Robert Baldyga will now take care of this board. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Robert Baldyga <r.baldyga@samsung.com> Acked-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * | PMIC: MAX77686: fix invalid bus checkJeroen Hofstee2014-06-23-5/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since p->bus is unsigned checking for negative values is optimized away. Since bus is already used as an argument use tmp. While at it, don't declare variables in the middle of a function. cc: Rajeshwari Shinde <rajeshwari.s@samsung.com> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * | Exynos: Split 5250 and 5420 memory bank configurationMichael Pratt2014-06-23-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since snow has a different memory configuration than peach, split the configuration between the 5250 and 5420. Exynos 5420 supports runtime memory configuration detection, and can make the determination between 4 and 7 banks at runtime. Include the bank size with the number of banks for context to make the number of banks meaningful. Signed-off-by: Michael Pratt <mpratt@chromium.org> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * | Exynos5: Config: Enable USB boot mode for all Exynos5 SoCsAkshay Saraswat2014-06-23-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Right now USB booting is enabled for Exynos5250 only. Moving all the configs for USB boot mode from exynos5250-dt.h to exynos5-dt.h in order to enableUSB booting for all Exynos5 SoCs. Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * | Exynos5: Config: Increase SPL footprint for Exynos5420Akshay Saraswat2014-06-23-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Max footprint for SPL in both Exynos 5250 and 5420 is limited to 14 KB. For Exynos5250 we need to keep it 14 KB because BL1 supports only fixed size SPL downloading. But in case of Exynos5420 we need not restrict it to 14 KB. And also, the SPL size for Exynos5420 is expected to increase with the upcoming patches and the patches under review right now. Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * | Exynos5: Config: Place environment at the end of SPI flashAkshay Saraswat2014-06-23-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently environment resides at the location where BL2 ends. This may hold good in case there is an empty space at this position. But what if this place already has a binary or is expected to have one. To avoid such scenarios it is better to save environment at the end of the flash. Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * | Exynos5420: Introduce support for the Peach-Pit boardAkshay Saraswat2014-06-23-133/+362
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While the Exynos5420 chip is used in both Smdk5420 and in the Peach-Pit line of devices, there could be other boards using the same chip, so a common configuration file is being added (exynos5420.h) as well as two common device tree files (exynos54xx.dtsi & exynos5420.dtsi). The peach board as declared in boards.cfg is a copy of smdk5420 declaration. The configuration files are similar, but define different default device trees, console serial ports and prompts. The device tree files for smdk5420 and peach-pit inherit from the same common file. Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * | Exynos5420: Let macros be used for exynos5420Akshay Saraswat2014-06-23-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Macros defined in exynos5_setup.h specific to SMDK5420 are required for Peach-Pit too. Hence, replacing CONFIG_SMDK5420 with CONFIG_EXYNOS5420 to enable these macros for all the boards based on Exynos5420. Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * | Exynos: SPI: Fix reading data from SPI flashAkshay Saraswat2014-06-23-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SPI recieve and transfer code in exynos_spi driver has a logical bug. We read data in a variable which can hold an integer. Then we assign this integer 32 bit value to another variable which has data type uchar. Latter represents a unit of our recieve buffer. Everytime when we write a value to our recieve buffer we step ahead by 4 units when actually we wrote to one unit. This results in the loss of 3 bytes out of every 4 bytes recieved. This patch intends to fix this bug. Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * | trats/trats2: exynos_power_init: return 0 if no battery detected.Przemyslaw Marczak2014-06-19-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Generic board support is now enabled for Exynos 4, and if any init function returns an error then the init process is stopped. This makes a boot issue on the Trats and Trats2 devices. If the device is supplied by USB cable or an external power supply then it can't boot because function exynos_power_init returns an error. Now this function returns 0 if battery is not connected. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Piotr Wilczek <p.wilczek@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
generated by cgit v1.1 at 2024-11-01 04:29:11 +0000