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* x86: Switch to use SMBIOS Kconfig options when writing SMBIOS tablesBin Meng2016-05-23-5/+5
| | | | | | | | Make use of the newly added Kconfig options of board manufacturer and product name to write SMBIOS tables. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: kconfig: Add two options for SMBIOS manufacturer and product nameBin Meng2016-05-23-0/+16
| | | | | | | | This introduces two Kconfig options to be used by SMBIOS tables: board manufacturer and product name. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: galileo: Enable MP table generationBin Meng2016-05-23-0/+1
| | | | | | | | | Now that we have added CPU uclass driver and fixed the IOAPIC ID conflict, enable MP table generation so that IOAPIC can be used by the Linux kernel. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: broadwell: Correct I/O APIC IDBin Meng2016-05-23-1/+2
| | | | | | | | | Currently ID 2 is assgined to broadwell I/O APIC, however per chromebook_samus.dts 2 is the core#2 LAPIC ID. Now we change I/O APIC ID to 4 to avoid conflict. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: quark: Assign a unique I/O APIC IDBin Meng2016-05-23-0/+4
| | | | | | | | | | | | | | | | | | | | | | | After power-on, both LAPIC and I/O APIC appear with the same APIC ID zero, which creates an ID conflict. When generating MP table, U-Boot reports zero as the LAPIC ID in the processor entry, and zero as the I/O APIC ID in the I/O APIC as well as the I/O interrupt assignment entries. Such MP table confuses Linux kernel and finally a kernel panic is seen during boot: BUG: unable to handle kernel paging request at ffff9000 IP: [<c101d462>] native_io_apic_write+0x22/0x30 *pdpt = 00000000014fb001 *pde = 00000000014ff067 *pte = 0000000000000000 Oops: 0002 [#1] Modules linked in: Pid: 1, comm: swapper Tainted: G W 3.8.7 #3 intel galileo/galileo EIP: 0060:[<c101d462>] EFLAGS: 00010086 CPU: 0 EIP is at native_io_apic_write+0x22/0x30 ... Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000009 Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: Call lapic_setup() in interrupt_init()Bin Meng2016-05-23-7/+5
| | | | | | | Let's configure LAPIC in a common place - interrupt_init(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: Remove SMP limitation in lapic_setup()Bin Meng2016-05-23-6/+1
| | | | | | | | | At present LAPIC is enabled and configured as virtual wire mode in lapic_setup() only when CONFIG_SMP is on. This limitation is however not necessary as for uniprocessor this is still needed. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: Don't touch IA32_APIC_BASE MSR on Intel QuarkBin Meng2016-05-23-12/+16
| | | | | | | | | | | Intel Quark processor core provides an integrated Local APIC but does not support the IA32_APIC_BASE MSR. As a result, the Local APIC is always globally enabled and the Local APIC base address is fixed at 0xfee00000. Attempting to access the IA32_APIC_BASE MSR causes a general protection fault. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: galileo: Enable CPU driverBin Meng2016-05-23-0/+14
| | | | | | | Add a cpu node in the device tree and enable CPU driver. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: Use latest microcode for all BayTrail boardsBin Meng2016-05-23-6574/+6
| | | | | | | | | Update board device tree to include latest microcode, and remove the old no longer needed microcode. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
* x86: baytrail: Update to latest microcodeBin Meng2016-05-23-0/+6568
| | | | | | | | Update BayTrail microcde to rev 325 (for CPUID 30673), rev 907 (for CPUID 30679). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: Add some notes for MRC cache with Intel FSPBin Meng2016-05-23-0/+7
| | | | | | | | | MRC cache relies on Intel FSP to produce a special GUID that contains the MRC cache data. Add such information in the CONFIG_ENABLE_MRC_CACHE help entry. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: crownbay: Disable boot stage supportBin Meng2016-05-23-3/+0
| | | | | | | | | | | | | | | It is observed that when enabling boot stage support, occasionally the board reboots during boot over and over again, and eventually boots to shell. This was seen on my board, but not on Jian's board. Debugging shows that the TSC timer calibration against PIT fails as boot stage APIs utilize timer in a very early stage and at that time TSC/PIT may not be stable enough for the calibration to pass. Disable it for now. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Cc: Jian Luo <Jian.Luo4@boschrexroth.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* acpi: Clean IASL generated intermediate filesBin Meng2016-05-23-0/+1
| | | | | | | | | | For boards that support ACPI, there are dsdt.aml, dsdt.asl.tmp and dsdt.c in the board directory after a successful build. These are intermediate files generated by IASL, and should be removed during a 'make clean'. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: doc: Add porting hints for ACPI with WindowsBin Meng2016-05-23-0/+6
| | | | | | | | Windows might cache system information and only detect ACPI changes if you modify the ACPI table versions. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: baytrail: Add GPIO ASL descriptionBin Meng2016-05-23-0/+98
| | | | | | | | | Since BayTrail, Intel starts to use new GPIO IPs in their chipset. This adds the GPIO ASL, so that OS can load corresponding drivers for it. On Linux, this is BayTrail pinctrl driver. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: baytrail: Add internal UART ASL descriptionBin Meng2016-05-23-0/+64
| | | | | | | | | | | | | | | BayTrail integrates an internal ns15550 compatible UART (PNP0501). Its IRQ is hardwired to IRQ3 in old revision chipset, but in newer revision one IRQ4 is being used for ISA compatibility. Handle this correctly in the ASL file. Linux does not need this ASL, but Windows need this to correctly discover a COM port existing in the system so that Windows can show it in the 'Device Manager' window, and expose this COM port to any terminal emulation application. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* acpi: Quieten IASL output when 'make -s' is usedBin Meng2016-05-23-1/+1
| | | | | | | | | IASL compiler does not provide a command line option to turn off its non-warning message. To quieten the output when 'make -s', redirect its output to /dev/null. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: doc: Mention Ubuntu/Windows installation and boot supportBin Meng2016-05-23-4/+8
| | | | | | | | As of now, U-Boot can support installing and booting Ubuntu/Windows with the help of SeaBIOS. Update the documentation. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: baytrail: Enable SeaBIOS on all boardsBin Meng2016-05-23-0/+3
| | | | | | | | | SeaBIOS can be loaded by U-Boot to aid the installation of Ubuntu and Windows to a SATA drive and boot from there. Enable it on all BayTrail boards. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: doc: Update information about IGD with SeaBIOSBin Meng2016-05-23-0/+24
| | | | | | | | Document how to make SeaBIOS load and run the VGA ROM of Intel IGD device when loaded by U-Boot. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: acpi: Remove header length check when writing tablesBin Meng2016-05-23-16/+10
| | | | | | | | | | Before moving 'current' pointer during ACPI table writing, we always check the table length to see if it is larger than the table header. Since our purpose is to generate valid tables, the check logic is always true, which can be avoided. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: acpi: Remove the unnecessary checksum calculation of DSDTBin Meng2016-05-23-6/+0
| | | | | | | | The generated AmlCode[] from IASL already has the calculated DSDT table checksum in place. No need for us to calculate it again. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: acpi: Switch to ACPI mode by ourselves instead of requested by OSPMBin Meng2016-05-23-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Per ACPI spec, during ACPI OS initialization, OSPM can determine that the ACPI hardware registers are owned by SMI (by way of the SCI_EN bit in the PM1_CNT register), in which case the ACPI OS issues the ACPI_ENABLE command to the SMI_CMD port. The SCI_EN bit effectively tracks the ownership of the ACPI hardware registers. However since U-Boot does not support SMI, we report all 3 fields in FADT (SMI_CMD, ACPI_ENABLE, ACPI_DISABLE) as zero, by following the spec who says: these fields are reserved and must be zero on system that does not support System Management mode. U-Boot seems to behave in a correct way that the ACPI spec allows, at least Linux does not complain, but apparently Windows does not think so. During Windows bring up debugging, it is observed that even these 3 fields are zero, Windows are still trying to issue SMI with hardcoded SMI port address and commands, and expecting SCI_EN to be changed by the firmware. Eventually Windows gives us a BSOD (Blue Screen of Death) saying ACPI_BIOS_ERROR and refuses to start. To fix this, turn on the SCI_EN bit by ourselves. With this patch, now U-Boot can install and boot Windows 8.1/10 successfully with the help of SeaBIOS using legacy interface (non-UEFI mode). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: Use high_table_malloc() for tables passing to SeaBIOSBin Meng2016-05-23-3/+1
| | | | | | | | Now that we already reserved high memory for configuration tables, call high_table_malloc() to allocate tables from the region. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: Reserve configuration tables in high memoryBin Meng2016-05-23-3/+8
| | | | | | | When SeaBIOS is on, reserve configuration tables in reserve_arch(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: Unify reserve_arch() for all x86 boardsBin Meng2016-05-23-27/+12
| | | | | | | | Instead of asking each platform to provide reserve_arch(), supply it in arch/x86/cpu/cpu.c in a unified way. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: Prepare configuration tables in dedicated high memory regionBin Meng2016-05-23-0/+68
| | | | | | | | | | Currently when CONFIG_SEABIOS is on, U-Boot allocates configuration tables via normal malloc(). To simplify, use a dedicated memory region which is reserved on the stack before relocation for this purpose. Add functions for reserve and malloc. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: Compile coreboot_table.c only for SeaBIOSBin Meng2016-05-23-1/+1
| | | | | | | coreboot_table.c only needs to be built when SeaBIOS is used. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: Fix up PIRQ routing table checksum earlierBin Meng2016-05-23-4/+4
| | | | | | | | | | | | | | | | PIRQ routing table checksum is fixed up in copy_pirq_routing_table(), which is fine if we only write the configuration table once. But with the SeaBIOS case, when we write the table for the second time, the checksum will be fixed up to zero per the checksum algorithm, which is caused by the checksum field not being zero before fix up, since the checksum has already been calculated in the first run. To fix this, move the checksum fixup to create_pirq_routing_table(), so that copy_pirq_routing_table() only does what its function name suggests: copy the table to somewhere else. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: Call board_final_cleanup() in last_stage_init()Bin Meng2016-05-23-18/+21
| | | | | | | | | | | At present board_final_cleanup() is called before booting a Linux kernel. This actually needs to be done before booting anything, like SeaBIOS, VxWorks or Windows. Move the call to last_stage_init() instead. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: minnowmax: Adjust U-Boot environment address in SPI flashBin Meng2016-05-23-2/+2
| | | | | | | | | | | | | | | Currently U-Boot environment address is at offset 0x7fe00 of a 8MB SPI flash. When creating a partial u-boot.rom image without flash descriptor and ME firmware, U-Boot actually occupies the last 1MB of the flash, and reprograming U-Boot causes previous environment settings get lost which is not convenient during testing. Adjust the environment address to 0x6ef000 instead (before the MRC cache data region in the flash). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* config: sandbox: enable qfw and cmd_qfw for testingMiao Yan2016-05-23-0/+1
| | | | | | | This patch enables qfw and cmd_qfw on sandbox for build coverage test Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: qemu: rename qemu/acpi_table.cMiao Yan2016-05-23-2/+1
| | | | | | | | Rename qemu/acpi_table.c to qemu/e820.c, because ACPI stuff is moved to qfw core, this file only contains code for installing e820 table. Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* cmd: qfw: bring ACPI generation code into qfw coreMiao Yan2016-05-23-209/+206
| | | | | | | | Loading ACPI table from QEMU's fw_cfg interface is not x86 specific (ARM64 may also make use of it). So move the code to common place. Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* cmd: qfw: do not depend on x86Miao Yan2016-05-23-1/+0
| | | | | | | | | The qfw command interface used to depend on X86, this patch removes this restriction so it can be built for sandbox for testing. For normal usage, it can only be used with CONFIG_QEMU. Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* cmd: qfw: do not require default macros when building qfw commandMiao Yan2016-05-23-0/+13
| | | | | | | | | | | The qfw command interface makes use of CONFIG_LOADADDR and CONFIG_RAMDISKADDR to setup kernel. But not all boards have these macros, which causes build problem on those platforms. This patch fixes this issue. Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* cmd: qfw: rename qemu_fw_cfg.[c|h] to qfw.[c|h]Miao Yan2016-05-23-11/+11
| | | | | | | Make file names consistent with CONFIG_QFW and CONFIG_CMD_QFW Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: qemu: add comment about qfw register endiannessMiao Yan2016-05-23-1/+8
| | | | | | | This patch adds some comments about qfw register endianness for clarity. Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: qemu: move x86 specific operations out of qfw coreMiao Yan2016-05-23-24/+60
| | | | | | | | | | | The original implementation of qfw includes several x86 specific operations, like directly calling outb/inb and using some inline assembly code which prevents it being ported to other architectures. This patch adds callback functions and moves those to arch/x86/ Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: qemu: split qfw command interface and qfw coreMiao Yan2016-05-23-177/+200
| | | | | | | | | | | | This patch splits qfw command interface and qfw core function into two files, and introduces a new Kconfig option (CONFIG_QFW) for qfw core. Now when qfw command interface is enabled, it will automatically select qfw core. This patch also makes the ACPI table generation select CONFIG_QFW. Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* cmd: qfw: make fwcfg_present and fwcfg_dma_present publicMiao Yan2016-05-23-17/+23
| | | | | | | | This patch is part of the qfw refactor work. This patch makes qemu_fwcfg_present() and qemu_fwcfg_dma_present() public functions. Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* cmd: qfw: remove qemu_fwcfg_free_files()Miao Yan2016-05-23-15/+11
| | | | | | | | | | | This patch is part of the qfw refactor work. The qemu_fwcfg_free_files() function is only used in error handling in ACPI table generation, let's not make this a core function and move it to the right place. Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* cmd: qfw: add API to iterate firmware listMiao Yan2016-05-23-3/+31
| | | | | | | | This patch is part of the refactor work of qfw. It adds 3 APIs to qfw core to iterate firmware list. Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: qemu: fix ACPI Kconfig optionsMiao Yan2016-05-23-11/+3
| | | | | | | | | | | | | | | CONFIG_GENENRATE_ACPI_TABLE controls the generation of ACPI table which uses U-Boot's built-in methods and CONFIG_QEMU_ACPI_TABLE controls whether to load ACPI table from QEMU's fw_cfg interface. But with commit "697ec431469ce0a4c2fc2c02d8685d907491af84 x86: qemu: Drop our own ACPI implementation", there is only one way to support ACPI table for QEMU targets which is the fw_cfg interface. Having two Kconfig options for this purpose is not necessary any more, so this patch consolidates the two. Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: qemu: Move qfw command over to cmd and add Kconfig entryTom Rini2016-05-23-241/+272
| | | | | | | | | | - Move the command portion of arch/x86/cpu/qemu/fw_cfg.c into cmd/qemu_fw_cfg.c - Move arch/x86/include/asm/fw_cfg.h to include/qemu_fw_cfg.h - Rename ACPI table portion to arch/x86/cpu/qemu/acpi_table.c Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: doc: Document ACPI supportBin Meng2016-05-23-1/+43
| | | | | | | | Remove ACPI from the TODO list and add a new section to document current ACPI support in U-Boot. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: doc: Minor update for accuracyBin Meng2016-05-23-23/+18
| | | | | | | | | | | | | | | | This updates the doc for the following places: - Mention CRB for Bayley Bay - Mention Congatec QEVAL 2.0 & conga-QA3/E3845 - Limit part of the QEMU paragraphs to 80 cols - Correct some typos (drive, it's, Ubuntu) - Add description for "console=ttyS0,115200" - Remove CONFIG_BOOTDELAY description which is already in x86-common.h Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: Remove acpi=off boot parameter when ACPI is onBin Meng2016-05-23-2/+7
| | | | | | | | | | Remove the kernel boot parameter acpi=off so that kernel can turn on ACPI support. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: baytrail: Add .gitignore for ACPI enabled boardsBin Meng2016-05-23-0/+9
| | | | | | | | | Let git ignore dsdt.aml, dsdt.asl.tmp and dsdt.c files. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-11-09 08:03:40 +0000