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| * imx6: centralise common boot options in mx6_common.hPeter Robinson2015-05-26-124/+10
| | | | | | | | | | | | | | Define common LOADADDR and BOOTDELAY to ensure a consistent experience across mx6 boards Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
| * imx6: move MXC_GPIO define to mx6_common.hPeter Robinson2015-05-26-33/+4
| | | | | | | | | | | | Define CONFIG_MXC_GPIO and CONFIG_CMD_GPIO by default in mx6_common Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
| * imx6: move standard ATAG configs to mx6_common.hPeter Robinson2015-05-26-96/+7
| | | | | | | | | | | | | | Define the standard ATAG consfigs in mx6_common. Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Reviewed-by: Tom Rini <trini at konsulko.com>
| * imx6: move generic imx6 options to mx6_common.hPeter Robinson2015-05-26-116/+8
| | | | | | | | | | | | | | | | All boards define CONFIG_MX6, CONFIG_DISPLAY_BOARDINFO, CONFIG_DISPLAY_CPUINFO and CONFIG_SYS_GENERIC_BOARD so define them in mx6_common Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Reviewed-by: Tom Rini <trini at konsulko.com>
| * imx6: move all standard includes to mx6_common.hPeter Robinson2015-05-26-177/+19
| | | | | | | | | | | | | | | | | | | | | | The linux/sizes.h, asm/arch/imx-regs.h, asm/imx-common/gpio.h, config_cmd_default.h includes are used fairly universally across imx6 boards so include them in mx6_common.h by default. We define CONFIG_SYS_NO_FLASH before config_cmd_default.h so that we don't have to undef CONFIG_CMD_FLASH / CONFIG_CMD_IMLS everywhere. Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
| * novena: standardise mx6_common.h includePeter Robinson2015-05-26-1/+1
| | | | | | | | | | | | | | Standardise mx6_common.h to the same as other mx6 boards Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Reviewed-by: Tom Rini <trini at konsulko.com>
| * spl: spl_mmc: fix mmc Falcon mode regressionTim Harvey2015-05-26-1/+1
| | | | | | | | | | | | | | | | | | | | | | 91199f4a5a21a7cf9dd9e7c05e295a042f8c2b7e broke mmc based Falcon mode. The block_read function returns the number of blocks read thus the error check needs to look for a return of 0 blocks read. Cc: Paul Kocialkowski <contact@paulk.fr> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Acked-by: Paul Kocialkowski <contact@paulk.fr>
| * imx: ventana: update README with Falcon mode documentationTim Harvey2015-05-26-0/+169
| | | | | | | | Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * imx: ventana: update README for micro-SD boot mediumTim Harvey2015-05-26-3/+71
| | | | | | | | Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * imx: ventana: update MMC env configurationTim Harvey2015-05-26-2/+3
| | | | | | | | | | | | We will use the same env size and redundancy used for NAND env for MMC. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * thermal: imx_thermal: increase critical temperature thresholdTim Harvey2015-05-26-6/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CPU temperature grade from OTP is now used to define the critical threshold at which point we busyloop until we are below, however this threshold is still too low. Instead of 20C below the max CPU temperature, change it to 5C defined now by TEMPERATURE_HOT_DETLA for clarity. Rename 'passive' to 'critical' as that better defines our use case here. Additionally change the output of the busyloop message to show the max CPU temperature as well as current. Before: CPU Temperature is 101 C, too hot to boot, waiting... CPU Temperature is 101 C, too hot to boot, waiting... After: CPU Temperature (101C) too close to max (105C) waiting... CPU Temperature (101C) too close to max (105C) waiting... Cc: Stefan Roese <sr@denx.de> Cc: Eric Nelson <eric.nelson@boundarydevices.com> Cc: Heiko Schocher <hs@denx.de> Cc: Nikita Kiryanov <nikita@compulab.co.il> Cc: Jon Nettleton <jon.nettleton@gmail.com> Cc: Jason Liu <r64343@freescale.com> Cc: Ye Li <b37916@freescale.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Christian Gmeiner <christian.gmeiner@gmail.com> Cc: Markus Niebel <Markus.Niebel@tq-group.com> Cc: Peng Fan <b51431@freescale.com> Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * arm, imx6: add support for aristainetos2 boardHeiko Schocher2015-05-26-568/+1585
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | add support for imx6dl based aristainetos2 board U-Boot 2015.04-rc5-00066-g60f6ed4 (Apr 10 2015 - 08:46:27) CPU: Freescale i.MX6DL rev1.1 at 792 MHz Reset cause: WDOG Board: aristaitenos2 Watchdog enabled I2C: ready DRAM: 1 GiB NAND: 1024 MiB MMC: FSL_SDHC: 0 SF: Detected N25Q128A with page size 256 Bytes, erase size 64 KiB, total 16 MiB Display: lg4573 (480x800) In: serial Out: serial Err: serial Net: FEC [PRIME] Hit any key to stop autoboot: 0 => Signed-off-by: Heiko Schocher <hs@denx.de>
| * i2c, mxc: rework i2c base address names for different SoCsHeiko Schocher2015-05-26-32/+31
| | | | | | | | | | | | | | rework and unify i2c address names for different SoCs, which use the mxc_i2c driver. Signed-off-by: Heiko Schocher <hs@denx.de>
| * arm, imx6, i2c: add I2C4 for MX6DLHeiko Schocher2015-05-26-12/+32
| | | | | | | | | | | | add I2C4 modul for MX6DL based boards. Signed-off-by: Heiko Schocher <hs@denx.de>
| * imx: dma: correct MXS_DMA_ALIGNMENTPeng Fan2015-05-26-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We should not hardcode MXS_DMA_ALIGNMENT to 32, since we can not guarantee that socs' cache line size is 32 bytes. If on chips whose cache line size is 64 bytes, error occurs: " NAND: ERROR: v7_dcache_inval_range - start address is not aligned - 0xbdf1d1a0 ERROR: v7_dcache_inval_range - stop address is not aligned - 0xbdf1f4a0 ERROR: v7_dcache_inval_range - start address is not aligned - 0xbdf1d1a0 " Align MXS_DMA_ALIGNMENT with ARCH_DMA_MINALIGN whose value is same to CONFIG_SYS_CACHELINE_SIZE if CONFIG_SYS_CACHELINE_SIZE defined. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
| * pwm: imx: Remove unreachable codeAxel Lin2015-05-26-4/+0
| | | | | | | | | | | | | | | | The break after return is unreachable code, remove it. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Stefano Babic <sbabic@denx.de> Acked-by: Heiko Schocher <hs@denx.de>
| * pwm: imx: Prevent NULL pointer dereferenceAxel Lin2015-05-26-0/+12
| | | | | | | | | | | | | | | | | | pwm_id_to_reg() can return NULL, so add NULL testing to prevent NULL pointer dereference. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Stefano Babic <sbabic@denx.de> Acked-by: Heiko Schocher <hs@denx.de>
| * imx: ventana: config: enable Falcon modeTim Harvey2015-05-21-0/+36
| | | | | | | | | | | | Falcon mode entails the SPL booting the OS directly instead of U-Boot. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * wandboard: Switch to SPL supportFabio Estevam2015-05-21-116/+448
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently we need to build one U-boot image for each of the wandboard variants: quad, dual-lite and solo. By switching to SPL we can support all these variants with a single binary, which is very convenient. Based on the work from Richard Hu. Tested kernel booting on the three boards. Signed-off-by: Richard Hu <hakahu@gmail.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Tested-by: Vagrant Cascadian <vagrant@aikidev.net> Reviewed-by: Stefano Babic <sbabic@denx.de>
| * thermal: imx_thermal: use CPU temperature grade for trip pointsTim Harvey2015-05-19-10/+19
| | | | | | | | | | | | | | Replace the hard-coded values for min/max/passive with values derived from the CPU temperature grade. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * imx: mx6: add display of CPU temperature grade in print_cpuinfo()Tim Harvey2015-05-19-4/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When CONFIG_IMX6_THERMAL is defined print the CPU temperature grade info along with the current temperature. Before: CPU: Temperature 42 C After: CPU: Automotive temperature grade (-40C to 125C) at 42C CPU: Industrial temperature grade (-40C to 105C) at 42C CPU: Extended Commercial temperature grade (-20C to 105C) at 42C Cc: Stefan Roese <sr@denx.de> Cc: Eric Nelson <eric.nelson@boundarydevices.com> Cc: Heiko Schocher <hs@denx.de> Cc: Nikita Kiryanov <nikita@compulab.co.il> Cc: Jon Nettleton <jon.nettleton@gmail.com> Cc: Jason Liu <r64343@freescale.com> Cc: Ye Li <b37916@freescale.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Christian Gmeiner <christian.gmeiner@gmail.com> Cc: Markus Niebel <Markus.Niebel@tq-group.com> Cc: Peng Fan <b51431@freescale.com> Tested-by: Nikolay Dimitrov <picmaster@mail.bg> Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * imx: mx6: add get_cpu_temp_grade to obtain cpu temperature grade from OTPTim Harvey2015-05-19-0/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MX6 has a temperature grade defined by OCOTP_MEM0[7:6] which is at 0x480 in the Fusemap Description Table in the reference manual. Return this value as well as min/max temperature based on the value. Note that the IMX6SDLRM and the IMX6SXRM do not indicate this in the their Fusemap Description Table however Freescale has confirmed that these eFUSE bits match the description within the IMX6DQRM and that they will be added to the next revision of the respective reference manuals. This has been tested with IMX6 Automative and Industrial parts. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * imx: mx6: display max cpu frequency in print_cpuinfo()Tim Harvey2015-05-19-1/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Display the max CPU frequency as well as the current running CPU frequency if the max CPU frequency is available and differs from the current CPU frequency. Before: CPU: Freescale i.MX6Q rev1.2 at 792 MHz After - using an 800MHz IMX6DL (running at its max) CPU: Freescale i.MX6DL rev1.1 at 792 MHz After - using a 1GHz IMX6Q (not running at its max): CPU: Freescale i.MX6Q rev1.2 996 MHz (running at 792 MHz) Cc: Stefan Roese <sr@denx.de> Cc: Eric Nelson <eric.nelson@boundarydevices.com> Cc: Heiko Schocher <hs@denx.de> Cc: Nikita Kiryanov <nikita@compulab.co.il> Cc: Jon Nettleton <jon.nettleton@gmail.com> Cc: Jason Liu <r64343@freescale.com> Cc: Ye Li <b37916@freescale.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Christian Gmeiner <christian.gmeiner@gmail.com> Cc: Markus Niebel <Markus.Niebel@tq-group.com> Cc: Peng Fan <b51431@freescale.com> Tested-by: Nikolay Dimitrov <picmaster@mail.bg> Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * imx: mx6: add get_cpu_speed_grade_hz func to return MHz speed grade from OTPTim Harvey2015-05-19-0/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The IMX6 has four different speed grades determined by eFUSE SPEED_GRADING indicated by OCOTP_CFG3[17:16] which is at 0x440 in the Fusemap Description Table. Return this frequency so that it can be used elsewhere. Note that the IMX6SDLRM and the IMX6SXRM do not indicate this in the their Fusemap Description Table however Freescale has confirmed that these eFUSE bits match the description within the IMX6DQRM and that they will be added to the next revision of the respective reference manuals. These have been tested with IMX6 Quad/Solo/Dual-light 800Mhz and 1GHz grades. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * mx6: add OTP bank1 registersTim Harvey2015-05-19-0/+19
| | | | | | | | Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * arm: mx6: ddr: set fast-exit on DDR3 if pd_fast_exit specifiedTim Harvey2015-05-19-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Commit fa8b7d66f49f0c7bd41467fe78f6488d8af6976a introduced fast-exit support to the MMDC however enabling it on the DDR3 got missed. Make sure we enable it on the DDR3 as well. Gateworks uses Micron memory as well as Winbond in MX6. We have found in testing that we need to enable fast-exit for Winbond stability. Gateworks boards are currently the only boards using the MX6 SPL and enabling fast-exit mode. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * arm/imx-common: Fix warning 'get_reset_cause' defined but not usedPrabhakar Kushwaha2015-05-19-0/+2
| | | | | | | | | | | | | | | | | | | | | | Fix below warning arch/arm/imx-common/cpu.c:29:14: warning: ‘get_reset_cause’ defined but not used static char *get_reset_cause(void) Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: Eric Nelson <eric.nelson@boundarydevices.com> Acked-by: Stefano Babic <sbabic@denx.de>
| * pmic: pfuze100 fix typoPeng Fan2015-05-19-3/+3
| | | | | | | | | | | | Change PUZE_100_SW1ABCONF to PFUZE100_SW1ABCONF Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * imx: mx6sx enable SION for i2c pin muxPeng Fan2015-05-19-20/+20
| | | | | | | | | | | | | | | | | | | | | | | | Enable IOMUX_CONFIG_SION for all I2C pin mux settings, otherwise we will get erros when doing i2c operations. error log like the following: " wait_for_sr_state: failed sr=81 cr=a0 state=2020 i2c_init_transfer: failed for chip 0xb retry=1 " Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * imx: marsboard: Enable thermal DM supportNikolay Dimitrov2015-05-19-0/+2
| | | | | | | | Signed-off-by: Nikolay Dimitrov <picmaster@mail.bg>
| * imx: riotboard: Enable thermal DM supportNikolay Dimitrov2015-05-19-0/+2
| | | | | | | | Signed-off-by: Nikolay Dimitrov <picmaster@mail.bg>
| * imx: riotboard, marsboard: Enable thermal supportNikolay Dimitrov2015-05-19-0/+1
| | | | | | | | Signed-off-by: Nikolay Dimitrov <picmaster@mail.bg>
| * hummingboard: Remove unused directoryFabio Estevam2015-05-19-183/+0
| | | | | | | | | | | | | | | | | | | | | | The 'mx6-microsom' directory was only used for the previous mx6solo hummingboard support, which has been removed in favour of the SPL version. Remove the remaining piece of the old mx6solo hummingboard support. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
| * imx: ventana: add pmic_setup to SPLTim Harvey2015-05-19-0/+4
| | | | | | | | | | | | | | We need to do any PMIC setup in the SPL if we are to bypass U-Boot for falcon mode. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * imx: ventana: (cosmetic) clean up size defines for improved readabilityTim Harvey2015-05-19-10/+12
| | | | | | | | | | | | Use the SZ_1M and SZ_1K macros from linuz/sizes.h for improved readability Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * imx: ventana: config: use MMC SPL RAW supportTim Harvey2015-05-19-4/+0
| | | | | | | | | | | | Switch to MMC RAW support for SPL. We will place the uboot.img at 69KB. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * env_nand: use nand_spl_load_image for readenv if SPLTim Harvey2015-05-19-0/+7
| | | | | | | | | | | | | | | | | | | | | | The readenv() implementation of env_nand uses the mtd layer which is unnecessary overhead in SPL when we already have a nand_spl_load_image() function that doesn't need it. Using this instead eliminates the need to provide a mtd_read for SPL env as well as reduces code (4KB savings in IMX6 SPL). Signed-off-by: Tim Harvey <tharvey@gateworks.com> Acked-by: Scott Wood <scottwood@freescale.com>
* | Merge branch 'zynq' of git://www.denx.de/git/u-boot-microblazeTom Rini2015-05-26-101/+52971
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| * | ARM: zynq: add default ps7_init_gpl.c/h for Zed, MicroZed, ZC70xMasahiro Yamada2015-05-25-5/+52919
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Due to licensing issues, the files ps7_init.c/h are not able to be distributed with U-Boot source code. Recent Xilinx tools also provide the GPL variants (ps7_init_gpl.c/h), compatible with U-Boot license. Prior to this commit, we had to copy ps7_init files into board/xilinx/zynq/ before the compile. To be more user-friendly, let's include ps7_init_gpl.c/h for Zedboard, MicroZed, ZC702, ZC706. These init code have been taken from the hwplatform_templates directory of Xilinx SDK 2014.4. You can still use customized ps7_init_gpl.c/h by enabling CONFIG_ZYNQ_CUSTOM_INIT. The recommended directory for storing them is now board/xilinx/zynq/custom_hw_platform, but board/xilinx/zynq is still supported for backward compatibility. The latter emits a warning message to prompt users to gradually switch to the new directory. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | ARM: zynq: add separate configuration for ZC702 and ZC706Masahiro Yamada2015-05-25-13/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Prior to this commit, ZC702 and ZC706 shared the same configuration and were built as follows: ZC702: make zynq_zc70x_defconfig && make ZC706: make zynq_zc70x_defconfig && make DEVICE_TREE=zynq-zc706 This commit introduces separate configuration for them, which makes the next commit much easier. Going forward, the recommended build commands are: ZC702: make zynq_zc702_defconfig && make ZC706: make zynq_zc706_defconfig && make Although the old work flow is still supported, CONFIG_TARGET_ZC70X has been marked as deprecated. If used, the warning message is shown to prompt users to switch to the new scheme. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | zynq: Use system timer implementation instead of ourMichal Simek2015-05-25-83/+6
| | | | | | | | | | | | | | | | | | | | | Don't use error-prone arch timer code and instead use system timer implementation to simplify our code. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | Merge git://git.denx.de/u-boot-nand-flashTom Rini2015-05-24-171/+217
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| * | mtd: vf610_nfc: enable ONFI detectionStefan Agner2015-05-24-18/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This changes enable ONFI detection. The Read ID command now allows one address byte which is needed for ONFI detection. To read the ONFI parameter page, the NAND_CMD_PARAM need to be supported. The CMD code enables one command and one address byte along with reading data from flash using R/B#, as specified by ONFI. Signed-off-by: Stefan Agner <stefan@agner.ch>
| * | mtd: vf610_nfc: add 32-error correction option for HW ECCStefan Agner2015-05-24-5/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add option to choose between current 24-error correction and 32-error correction through Kconfig. 32-error correction allow to use NAND chips which require up to 8-bit error correction per 512 byte (when using 2K pages). Signed-off-by: Stefan Agner <stefan@agner.ch>
| * | mtd: vf610_nfc: add Freescale NFC controller configs to KconfigStefan Agner2015-05-24-23/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit allows users to enable/disable the Freescale NFC controller found in systems like Vybrid (VF610), MPC5125, MCF54418 or Kinetis K70 via Kconfig with more detailed help docs. Signed-off-by: Stefan Agner <stefan@agner.ch> Acked-by: Stefano Babic <sbabic@denx.de> [scottwood: updated vf610twr_nand_defconfig] Signed-off-by: Scott Wood <scottwood@freescale.com>
| * | mtd: vf610_nfc: use in-band bad block tableStefan Agner2015-05-24-27/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Use in-band bad block table (NAND_BBT_NO_OOB) which allows to use the full OOB for hardare ECC purposes. Since there is no ECC correction on the OOB it is also safer to use in-band area to store the bad block table marker. Signed-off-by: Stefan Agner <stefan@agner.ch>
| * | mtd: vf610_nfc: implement OOB only readStefan Agner2015-05-24-59/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement read of OOB area only. When using column and sector size properties, only parts of the page can be read. However, this works only when hardware ECC is disabled, otherwise the ECC engine would ruin the data in the buffer. To allow OOB only reads, three points had to be addressed: - Set ECC mode per command. - Handle NAND_CMD_READOOB seperate. Make sure column and sector size is correctly set up, while disabling ECC. - Now, the OOB data end up at the beginning of the buffer. Remove the special handling of OOB (spareonly). Especially bad block scans benefit from this change. On a 512MiB SLC NAND device, the bad block scan took 1.5s less than before. Signed-off-by: Stefan Agner <stefan@agner.ch>
| * | mtd: vf610_nfc: allow bitflips in an empty pageStefan Agner2015-05-24-1/+1
| | | | | | | | | | | | | | | | | | | | | Allow bit flips in a empty page up to half of the recoverable bits (strength / 2). Signed-off-by: Stefan Agner <stefan@agner.ch>
| * | mtd: vf610_nfc: remove read on SEQINStefan Agner2015-05-24-6/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since we do not support sub-page writes anyway, reading the page back to the controller on SEQIN command is not required. Remove the page read on SEQIN. However, the column/page values relevant to the SEQIN command, hence set the column/row address on SEQIN command. Signed-off-by: Stefan Agner <stefan@agner.ch>
| * | mtd: vf610_nfc: remove caching of page in bufferStefan Agner2015-05-24-10/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To improve performance we remember the current page in the buffer and avoid reading it twice. This implicit page cache increases complexity while does not increase performance in real world cases. This patch removes that feature. Acked-by: Bill Pringlemeir <bpringlemeir@nbsps.com> Signed-off-by: Stefan Agner <stefan@agner.ch>
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