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* x86: Add an SPL implementationSimon Glass2017-02-06-0/+163
| | | | | | | | SPL needs to set up the machine ready for loading 64-bit U-Boot and jumping to it. Call the existing init routines in order to accomplish this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Tidy up use of size_t in relocationSimon Glass2017-02-06-2/+2
| | | | | | | Addresses should not be cast to size_t. Use uintptr_t instead. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add support for 64-bit relocationSimon Glass2017-02-06-0/+45
| | | | | | | | | Add a 64-bit relocation function. SPL loads U-Boot into RAM at a fixed address and runs it. U-Boot then relocates itself to the top of RAM using this relocation function. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Refactor relocation to prepare for 64-bitSimon Glass2017-02-06-24/+31
| | | | | | | | Move the core relocation code into a separate function so that the checking code can be used for 64-bit relocation also. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Do relocation before clearing BSSSimon Glass2017-02-06-1/+1
| | | | | | | | | | | | | The BSS region may overlap with relocations. If we clear BSS we will overwrite the start of the relocation area. This doesn't matter when running from SPI flash, since it is read-only. But when relocating 64-bit U-Boot from one place in RAM to another, relocation will fail because some of its relocations have been zeroed. To fix this, put the ELF fixup call before the BSS clearing call. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: board_r: Set the global data pointer after relocationSimon Glass2017-02-06-0/+10
| | | | | | | | | | | | | | | | | | Since 'gd' is just a normal variable on 64-bit x86, it is relocated by the time we get to board_init_r(). The old 'gd' variable is passed in as parameter to board_init_r(), presumably for this situation. Assign it on 64-bit x86 so that gd points to the correct data. Options to improve this: - Make gd a fixed register and remove the board_init_r() parameter - Make all archs use this board_init_r() parameter The second has a TODO in the code. The first has a TODO in a future commit ('x86: Support global_data on x86_64') Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* board_f/r: Use static const for the init sequencesSimon Glass2017-02-06-3/+3
| | | | | | | | | | These tables should be declared static const. Unfortunately the table in board_r is updated on machines with manual relocation. Update them. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: board_f: Update init sequence for 64-bit startupSimon Glass2017-02-06-3/+7
| | | | | | | | | Adjust the code so that 64-bit startup works. Since we don't need to do CAR changes in U-Boot proper anymore (they are done in SPL) we can simplify the flow and return normally from board_init_f(). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add 64-bit start-up codeSimon Glass2017-02-06-0/+37
| | | | | | | | Add code to start up U-Boot in 64-bit mode. It is fairly simple since we are running from RAM and SPL has done the low-level init. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Allow 32-bit init to move to SPLSimon Glass2017-02-06-2/+2
| | | | | | | | Update the Makefile so that some 32-bit init can be built into SPL rather than U-Boot proper. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Use X86_32BIT_INIT instead of X86_RESET_VECTORSimon Glass2017-02-06-5/+7
| | | | | | | | Use this new option to control the location of 32-bit init. This will allow us to place this in SPL if needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Use X86_16BIT_INIT instead of X86_RESET_VECTORSimon Glass2017-02-06-9/+8
| | | | | | | | Use this new option to control the location of 16-bit init. This will allow us to place this in SPL if needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Kconfig: Add location options for 16/32-bit initSimon Glass2017-02-06-0/+40
| | | | | | | | | | | | | | | | | | At present all 16/32-bit init is controlled by CONFIG_X86_RESET_VECTOR. If this is enabled, then U-Boot is the 'first' boot loader and handles execution from the reset vector through to U-Boot's command prompt. If it is not enabled then U-Boot starts at the 32-bit entry and skips most of its init, assuming that the previous boot loader has done this already. With the move to suport 64-bit operation, we have more cases to consider. The 16-bit and 32-bit init may be in SPL rather than in U-Boot proper. Add Kconfig options which control the location of the 16-bit and the 32-bit init. These are not intended to be user-setting except for experimentation. Their values should be determined by whether 64-bit U-Boot is used. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add Kconfig options to build 64-bit U-BootSimon Glass2017-02-06-0/+46
| | | | | | | | Add a new CONFIG_X86_64 option which will eventually cause U-Boot to be built as a 64-bit application, with SPL doing the 16/32-bit init. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: lib: Fix types and casts for 64-bit compilationSimon Glass2017-02-06-5/+5
| | | | | | | Fix various compiler warnings in the x86 library code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: fsp: Fix cast for 64-bit compilationSimon Glass2017-02-06-2/+2
| | | | | | | Fix a cast in get_next_hob() that causes warnings on 64-bit machines. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: dts: Mark serial as needed before relocationSimon Glass2017-02-06-0/+1
| | | | | | | | We almost always need the serial port before relocation, so mark it as such. This will ensure that it appears in the device tree for SPL, if used. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Fix types for 64-bit compilationSimon Glass2017-02-06-4/+4
| | | | | | | Fix a few types that causes warnings on 64-bit machines. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Add more debugging for failuresSimon Glass2017-02-06-10/+31
| | | | | | | | Add various debug() messages in places where errors occur. This aids with debugging. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Declare global data where it is usedSimon Glass2017-02-06-0/+10
| | | | | | | | Some files are missing this declaration. Add it to avoid build errors when we actually need the declaration. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Update mpspec to build on 64-bit machinesSimon Glass2017-02-06-10/+10
| | | | | | | | | At present this uses u32 to store an address. We should use unsigned long and avoid special types in function return values and parameters unless necessary. This makes the code more portable. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Use unsigned long for address in table generationSimon Glass2017-02-06-36/+29
| | | | | | | | We should use unsigned long rather than u32 for addresses. Update this so that the table-generation code builds correctly on 64-bit machines. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* spl: Don't create a BSS padding when it is separateSimon Glass2017-02-06-1/+2
| | | | | | | | When BSS does not immediate follow the SPL image we don't need padding before the device tree. Remove it in this case. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* spl: Allow PCH drivers to be used in SPLSimon Glass2017-02-06-0/+10
| | | | | | | Add an option for building Platorm Controller Hub drivers in SPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* spl: Allow timer drivers to be used in SPLSimon Glass2017-02-06-0/+10
| | | | | | | Add a new Kconfig option to allow timer drivers to be used in SPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* spl: Allow RTC drivers to be used in SPLSimon Glass2017-02-06-0/+11
| | | | | | | Add a new Kconfig option to allow RTC drivers to be used in SPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* spl: Allow PCI drivers to be used in SPLSimon Glass2017-02-06-0/+10
| | | | | | | Add a new Kconfig option to allow PCI drivers to be used in SPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* spl: Allow CPU drivers to be used in SPLSimon Glass2017-02-06-0/+11
| | | | | | | Add a new Kconfig option to allow CPU drivers to be used in SPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* spl: Makefile: Define SPL_ earlierSimon Glass2017-02-06-0/+6
| | | | | | | | | This Makefile variable can be used in the architecture's main Makefile but at present it is not set up until later. Set it just before this Makefile is included. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* spl: spi: Add a debug message if loading failsSimon Glass2017-02-06-1/+4
| | | | | | | This currently fails silently. Add a debug message to aid debugging. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* console: Don't enable CONFIG-CONSOLE_MUX, etc. in SPLSimon Glass2017-02-06-20/+20
| | | | | | | | | CONFIG_CONSOLE_MUX and CONFIG_SYS_CONSOLE_IS_IN_ENV are not applicable for SPL. Update the console code to use CONFIG_IS_ENABLED(), so that these options will be inactive in SPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Synchronize list of x86 subarchitectures (update bootparam.h)Andy Shevchenko2017-02-06-1/+2
| | | | | | | | Basically rename X86_SUBARCH_MRST to X86_SUBARCH_INTEL_MID to be more specific. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2017-02-03-103/+356
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: configs/ls1046aqds_defconfig configs/ls1046aqds_nand_defconfig configs/ls1046aqds_qspi_defconfig configs/ls1046aqds_sdcard_ifc_defconfig configs/ls1046aqds_sdcard_qspi_defconfig configs/ls1046ardb_emmc_defconfig configs/ls1046ardb_qspi_defconfig configs/ls1046ardb_sdcard_defconfig
| * arch: powerpc: update the eLBC IP input clockPrabhakar Kushwaha2017-02-03-40/+24
| | | | | | | | | | | | | | | | | | | | | | | | eLBC IP clock is always a constant divisor of platform clock pre-defined per SoC. Clock ratio register (LCRR) used in current implementation governs eLBC IP output cloc. Update sys_info->freq_localbus to represent eLBC input clock with value constant divisor of platform clock. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * arch: powerpc: Move CONFIG_FSL_ELBC to KconfigPrabhakar Kushwaha2017-02-03-16/+20
| | | | | | | | | | | | | | Enable ELBC from Kconfig. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * arch: arm: update the IFC IP input clockPrabhakar Kushwaha2017-02-03-24/+5
| | | | | | | | | | | | | | | | | | | | | | | | IFC IP clock is always a constant divisor of platform clock pre-defined per SoC. Clock control register (CCR) used in current implementation governs IFC IP output clock. Update sys_info->freq_localbus to represent IFC input clock with value constant divisor of platform clock. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * arch: powerpc: update the IFC IP input clockPrabhakar Kushwaha2017-02-03-8/+21
| | | | | | | | | | | | | | | | | | | | | | | | IFC IP clock is always a constant divisor of platform clock pre-defined per SoC. Clock control register (CCR) used in current implementation governs IFC IP output clock. Update sys_info->freq_localbus to represent IFC input clock with value constant divisor of platform clock. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * arch: powerpc: Move CONFIG_FSL_IFC to KconfigPrabhakar Kushwaha2017-02-03-13/+17
| | | | | | | | | | | | | | Enable IFC from Kconfig. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls1012a: Add support of PPAPrabhakar Kushwaha2017-02-03-0/+22
| | | | | | | | | | | | | | | | | | | | | | The PPA implements PSCI which requires for power managment. Added support of PPA for LS1012AQDS, LS1012ARDB and LS1012AFRDM. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * board: freescale: ls1012a: Enable secure DDR on LS1012A platformsPrabhakar Kushwaha2017-02-03-0/+91
| | | | | | | | | | | | | | | | | | | | | | PPA binary needs to be relocated on secure DDR, hence marking out a portion of DDR as secure if CONFIG_SYS_MEM_RESERVE_SECURE flag is set Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls1046a: Enable workaround for erratum A-008336York Sun2017-01-31-0/+1
| | | | | | | | | | | | | | Erratum A-008336 applies to LS1046A per latest SoC document. Signed-off-by: York Sun <york.sun@nxp.com> CC: Shengzhou Liu <Shengzhou.Liu@nxp.com>
| * armv7: ls1021aqds: Set cpo_sample for erratum A-009942York Sun2017-01-31-0/+3
| | | | | | | | | | | | | | | | | | Set cpo_sample as suggested by the driver "WARN: pls set popts->cpo_sample = 0x58 in <board>/ddr.c to optimize cpo". Signed-off-by: York Sun <york.sun@nxp.com> CC: Shengzhou Liu <Shengzhou.Liu@nxp.com>
| * drivers: net: fsl-mc: Fixup MAC addresses in DPCBogdan Purcareata2017-01-31-2/+101
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixup port_mac_address property in MC DPC with values from the u-boot environment. Since u-boot already reads the environment MAC addresses when probing the PHYs, use these values. The u-boot environment MAC addresses take precedence over any eventual ones defined in the DPC, except for the case where they are randomly assigned (no u-boot env value declared for port). The patch assumes the "/board_info/ports/" node is present in the DPC. Signed-off-by: Bogdan Purcareata <bogdan.purcareata@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [York S: Fix several indentations] Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls1046a: enable usb in defconfigTang Yuantian2017-01-27-0/+18
| | | | | | | | | | Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls1046a: added usb nodes in dtsTang Yuantian2017-01-27-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | The LS1046A processor has three integrated USB 3.0 controllers (USB1, USB2, and USB3) that allow direct connection to the USB ports with appropriate protection circuitry and power supplies. USB1 and USB2 ports are powered by a NX5P2190UK device, which supplies 5v power at up to 1.2 A. The power enable and power-fault-detect pins are connected to the LS1046A processor via CPLD for individual port management. Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls1046aqds: added usb feature supportTang Yuantian2017-01-27-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | The LS1046AQDS processor has three integrated USB 3.0 controllers (USB1, USB2, and USB3) that allow direct connection to the USB ports with appropriate protection circuitry and power supplies. USB1 and USB2 ports are powered by a NX5P2190UK device, which supplies 5v power at up to 1.2 A. The power enable and power-fault-detect pins are connected to the LS1046A processor via CPLD for individual port management. Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | Merge git://git.denx.de/u-boot-mpc85xxTom Rini2017-02-01-17/+38
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| * | powerpc: mpc5200: Correct return value of memcpy functionMark Marshall2017-02-01-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | The memcpy() function returns a pointer to trg. Signed-off-by: Mark Marshall <Mark.Marshall@omicron.at> Reviewed-by: Thomas Graziadei <thomas.graziadei@omicronenergy.com> Reviewed-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: York Sun <york.sun@nxp.com>
| * | powerpc: mpc85xx: Use symbolic names for cache control bitsMark Marshall2017-01-31-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | We should use the symbolic names for the cache control bits. Signed-off-by: Mark Marshall <Mark.Marshall@omicron.at> Reviewed-by: Thomas Graziadei <thomas.graziadei@omicronenergy.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | powerpc: mpc83xx: Enable pre-relocation mallocmario.six@gdsys.cc2017-01-31-7/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | To enable DM on MPC83xx, we need pre-relocation malloc, which is implemented in this patch. Signed-off-by: Mario Six <mario.six@gdsys.cc> [York S: Fixed compiling warning for unused variable 'i'] Reviewed-by: York Sun <york.sun@nxp.com>
generated by cgit v1.1 at 2024-09-19 14:53:25 +0000