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* bootm: Add subcommandsKumar Gala2008-10-29-2/+219
| | | | | | | | | | | | | | Add the ability to break the steps of the bootm command into several subcommands: start, loados, ramdisk, fdt, bdt, cmdline, prep, go. This allows us to do things like manipulate device trees before they are passed to a booting kernel or setup memory for a secondary core in multicore situations. Not all OS types support all subcommands (currently only start, loados, ramdisk, fdt, and go are supported). Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* bootm: Move to using a function pointer table for the boot os functionKumar Gala2008-10-29-37/+31
| | | | | | | | This removes a bit of code and makes it easier for the upcoming sub bootm command support to call into the proper OS specific handler. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Wolfgang Denk <wd@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-videoWolfgang Denk2008-10-28-85/+195
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| * lcd: Let the board code show board-specific infoHaavard Skinnemoen2008-10-27-79/+178
| | | | | | | | | | | | | | | | | | | | | | | | | | The information displayed when CONFIG_LCD_INFO is set is inherently board-specific, so it should be done by the board code. The current code dealing with this only handles two cases, and is already a horrible mess of #ifdeffery. Yes, this duplicates some code, but it also allows boards to print more board-specific information; this used to be very difficult. Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> Signed-off-by: Anatolij Gustschin <agust@denx.de>
| * lcd: Set lcd_is_enabled before clearing the screenHaavard Skinnemoen2008-10-25-1/+1
| | | | | | | | | | | | | | | | This allows the logo/info rendering routines to use the regular lcd_putc/lcd_puts/lcd_printf calls. Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> Signed-off-by: Anatolij Gustschin <agust@denx.de>
| * lcd: Implement lcd_printf()Haavard Skinnemoen2008-10-25-0/+14
| | | | | | | | | | | | | | | | | | lcd_printf() has a prototype in include/lcd.h but no implementation. Fix this by borrowing the lcd_printf() implementation from the cogent board code (which appears to use its own LCD framework.) Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> Signed-off-by: Anatolij Gustschin <agust@denx.de>
| * atmel_lcdfb: Straighten out funky vl_sync logicHaavard Skinnemoen2008-10-25-4/+1
| | | | | | | | | | | | | | | | If the board _didn't_ request INVLINE_INVERTED, we set INVLINE_INVERTED, otherwise we don't. WTF? Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> Signed-off-by: Anatolij Gustschin <agust@denx.de>
| * atmel_lcdfb: Eliminate unneeded #include <asm/arch/hardware.h>Haavard Skinnemoen2008-10-25-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | atmel_lcdfb doesn't actually need anything from asm/arch/hardware.h. It includes a file that does, asm/arch/gpio.h, but this file doesn't include <asm/arch/hardware.h> like it's supposed to. Add the missing include to asm/arch/gpio.h and remove the workaround from the atmel_lcdfb driver. This makes the driver compile on avr32. Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> Signed-off-by: Anatolij Gustschin <agust@denx.de>
* | i386: Renamed show_boot_progress in assembler codeGraeme Russ2008-10-28-14/+14
| | | | | | | | | | | | | | Renamed show_boot_progress in assembler init phase to show_boot_progress_asm to avoid link conflicts with C version Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
* | Merge branch 'denx'Andy Fleming2008-10-27-1/+922
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| * \ Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2008-10-27-687/+624
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| * | | ppc4xx: New board avnet fx12 minimodulGeorg Schardt2008-10-24-0/+252
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the avnet fx12 minimodul. It needs the "ppc4xx: Generic architecture for xilinx ppc405" patch from Ricardo. Signed-off-by: Georg Schardt <schardt@team-ctech.de> Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es> Signed-off-by: Stefan Roese <sr@denx.de>
| * | | ppc4xx: Generic architecture for xilinx ppc405(v3)Ricardo Ribalda Delgado2008-10-24-1/+663
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As "ppc44x: Unification of virtex5 pp440 boards" did for the xilinx ppc440 boards, this patch presents a common architecture for all the xilinx ppc405 boards. Any custom xilinx ppc405 board can be added very easily with no code duplicity. This patch also adds a simple generic board, that can be used on almost any design with xilinx ppc405 replacing the file ppc405-generic/xparameters.h This patch is prepared to work with the latest version of EDK (10.1) Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es> Signed-off-by: Stefan Roese <sr@denx.de>
| * | | ppc4xx: Disable DDR2 autocalibration on Kilauea for nowStefan Roese2008-10-24-0/+7
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | Since the new autocalibration still has some problems on some Kilauea boards with 200MHz DDR2 frequency we disable the autocalibration and use the hardcoded values as done before. This seems to work reliably on all known DDR2 frequencies. After the autocalibration issue is fixed we will enable it again. Signed-off-by: Stefan Roese <sr@denx.de>
* | | 85xx: Update MPC85xx_PORDEVSR_IO_SEL maskPeter Tyser2008-10-27-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | The MPC8572 has a 4-bit wide PORDEVSR IO_SEL field. Other MPC85xx processors have a 3-bit wide IO_SEL field but have the most significant bit is wired to 0 so this change should not affect them. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* | | powerpc: fix pci window initialization to work with > 4GB DRAMBecky Bruce2008-10-27-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | The existing code has a few errors that need to be fixed in order to support large RAM sizes. Fix those, and add a comment to make it clearer. Signed-off-by: Becky Bruce <becky.bruce@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org>
* | | pci/fsl_pci_init: Removed a bunch pointless trailing backslashes.Kumar Gala2008-10-27-7/+7
| |/ |/| | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | 86xx: Convert all fsl_pci_init users to new APIsKumar Gala2008-10-24-142/+59
| | | | | | | | | | | | | | | | | | | | | | | | Converted MPC8610HCPD, MPC8641HPCN, and SBC8641D to use fsl_pci_setup_inbound_windows() and ft_fsl_pci_setup(). With these changes the board code is a bit smaller and we get dma-ranges set in the device tree for these boards. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com> Acked-by: Jon Loeliger <jdl@freescale.com>
* | 85xx: Convert all fsl_pci_init users to new APIsKumar Gala2008-10-24-445/+200
| | | | | | | | | | | | | | | | | | | | | | | | Converted ATUM8548, MPC8536DS, MPC8544DS, MPC8548CDS, MPC8568MDS, MPC8572DS, TQM85xx, and SBC8548 to use fsl_pci_setup_inbound_windows() and ft_fsl_pci_setup(). With these changes the board code is a bit smaller and we get dma-ranges set in the device tree for these boards. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
* | pci/fsl_pci_init: Added fdt helper for setting up bus-ranges & dma-rangesKumar Gala2008-10-24-0/+20
| | | | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
* | pci/fsl_pci_init: Add a common PCI inbound setup functionKumar Gala2008-10-24-0/+81
| | | | | | | | | | | | | | | | Add a common setup function that determines the pci_region(s) based on how much memory we have in the system. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
* | pci/fsl_pci_init: Enable larger address and setting inbound windows properlyKumar Gala2008-10-24-14/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * PCI Inbound window was setup incorrectly. The PCI address and system address were swapped. The PCI address should be setting piwar/piwbear and the system address should be setting pitar. * Removed masking of addresses to allow for system address to support system address & PCI address >32-bits * Set PIWBEAR & POTEAR to allow for full 64-bit PCI addresses * Respect the PCI_REGION_PREFETCH for inbound windows Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
* | fdt: Added helper to set PCI dma-ranges propertyKumar Gala2008-10-24-0/+74
| | | | | | | | | | | | | | | | | | | | | | Added fdt_pci_dma_ranges() that parses the pci_region info from the struct pci_controller and populates the dma-ranges based on it. The max # of windws/dma-ranges we support is 3 since on embedded PowerPC based systems this is the max number of windows. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
* | fdt: Add fdt_getprop_u32_default helpersKumar Gala2008-10-24-0/+29
| | | | | | | | | | | | | | | | | | Add helper functions to return find a node and return it's property or a default value. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com> Acked-by: Gerald Van Baren <vanbaren@cideas.com>
* | 86xx: Enable 64-bit PCI resources on all Freescale boardsKumar Gala2008-10-24-0/+2
| | | | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
* | 85xx: Enable 64-bit PCI resources on all Freescale boardsKumar Gala2008-10-24-0/+9
| | | | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
* | pci: Allow for PCI addresses to be 64-bitKumar Gala2008-10-24-63/+102
| | | | | | | | | | | | | | | | | | | | PCI bus is inherently 64-bit. While not all system require access to the full 64-bit PCI address range some do. This allows those systems to enable the full PCI address width via CONFIG_SYS_PCI_64BIT. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com> Acked-by: Wolfgang Denk <wd@denx.de>
* | 85xx: Fix the incorrect register used for DDR erratum1Dave Liu2008-10-24-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 8572 DDR erratum1: DDR controller may enter an illegal state when operating in 32-bit bus mode with 4-beat bursts. Description: When operating with a 32-bit bus, it is recommended that DDR_SDRAM_CFG[8_BE] is cleared when DDR2 memories are used. This forces the DDR controller to use 4-beat bursts when communicating to the DRAMs. However, an issue exists that could lead to data corruption when the DDR controller is in 32-bit bus mode while using 4-beat bursts. Projected Impact: If the DDR controller is operating in 32-bit bus mode with 4-beat bursts, then the controller may enter into a bad state. All subsequent reads from memory is corrupted. Four-beat bursts with a 32-bit bus only is used with DDR2 memories. Therefore, this erratum does not affect DDR3 mode. Work Arounds: To work around this issue, software must set DEBUG_1[31] in DDR memory mapped space (CCSRBAR offset + 0x2f00 for DDR_1 and CCSRBAR offset + 0x6f00 for DDR_2). Currenlty, the code is using incorrect register DDR_SDRAM_CFG_2 as condition, but it should be DDR_SDRAM_CFG register. Signed-off-by: Dave Liu <daveliu@freescale.com>
* | 85xx: remove unused config definitionDave Liu2008-10-24-18/+0
| | | | | | | | Signed-off-by: Dave Liu <daveliu@freescale.com>
* | 85xx: Add basic e500mc core supportKumar Gala2008-10-24-0/+16
| | | | | | | | | | | | | | | | | | | | | | Introduce CONFIG_E500MC to deal with the minor differences between e500v2 and e500mc. * Certain fields of HID0/1 don't exist anymore on e500mc * Cache line size is 64-bytes on e500mc * reset value of PIR is different Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | 85xx: Use CONFIG_SYS_CACHELINE_SIZE instead of magic numberKumar Gala2008-10-24-2/+2
|/ | | | | | | Using CONFIG_SYS_CACHELINE_SIZE instead of 31 means we can handle e500mc's 64-byte cacheline properly when it gets added. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Fix strmhz(): avoid printing negative fractionsWolfgang Denk2008-10-22-1/+1
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* mpc83xx: Removed #ifdef CONFIG_MPC834X dependency on upmconfig functionRichard Retanubun2008-10-21-5/+0
| | | | | | | | This is done to allow other 83XX based platforms which also have UPM (e.g. 8360) to configure and use their UPM in u-boot. Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: add support for switching between USB Host/Function for MPC837XEMDSAnton Vorontsov2008-10-21-4/+4
| | | | | | | | | | With this patch u-boot can fixup the dr_mode and phy_type properties for the Dual-Role USB controller. While at it, also remove #ifdefs around includes, they are not needed. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: add ELBC NAND support for the MPC837XEMDS boardsAnton Vorontsov2008-10-21-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Though NAND chip is replaceable on the MPC837XE-MDS boards, the current settings don't work with the default chip on the board. Nevertheless Freescale's U-Boot sets the option register correctly, so I just dumped the register from the working u-boot. My guess is that the old settings were applicable for some pilot boards, not found in the production. This patch also enables FSL ELBC driver so that we could access the NAND storage in the u-boot. The NAND support costs about 45KB, so the u-boot no longer fits into two 128KB NOR flash sectors, thus we also have to adjust environment location: add another 128KB to the monitor length. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> It is due to hardware design and logic defect, that is the I/O[0:7] of NAND chip is connected to LAD[7:0], so when the NAND chip connected to nLCS3, you have to set up the OR3[BCTLD] = '1' for normal operation, otherwise it will have bus contention due to the pin 48/25 of U60 is enabled. Setup the OR3[BCTLD] = '1' , that meaning the LBCTL is not asserted upon access to the NAND chip, keep the default state. Acked-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: fix PCI scan hang on the standalone MPC837xE-MDS boardsAnton Vorontsov2008-10-21-0/+47
| | | | | | | | | | | | | | | | | | | | | | | The MPC837xE-MDS board's CPLD can auto-detect if the board is on the PIB, standalone or acting as a PCI agent. User's Guide says: - When the CPLD recognizes its location on the PIB it automatically configures RCW to the PCI Host. - If the CPLD fails to recognize its location then it is automatically configured as an Agent and the PCI is configured to an external arbiter. This sounds good. Though in the standalone setup the CPLD sets PCI_HOST flag (it's ok, we can't act as PCI agents since we receive CLKIN, not PCICLK), but the CPLD doesn't set the ARBITER_ENABLE flag, and without any arbiter bad things will happen (here the board hangs during any config space reads). In this situation we must disable the PCI. And in case of anybody really want to use an external arbiter, we provide "pci_external_aribter" environment variable. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: add SGMII riser module support for the MPC8378E-MDS boardsAnton Vorontsov2008-10-21-0/+125
| | | | | | | | | | This involves configuring the SerDes and fixing up the flags and PHY addresses for the TSECs. For Linux we also fix up the device tree. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: add TSECs' HRCWH masks for MPC837x processorsAnton Vorontsov2008-10-21-0/+2
| | | | | | | We'll use these masks to parse TSEC modes out of HRCWH. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: serdes: add forgotten shifts for rfcksAnton Vorontsov2008-10-21-6/+6
| | | | | | | | | | The rfcks should be shifted by 28 bits left. We didn't notice the bug because we were using only 100MHz clocks (for which rfcks == 0). Though, for SGMII we'll need 125MHz clocks. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: fix serdes setup for the MPC8378E boardsAnton Vorontsov2008-10-21-2/+2
| | | | | | | | | | | | | | | | | | | | | | MPC837xE specs says that SerDes1 has: — Two lanes running x1 SGMII at 1.25 Gbps; — Two lanes running x1 SATA at 1.5 or 3.0 Gbps. And for SerDes2: — Two lanes running x1 PCI Express at 2.5 Gbps; — One lane running x2 PCI Express at 2.5 Gbps; — Two lanes running x1 SATA at 1.5 or 3.0 Gbps. The spec also explicitly states that PEX options are not valid for the SD1. Nevertheless MPC8378 RDB and MDS boards configure the SD1 for PEX, which is wrong to do. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: mpc8360emds: rework LBC SDRAM setupAnton Vorontsov2008-10-21-26/+38
| | | | | | | | | | | | | | | | | | | Currently 64M of LBC SDRAM are mapped at 0xF0000000 which makes it difficult to use (b/c then the memory is discontinuous and there is quite big memory hole between the DDR/SDRAM regions). This patch reworks LBC SDRAM setup so that now we dynamically place the LBC SDRAM near the DDR (or at 0x0 if there isn't any DDR memory). With this patch we're able to: - Boot without external DDR memory; - Use most "DDR + SDRAM" setups without need to support for sparse/discontinuous memory model in the software. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* FDT: don't use private kernel header filesWolfgang Denk2008-10-21-14/+25
| | | | | | | | | | | | | | On some systems (for example Fedora Core 4) U-Boot builds with the following wanrings only: ... In file included from /home/wd/git/u-boot/include/libfdt_env.h:33, from fdt.c:51: /usr/include/asm/byteorder.h:6:2: warning: #warning using private kernel header; include <endian.h> instead! This patch fixes this problem. Signed-off-by: Wolfgang Denk <wd@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk2008-10-21-330/+1368
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| * ppc4xx: Add 1.0 & 1.066 GHz to canyonlands bootstrap command for PLL setupStefan Roese2008-10-21-0/+12
| | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Correctly setup ranges property in ebc nodeStefan Roese2008-10-21-17/+59
| | | | | | | | | | | | | | | | Previously only the NOR flash mapping was written into the ranges property of the ebc node. This patch now writes all enabled chip select areas into the ranges property. Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Add GDSys neo 405EP board supportDirk Eibach2008-10-21-0/+547
| | | | | | | | | | Signed-off-by: Dirk Eibach <eibach@gdsys.de> Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Update configs for Netstal boardsNiklaus Giger2008-10-21-275/+292
| | | | | | | | | | | | | | | | | | | | I reorganized my config files, putting the common stuff into netstal-common.h (got the idea by looking a amcc-common.h from Stefan). Added stuff to boot the new powerpc linux via NFS (only tested with HCU4). Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Add routine to retrieve CPU numberAdam Graham2008-10-21-1/+21
| | | | | | | | | | | | | | | | | | | | | | | | Provide a weak defined routine to retrieve the CPU number for reference boards that have multiple CPU's. Default behavior is the existing single CPU print output. Reference boards with multiple CPU's need to provide a board specific routine. See board/amcc/arches/arches.c for an example. Signed-off-by: Adam Graham <agraham@amcc.com> Signed-off-by: Victor Gallardo <vgallardo@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Add static support for 44x IBM SDRAM ControllerAdam Graham2008-10-21-18/+53
| | | | | | | | | | | | | | | | | | | | This patch add the capability to configure a PPC440 based IBM SDRAM Controller with static, compiled-in, values. PPC440 memory subsystem includes a Memory Queue core. Signed-off-by: Adam Graham <agraham@amcc.com> Signed-off-by: Victor Gallardo <vgallardo@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Add AMCC Arches board support (dual 460GT)Adam Graham2008-10-21-19/+384
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The Arches Evaluation board is based on the AMCC 460GT SoC chip. This board is a dual processor board with each processor providing independent resources for Rapid IO, Gigabit Ethernet, and serial communications. Each 460GT has it's own 512MB DDR2 memory, 32MB NOR FLASH, UART, EEPROM and temperature sensor, along with a shared debug port. The two 460GT's will communicate with each other via shared memory, Gigabit Ethernet and x1 PCI-Express. Signed-off-by: Adam Graham <agraham@amcc.com> Signed-off-by: Victor Gallardo <vgallardo@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
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