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| * imx: mx6: fix mmdc ch0 clk for 6SLPeng Fan2016-12-16-0/+5
| | | | | | | | | | | | | | | | | | | | >From RM, per_periph2_clk_sel option3 is: "derive clock from 198MHz clock (divided 392MHz PLL2 PFD)." So fix it. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
| * imx: mx6sll: add iomux settingsPeng Fan2016-12-16-5/+11
| | | | | | | | | | | | | | | | Add iomux settings for i.MX6 SLL Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye.Li <ye.li@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
| * imx-common: timer: add i.MX6SLL supportPeng Fan2016-12-16-3/+7
| | | | | | | | | | | | | | Add i.MX6 SLL GPT timer support. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
| * imx: mx6sll: update register addressPeng Fan2016-12-16-27/+50
| | | | | | | | | | | | | | Update register address for i.MX6 SLL Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
| * imx: mx6sll: add pinmux header filesPeng Fan2016-12-16-0/+1021
| | | | | | | | | | | | | | Add i.MX6SLL pinmux header files Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
| * imx: add i.MX 6SLL CPU typePeng Fan2016-12-16-1/+5
| | | | | | | | | | | | | | | | Add i.MX6SLL cpu type. MXC_CPU_MX6D is not a real value in chip, so change it to 0x6A. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
| * configs: colibri_vf: Add fdt_fixup environment variableSanchayan Maity2016-12-16-3/+4
| | | | | | | | | | | | | | | | u-boot allows modifying a device tree after it is loaded into memory. Add fdt_fixup hook in u-boot environment which can facilitate such modifications. Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
| * board/liteboard: Add support for liteBoardMarcin Niestroj2016-12-16-0/+547
| | | | | | | | | | | | | | | | | | | | | | | | liteBoard is a development board which uses liteSOM as its base. Hardware specification: * liteSOM (i.MX6UL, DRAM, eMMC) * Ethernet PHY (id 0) * USB host (usb_otg1) * MicroSD slot (uSDHC1) Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
| * ARM: imx6ul: Add support for liteSOMMarcin Niestroj2016-12-16-0/+231
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | liteSOM is a System On Module (http://grinn-global.com/litesom/). It can't exists on its own, but will be used as part of other boards. Hardware specification: * NXP i.MX6UL processor * 256M or 512M DDR3 memory * optional eMMC (uSDHC2) Here we treat SOM similar to SOC, so we place it inside arch/arm/mach-* directory and make it possible to reuse initialization code (i.e. DDR, eMMC init) for all boards that use it. Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
| * udoo_neo: Add Ethernet supportBreno Lima2016-12-16-2/+112
| | | | | | | | | | | | | | | | UDOO Neo boards has one FEC port connected to KSZ8091, add support for it. Tested on a UDOO Neo Full with "dhcp zImage" command. Signed-off-by: Breno Lima <breno.lima@nxp.com>
| * udoo_neo: Add PFUZE300 PMIC supportBreno Lima2016-12-16-0/+156
| | | | | | | | | | | | | | | | UDOO Neo boards has a PFUZE300 connected to I2C1 bus. Tested on a UDOO Neo Full with "pmic PFUZE3000 dump" command. Signed-off-by: Breno Lima <breno.lima@nxp.com>
| * power: pmic: Add Voltage configuration macroBreno Lima2016-12-16-0/+5
| | | | | | | | | | | | | | Add pfuze3000 voltage configuration macro for SW1AB, SW3 and VLDO1/2 according to tables 53, 57 and 62 on PF3000 datasheet. Signed-off-by: Breno Lima <breno.lima@nxp.com>
| * udoo_neo: Add thermal supportBreno Lima2016-12-16-0/+4
| | | | | | | | | | | | | | Add thermal support on the Kconfig file. Signed-off-by: Breno Lima <breno.lima@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
| * udoo_neo: Remove console optionBreno Lima2016-12-16-1/+0
| | | | | | | | | | | | | | It's not necessary to define the console option as we use the distro config. Signed-off-by: Breno Lima <breno.lima@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
| * udoo_neo: Remove mmcautodetect optionBreno Lima2016-12-16-1/+0
| | | | | | | | | | | | | | It's not necessary to define the mmcautodetect as it is not used anywhere. Signed-off-by: Breno Lima <breno.lima@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
| * udoo_neo: Staticize board_string()Breno Lima2016-12-16-1/+1
| | | | | | | | | | | | | | Change board_string() function to static because it's being used locally. Signed-off-by: Breno Lima <breno.lima@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
| * udoo_neo: Move MX6SX configuration to KconfigBreno Lima2016-12-16-1/+2
| | | | | | | | | | | | | | | | | | It's not necessary to define the processor in the defconfig file. The preferred method to select the SoC is via Kconfig file. Signed-off-by: Breno Lima <breno.lima@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
| * udoo_neo: Remove USDHC3 supportBreno Lima2016-12-16-89/+6
| | | | | | | | | | | | | | | | It's not necessary to support USDHC3 in U-Boot as it's being used for the WLAN. Signed-off-by: Breno Lima <breno.lima@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
| * arm: imx: initial support for colibri imx6Max Krummenacher2016-12-16-0/+2449
| | | | | | | | | | | | | | | | This adds board support for the Toradex module family Colibri iMX6. The familiy consists of a module with i.MX6 DualLite, i.MX6 Solo, both with a version for commercial and industrial temperature range. Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
| * arm: imx: initial support for apalis imx6Max Krummenacher2016-12-16-0/+2691
| | | | | | | | | | | | | | | | This adds board support for the Toradex module family Apalis iMX6. The familiy consists of a module with i.MX6 Dual, i.MX6 Quad with commercial and industrial temperature range. Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
| * ARM: dts: vf: Fix warning about missing reg propertyStefan Agner2016-12-16-0/+2
| | | | | | | | | | | | | | | | | | Add proper reg values for the two AIPS bus nodes. This avoids this two warnings: Node /soc/aips-bus@40000000 has a unit name, but no reg property Node /soc/aips-bus@40080000 has a unit name, but no reg property Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
| * colibri_vf: use same NAND clock as Linux usesStefan Agner2016-12-16-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently a divider of 6 has been used, leading to following NAND Flash Controller (NFC) clocks: VF61: 27.7 MHz (166.7MHz bus clock) VF50: 22 MHz (132MHz bus clock) The NAND Flash Memory used on VF50 allows to use clock speed of up to 33MHz, while the Flash Memory of VF61 allows 50MHz. We can use the same divider of 4 on both modules to configure the maximal possible clock speeds: VF61: 41.7 MHz VF50: 33 MHz Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
| * colibri_vf: cleanup USB clock initializationStefan Agner2016-12-16-4/+10
| | | | | | | | | | | | | | | | | | Use the same preprocessor define to enable clocks as we use to enable the driver. Make sure that the necessary PLL's are on (they get enabled by boot ROM by default, so this is more for completness). Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
| * colibri_vf: use device-tree for MTD partitionsStefan Agner2016-12-16-0/+13
| | | | | | | | | | | | | | | | Use device-tree fixup to communicate the MTD partitions to the kernel. U-Boot's mtdparts environment variable will be used as partition source for the device-tree based partition table too. Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
| * toradex: allow custom fdt board setup in board fileStefan Agner2016-12-16-5/+53
| | | | | | | | | | | | | | | | | | | | The config block support currently uses the ft_board_setup function to patch the device tree with config block information. However, this does not allow to patch the device tree with board specific information. Rename the common setup function to ft_common_board_setup and use the call it from the board files directly. Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
| * toradex: fix USB Download gadget fixup callbackStefan Agner2016-12-16-2/+2
| | | | | | | | | | | | | | Use the proper config option to guard the USB Download Function fixup callback. Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
| * Merge branch 'master' of git://git.denx.de/u-bootStefano Babic2016-12-16-3765/+9059
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| * | Revert "ARM: mx6: add MMC2 boot device detection support in SPL"Breno Lima2016-12-05-5/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 54e4fcfa3c749a78 ("ARM: mx6: add MMC2 boot device detection support in SPL") prevents UDOO neo board to boot: Trying to boot from MMC2 port 1 MMC Device 1 not found spl: could not find mmc device. error: -19 SPL: failed to boot from all boot devices This reverts commit 54e4fcfa3c749a789192e83740a53234182f4ca3. Signed-off-by: Breno Lima <breno.lima@nxp.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2016-12-16-176/+95
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| * | | Revert "sf: Fix quad bit set for micron devices"Cyrille Pitchen2016-12-15-63/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit c56ae7519f141523ba1248b22b5b5169b21772fe. Once the 'Quad Enable' bit is cleared in their Enhanced Volatile Configuration Register (EVCR), Micron memories expect ALL commands to use the SPI 4-4-4 protocol. Commands using SPI 1-y-z protocols are no longer accepted. Within the reverted commit, the write_evcr() function is implemented using the spi_flash_write_common(), which is a shortcut for the [ spi_flash_cmd_write_enable(), spi_flash_cmd_write(), spi_flash_cmd_wait_ready() ] sequence. Since the internal state of the Micron memory has been changed when the spi_flash_cmd_write() function completes, the later call of the spi_flash_cmd_wait_ready() function fails. Indeed the SPI controller driver is not aware of the SPI protocol switch. Further patches will fix the support of Micron QSPI memories. Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> [Rebase on master, use JEDEC_MFR(info) in place of idcode0] Signed-off-by: Jagan Teki <jagan@openedev.com>
| * | | sf: Do not force the DT memory map size to exactly match the devicePhil Edworthy2016-12-15-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As long as the memory mapped size specifeid in the DT is the same or bigger than the device size, it will work. So do not force the sizes to be identical. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * | | mtd: spi: don't return -1 when scan succeedFabien Parent2016-12-15-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In spi_flash_scan, 'ret' is initialled to -1, but 'ret' is not always used to store a return value, in that case, even when the function succeed, an error (-1) will be returned. Lets just return 0 if we hit the end of the function. Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * | | spi: cadence_qspi: Move DT prop code to match layoutPhil Edworthy2016-12-15-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the code to read the "sram-size" property into the other code that reads properties from the node, rather than the SF subnode. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * | | spi: cadence_qspi: Fix CS timingsPhil Edworthy2016-12-15-11/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Cadence QSPI controller has specified overheads for the various CS times that are in addition to those programmed in to the Device Delay register. The overheads are different for the delays. In addition, the existing code does not handle the case when the delay is less than a SCLK period. This change accurately calculates the additional delays in Ref clocks. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * | | spi: cadence_qspi: Remove returns from end of void functionsPhil Edworthy2016-12-15-8/+0
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Acked-by: Marek Vasut <marek.vasut@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * | | spi: cadence_qspi: Use spi mode at the point it is neededPhil Edworthy2016-12-15-9/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of extracting mode settings and passing them as separate args to another function, just pass the SPI mode as an arg. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * | | spi: cadence_qspi: Clean up the #define namesPhil Edworthy2016-12-15-43/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A lot of the #defines are for single bits in a register, where the name has _MASK on the end. Since this can be used for both a mask and the value, remove _MASK from them. Whilst doing so, also remove the unnecessary brackets around the constants. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Acked-by: Marek Vasut <marek.vasut@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * | | spi: cadence_qspi: Use #define for bits instead of bit shiftsPhil Edworthy2016-12-15-18/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most of the code already uses #defines for the bit value, rather than the shift required to get the value. This changes the remaining code over. Whislt at it, fix the names of the "Rd Data Capture" register defs. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Acked-by: Marek Vasut <marek.vasut@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * | | spi: cadence_qspi: Better debug information on the SPI clock ratePhil Edworthy2016-12-15-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Show what the output clock rate actually is. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Acked-by: Marek Vasut <marek.vasut@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * | | spi: cadence_qspi: Fix baud rate calculationPhil Edworthy2016-12-15-16/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the existing code, when the requested SPI clock rate is near to the lowest that can be achieved by the hardware (max divider of the ref clock is 32), the generated clock rate is wrong. For example, with a 50MHz ref clock, when asked for anything less than a 1.5MHz SPI clock, the code sets up the divider to generate 25MHz. This change fixes the calculation. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * | | spi: cadence_qspi: Fix clearing of pol/pha bitsPhil Edworthy2016-12-15-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Or'ing together bit positions is clearly wrong. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Acked-by: Marek Vasut <marek.vasut@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * | | spi: Add error checking for invalid bus widthsSimon Glass2016-12-15-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present an invalid bus width prints a message but does not return an error. This is the opposite of the correct behaviour. Adjust it to avoid code bloat in the common case, and avoid hard-to-debug failure in the uncommon case. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * | | ARM: dts: am437x-idk: Fix QSPI compatible stringVignesh R2016-12-15-1/+1
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | Unlike Linux kernel, U-Boot depends on "spi-flash" compatible to probe m25p80 spi-nor devices. Hence, add "spi-flash" compatible string to m25p80 node. Without this patch, flash device DT data is not parsed and QSPI operates in unsupported mode leading to data corruption. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* | | Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-12-16-36/+624
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| * | | ARMv8: LS1043A: Enable LS1043A default PSCI supportmacro.wave.z@gmail.com2016-12-15-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A most basic PSCI implementation with only one psci_version is added for LS1043A, this can verify the generic PSCI framework, and more platform specific implementation will be added later. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | ARMv8: Setup PSCI memory and device treemacro.wave.z@gmail.com2016-12-15-5/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Newly add ARMv8 PSCI needs to be initialized, be copied or reserved in right place, this patch does all the setup steps. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | ARMv8: Add basic PSCI frameworkmacro.wave.z@gmail.com2016-12-15-0/+312
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces a generic ARMv8 PSCI framework, with all functions returning a dummy ARM_PSCI_RET_NI (Not Implemented), then it is up to each platform to implement their own functions based on this framework. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | ARMv8: Enable SMC instructionmacro.wave.z@gmail.com2016-12-15-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PSCI implementation needs the SMC instruction to be enabled. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | ARMv8: Add secure sections for PSCI text and datamacro.wave.z@gmail.com2016-12-15-1/+91
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds secure_text, secure_data and secure_stack sections for ARMv8 to hold PSCI text and data, and it is based on the legacy implementation of ARMv7. ARMV8_SECURE_BASE defines the address for PSCI secure sections, ARMV8_PSCI and ARMV8_PSCI_NR_CPUS are firstly used in this patch, so they are introduce here in Kconfig too. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | ARMv8: LS1043A: change macro CONFIG_ARMV8_PSCI definitionmacro.wave.z@gmail.com2016-12-15-9/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | NXP/Freescale uses macro CONFIG_ARMV8_PSCI to enable their private PSCI implementation in PPA firmware, but this macro naming too generic, so this patch replaces it with a specic one CONFIG_FSL_PPA_ARMV8_PSCI. And this macro CONFIG_ARMV8_PSCI will be used for a generic PSCI for ARMv8 which will be added in following patchs. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
generated by cgit v1.1 at 2024-11-20 13:51:36 +0000