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* board/freescale: Update MAINTAINERS filesYork Sun2016-08-02-9/+17
| | | | | | Update maintainers for secure boot targets. Signed-off-by: York Sun <york.sun@nxp.com>
* armv8: ls1043a: enable pxe commandsWenbin Song2016-08-02-0/+2
| | | | | | | Enable pxe command for ls1043ardb and ls1043aqds. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: ls1012a: Update Refresh cycle for DDRPrabhakar Kushwaha2016-08-02-1/+1
| | | | | | | | | | | Refresh cycle value must be selected based on the frequency of DDR. tREFI = 7.8 us as per JEDEC. The value for MDREF[REF_CNT] should be based on round up (tREFI/tCK) formula. For 500MHz, mdref value should be 0x0f3c8000. Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: ls1012a: Enable DDR row-bank-column decodingPrabhakar Kushwaha2016-08-02-1/+1
| | | | | | | | | | Enable DDR row-bank-column decoding to decode DDR address as row-bank-column instead of bank-row-column for improving performance of serial data transfers. Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* board: ls1012aqds: Update LBMAP_MASK and RST_CTL_RESETPrabhakar Kushwaha2016-08-02-2/+2
| | | | | | | | | | | qixis_reset altbank usagge ~QIXIS_LBMAP_MASK in code. So define inverse value QIXIS_LBMAP_MASK. Also, update QIXIS_RST_CTL_RESET value to keep RST_CTL[REQ_MOD] as 0b11 i.e. PORESET during qixis_reset Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* crypto/fsl: Update blob cmd to accept 64bit addressesSumit Garg2016-08-02-4/+11
| | | | | | | | | Update blob cmd to accept 64bit source, key modifier and destination addresses. Also correct output result print format for fsl specific implementation of blob cmd. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* driver: spi: fsl-qspi: remove compile WarningsYunhui Cui2016-08-02-1/+3
| | | | | | | | | | Warnins log: drivers/spi/fsl_qspi.c: In function ‘qspi_ahb_read’: drivers/spi/fsl_qspi.c:400:16: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] memcpy(rxbuf, (u8 *)(priv->cur_amba_base + priv->sf_addr), len); Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* powerpc/mpc85xx: Update erratum workaround for A006379York Sun2016-08-02-1/+1
| | | | | | | | Update erratum workaround for A006379 to set register CPCHDBCR0 with value 0x001e0000, replacing the old value 0x003c0000. Signed-off-by: York Sun <york.sun@nxp.com> Reported-by: Dave Liu <dave.liu@nxp.com>
* Merge git://git.denx.de/u-boot-rockchipTom Rini2016-07-31-49/+1415
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| * rockchip: add support for rk3288 PopMetal boardjk.kernel@gmail.com2016-07-31-1/+729
| | | | | | | | | | | | | | | | | | PopMetal is a rockchip rk3288 based board made by ChipSpark, which has many interface such as HDMI, VGA, USB, micro-SD card, WiFi, Audio and Gigabit Ethernet. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: add basic support for fennec-rk3288 boardjk.kernel@gmail.com2016-07-31-3/+630
| | | | | | | | | | | | | | | | | | | | Fennec is a RK3288-based development board with 2 USB ports, HDMI, micro-SD card, audio and WiFi and Gigabit Ethernet. It also includes on-board 8GB eMMC and 2GB of SDRAM. Expansion connectors provides access to display pins, I2C, SPI, UART and GPIOs. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: rk3288: move evb board to rockchip folderjk.kernel@gmail.com2016-07-31-6/+6
| | | | | | | | | | | | | | | | The 'evb-rk3288' is not a vendor name, change it to 'rockchip' which is the real vendor name. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: rk3288: revise CONFIG_FASTBOOT_BUF_ADDRjk.kernel@gmail.com2016-07-31-3/+1
| | | | | | | | | | | | | | | | CONFIG_SYS_LOAD_ADDR is absolutely safe to store image for fastboot. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: remove the duplicated macro configjk.kernel@gmail.com2016-07-31-4/+0
| | | | | | | | | | | | | | | | CONFIG_DOS_PARTITION and CONFIG_EFI_PARTITION are already included in config_distro_defaults.h, and we don't need them in SPL stage. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: rk3288: disable fastboot in SPL stagejk.kernel@gmail.com2016-07-31-1/+1
| | | | | | | | | | | | | | Reduce compilation time for SPL. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * Revert "rockchip: Move the MMC setup check earlier"jk.kernel@gmail.com2016-07-31-14/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Boot Rom wouldn't initialize sdmmc while booting from eMMC. We need to setup sdmmc gpio, otherwise we will hit an error below: =>mmc info blk_get_device: if_type=6, devnum=0: dwmmc@ff0c0000.blk, 6, 0 uclass_find_device_by_seq: 0 -1 uclass_find_device_by_seq: 0 0 - -1 -1 - -1 0 - found uclass_find_device_by_seq: 0 1 - -1 -1 - -1 0 - not found fdtdec_get_int_array: interrupts get_prop_check_min_len: interrupts Buswidth = 1, clock: 0 Buswidth = 1, clock: 400000 Sending CMD0 dwmci_send_cmd: Timeout on data busy dwmci_send_cmd: Timeout on data busy dwmci_send_cmd: Timeout on data busy dwmci_send_cmd: Timeout on data busy This reverts commit 6efeeea79c880d3dd262e0dca9da2687f0ab68c9. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
| * cosmetic: rockchip: rk3288: pinctrl: fix config symbol namingjk.kernel@gmail.com2016-07-31-1/+1
| | | | | | | | | | | | | | | | Revise config to CONFIG_ROCKCHIP_RK3288_PINCTRL. Signed-off-by: Ziyuan Xu <jk.kernel@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
| * rockchip: add a dummy byte for the sdram-channel propertyjk.kernel@gmail.com2016-07-31-1/+2
| | | | | | | | | | | | | | | | Add an extra byte so that this data is not byteswapped. Signed-off-by: Ziyuan Xu <jk.kernel@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
| * rockchip: rk3288: Fix pinctrl for GPIO bank 0John Keeping2016-07-31-2/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Bank 0 is the "PMU GPIO" bank which is controlled by the PMU registers rather than the GRF registers. In the GRF the top half of the register is used as a mask so that some bits can be updated without affecting the others, but in the PMU this feature is not provided and the top half of the register is reserved. Take the same approach as the Linux driver to update the value via read-modify-write but setting the mask for only the bits that have changed. The PMU registers ignore the top 16 bits so this works for both GRF and PMU iomux registers. Signed-off-by: John Keeping <john@metanate.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * rk3399: Reserve space for ARM Trust FirmwareKever Yang2016-07-31-1/+2
| | | | | | | | | | | | | | RK3399 needs reserve 0x200000 at the beginning of DRAM, for ATF bl31. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: rk3036: update MAINTAINER fileXu Ziyuan2016-07-31-4/+4
| | | | | | | | | | | | | | Update MAINTAINER files for kylin_rk3036, evb_rk3036. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * configs: rockchip: remove no use MACROKever Yang2016-07-31-8/+0
| | | | | | | | | | | | | | | | The CONFIG_ROCKCHIP_COMMON and CONFIG_SPL_ROCKCHIP_COMMON are no use now, remove them. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * mmc-uclass: correct the device numberKever Yang2016-07-31-3/+9
| | | | | | | | | | | | | | | | | | Not like the mmc-legacy which the devnum starts from 1, it starts from 0 in mmc-uclass, so the device number should be (devnum + 1) in get_mmc_num(). Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* | sunxi: Re-enable h3 emac supportHans de Goede2016-07-31-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | With the recent bug fixes for the sun8i_emac driver all known issues are resolved, so we can re-enable the driver. While at it, also enable the emac on the Orange Pi One. Cc: Chen-Yu Tsai <wens@csie.org> Cc: Corentin LABBE <clabbe.montjoie@gmail.com> Cc: Amit Singh Tomar <amittomer25@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Acked-by: Jagan Teki <jteki@openedev.com>
* | net: sun8i_emac: Fix DMA alignment issues with the rx / tx buffersHans de Goede2016-07-31-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes the following CACHE warnings when using sun8i_emac: => dhcp BOOTP broadcast 1 BOOTP broadcast 2 CACHE: Misaligned operation at range [7bf594a8, 7bf59628] BOOTP broadcast 3 CACHE: Misaligned operation at range [7bf59c90, 7bf59e10] CACHE: Misaligned operation at range [7bf5a478, 7bf5a5f8] DHCP client bound to address 10.42.43.80 (1009 ms) Note this commit also changes the max rx size from 2024 to 2044, matching what the kernel driver uses. Cc: Chen-Yu Tsai <wens@csie.org> Cc: Corentin LABBE <clabbe.montjoie@gmail.com> Cc: Amit Singh Tomar <amittomer25@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sunxi: On newer SoCs use words 1-3 instead of just word 3 from the SIDHans de Goede2016-07-31-1/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It seems that bytes 13-14 of the SID / bytes 1-2 from word 3 of the SID are always 0 on H3 making it a poor candidate to use as source for the serialnr / mac-address, and the other non constant words (1 and 2) also have quite a few bits which are the same for some boards, This commits switches to using the crc32 of words 1 - 3 to get a more unique value for the mac-address / serialnr. Cc: Chen-Yu Tsai <wens@csie.org> Cc: Corentin LABBE <clabbe.montjoie@gmail.com> Cc: Amit Singh Tomar <amittomer25@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sunxi: Ensure that the NIC specific bytes of the mac are not all 0Hans de Goede2016-07-31-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | On 2 of my H3 boards bytes 13-15 of the SID are all 0 leading to the NIC specific bytes of the mac all being 0, which leads to the boards not getting an ipv6 address from the dhcp server. This commits adds a check to ensure this does not happen. Cc: Chen-Yu Tsai <wens@csie.org> Cc: Corentin LABBE <clabbe.montjoie@gmail.com> Cc: Amit Singh Tomar <amittomer25@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sunxi: Hummingbird_A31_defconfig: Drop MACPWR optionChen-Yu Tsai2016-07-31-1/+1
| | | | | | | | | | | | | | | | | | | | MACPWR was used to bring the Ethernet PHY out of reset. The designware driver now supports the phy reset gpio binding, so this is no longer needed. In fact in requesting the same GPIO, it makes the designware driver fail to probe. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | sunxi: gpio: Add .xlate function for gpio phandle resolutionChen-Yu Tsai2016-07-31-0/+16
|/ | | | | | | | | | | | | sunxi uses a 2 cell phandle for gpio bindings. Also there are no seperate nodes for each pin bank. Add a custom .xlate function to map gpio phandles to the correct pin bank device. This fixes gpio_request_by_name usage. Fixes: 7aa974858422 ("dm: sunxi: Modify the GPIO driver to support driver model") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* m68k: code reformatting for all start.S filesAngelo Dureghello2016-07-30-501/+449
| | | | | | | | | | | | | This patch is style-related only, to reformat all the start.S code, actually not following a coherent style inside single files and between different cpu start.S files. Linux format has been respected, as - max line width at 80 columns - one 8 cols tab between asm instructions and operands - inline comments, where any, fixed at col 41 Signed-off-by: Angelo Dureghello <angelo@sysam.it>
* ARM: am57xx_evm: Enable QSPI supportVignesh R2016-07-30-0/+51
| | | | | | | | | | AM571x IDK and AM572x IDK EVMs have spansion s25fl256s QSPI flash on the board connected to TI QSPI IP over CS0. Therefore enable QSPI support. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* ARM: dts: am57xx-idk-common: Enable support for QSPIVignesh R2016-07-30-0/+49
| | | | | | | | | | | AM571x and AM572x IDK have a spansion s25fl256s QSPI flash on the board connected to TI QSPI over CS0. Hence, add QSPI and flash slave DT nodes. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* configs: am43xx_evm_defconfig: Enable CONFIG_SPI_FLASH_BARVignesh R2016-07-30-0/+1
| | | | | | | | | | AM437x SK and AM437x IDK EVMs have 64MB flash, therefore enable CONFIG_SPI_FLASH_BAR to access flash regions above 16MB. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* ARM: dts: dra7xx: Update spi-max-frequency for QSPIVignesh R2016-07-30-2/+2
| | | | | | | | | | | According to AM572x DM SPRS953A, QSPI max bus speed is 76.8MHz. Therefore update the spi-max-frequency value of QSPI node for DRA74 and DRA72 evm. This increase flash read speed by ~2MB/s. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
* configs: dra7xx: Update QSPI speed to 76.8MHzVignesh R2016-07-30-1/+1
| | | | | | | | | | Now that QSPI driver can support 76.8MHz, update the CONFIG_SF_DEFAULT_SPEED to the same value. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
* spi: ti_qspi: dra7xx: Add support to use 76.8MHz clockVignesh R2016-07-30-5/+12
| | | | | | | | | | According to AM572x DM SPRS953A, QSPI bus speed can be 76.8MHz, update the driver to use the same. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
* ARM: dra7xx: Change DPLL_PER_HS13 divider valueLokesh Vutla2016-07-30-1/+1
| | | | | | | | | | | According to AM572x DM SPRS953A, QSPI bus speed can be 76.8MHz, hence update QSPI input clock divider value (DPLL_PER_HS13) to provide 76.8MHz clock, so that driver can use the same. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* sf: sf_params: Add AT25DF321 flash supportWenyou Yang2016-07-30-1/+2
| | | | | | | | Add AT25DF321 flash support. Fix AT25DF321A device name. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* spi: ti_qspi: Remove delay in read path for dra7xxVignesh R2016-07-30-3/+0
| | | | | | | | | | | | As per commit b545a98f5dc563 ("spi: ti_qspi: Add delay for successful bulk erase) says its added to meet bulk erase timing constraints. But bulk erase is a cmd to flash and delay in read path does not make sense. Morever, testing on DRA74/DRA72 evm has shown that this delay is no longer required. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
* spi: ti_qspi: Fix compiler warning when DEBUG macro is setVignesh R2016-07-30-2/+2
| | | | | | | | | | clk_div is uninitialized at the beginning of ti_spi_set_speed(), move debug() print after clk_div calculation to avoid compiler warning and to have proper value of clk_div printed during debugging. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
* spi: ti_qspi: Fix failure on multiple READ_ID cmdVignesh R2016-07-30-3/+2
| | | | | | | | | | | | | | Populating QSPI_RD_SNGL bit(0x1) in priv->cmd means that value QSPI_INVAL (0x4) is not written to CMD field of QSPI_SPI_CMD_REG in ti_qspi_cs_deactivate(). Therefore CS is never deactivated between successive READ ID which results in sf probe to fail. Fix this by not populating priv->cmd with QSPI_RD_SNGL and OR it wih priv->cmd as required (similar to the convention followed in the driver). Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
* spi: Add support for N25Q016AMoritz Fischer2016-07-30-0/+1
| | | | | | | | This commit adds support in the spi-nor driver for the N25Q016A, a 16Mbit SPI NOR flash from Micron. Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2016-07-28-402/+3882
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| * MAINTAINERS: i.MX: Add board/freescale/*mx* pathFabio Estevam2016-07-28-0/+1
| | | | | | | | | | | | | | | | | | | | | | Pass the board/freescale/*mx*/ path as files maintained by Stefano Babic. While this is not ideal and does not cover all the i.MX board cases, it gives at least a better hint for the /scripts/get_maintainer.pl tool. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
| * mx7dsabresd: MAINTAINERS: Add mx7dsabresd_secure_defconfigFabio Estevam2016-07-28-0/+1
| | | | | | | | | | | | Add an entry for the mx7dsabresd_secure_defconfig target. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
| * mx7_common: initialize generic timer on all CPU'sStefan Agner2016-07-28-0/+1
| | | | | | | | | | | | | | | | | | Use CONFIG_TIMER_CLK_FREQ to let the non-secure init code initialize the generic timer on all CPU's. This allows to make use of the timer freuquency register also on other CPU than the start CPU which is important for KVM. Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
| * mx6ul_14x14_evk: Remove unused defineDiego Dorta2016-07-28-3/+0
| | | | | | | | | | | | | | Remove unused define constant. Signed-off-by: Diego Dorta <diego.dorta@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
| * cgtqmx6eval: Remove uneeded PHYS_SDRAM_SIZEFabio Estevam2016-07-28-1/+0
| | | | | | | | | | | | | | | | | | | | | | cgtqmx6eval uses the imx_ddr_size() function to calculate the DDR size in runtime, so there is no need to define PHYS_SDRAM_SIZE. Remove the unneeded definition. Cc: Otavio Salvador <otavio@ossystems.com.br> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Acked-by: Otavio Salvador <otavio@ossystems.com.br>
| * novena: Remove uneeded PHYS_SDRAM_SIZEFabio Estevam2016-07-28-1/+0
| | | | | | | | | | | | | | | | | | | | | | novena uses the imx_ddr_size() function to calculate the DDR size in runtime, so there is no need to define PHYS_SDRAM_SIZE. Remove the unneeded definition. Cc: Marek Vasut <marex@denx.de> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Acked-by: Marek Vasut <marex@denx.de>
| * bx50v3: Use imx_ddr_size() for calculating the DDR sizeFabio Estevam2016-07-28-3/+1
| | | | | | | | | | | | | | | | | | imx_ddr_size() can be used to calculate the DDR size in runtime. By using this function we no longer need to define PHYS_SDRAM_SIZE. Cc: Martin Donnelly <martin.donnelly@ge.com> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
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