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* ENGR00155018 mx53_pcba: update Ripley AUX input to 950mA and charge currentWayne Zou2011-08-19-2/+3
| | | | | | | set Ripley AUX input current limit to 950mA and set charge termination current to 400mA Signed-off-by: Wayne Zou <b36644@freescale.com>
* ENGR00154998 mx53 pcba: correct the default bootargsXinyu Chen2011-08-18-29/+9
| | | | | | Default boot up with the 7' LCD on. Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
* ENGR00154924 [MX6]Disable some clocks in ubootAnson Huang2011-08-17-2/+7
| | | | | | | | | | | We should disabel some clocks in uboot to save power, or when we download from enet to boot up kernel, the power consumption could be up 800mA@5V, may damage the chip. After apply it, we can save more then 200mA@5V. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00154396: U_BOOT: Env config adjustment.Terry Lv2011-08-12-85/+85
| | | | | | | Change env size to 8K and change gpmi nand env offset to 2M. This will reduce boot time and fix gpmi nand env problem. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00154762 mx53_pcba: update Ripley/mc34708 USB/AUX charger settingsWayne Zou2011-08-12-4/+13
| | | | | | update Ripley USB and AUX/DC charger settings for pcba revB board Signed-off-by: Wayne Zou <b36644@freescale.com>
* ENGR00154468 mx53 pcba: Add DC-IN power supply support for revB boardWayne Zou2011-08-08-1/+9
| | | | | | | | Add DC-IN power supply support for revB board when booting from EMMC. set both AUX&USB current limit to 1.5A for Ripley 2.1 only Change CC current to 950mA Signed-off-by: Wayne Zou <b36644@freescale.com>
* ENGR00154400 mx53 pcba: bringup update for RevB boardXinyu Chen2011-08-05-13/+16
| | | | | | | | | Update DDR DCD configuration Open all the clocks during boot Change CV voltage to 4.2V Signed-off-by: Weihua Zou <wayne.zou@freescale.com> Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
* ENGR00153761 imx6q ipuv3: improve display qualityrel_imx_2.6.38_11.08.00Jason Chen2011-07-27-2/+8
| | | | | | | | | to avoid ipu starvation issue. 1. enable IPU AXI cache in uboot 2. set Qos to 7 for IPU to highest priority in uboot. 3. set AXI id to 0 for high priority IDMA channel in linux. Signed-off-by: Jason Chen <b02280@freescale.com>
* ENGR00153759 mx51: fix fastboot build failed without boot partition macroXinyu Chen2011-07-27-0/+2
| | | | | | | In mx51 configuration, CONFIG_BOOT_PARTITION_ACCESS is not defined. This cause build error to fastboot.c Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
* ENGR00153526 mx53 pcba: add pcba board revB support in ubootXinyu Chen2011-07-27-3/+1734
| | | | | | | | | | | | | | | Add new machine type for pcba. Add UART, I2C, SD/MMC, PMIC, DDR initial support. Add MFG tool support. Add support for MC34708 on revB pcba board. Update VDDGP setting on MC34708 PMIC for revB board. Close unused clock, for fastboot it will enable usb_phy usb_oh3 clock by itself, still need to verify this work or not when revB bootup. Signed-off-by: Wayne Zou <b36644@freescale.com> Signed-off-by: Lily Zhang <r58066@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00153605 fastboot: uboot cannot be burned to boot partitionSammy He2011-07-26-5/+16
| | | | | | | uboot image cannot be burned to boot partition for eMMC 4.3. This patch will fix it. Signed-off-by: Sammy He <r62914@freescale.com>
* ENGR00153597 [MX6]Enbale MMDC low powerAnson Huang2011-07-25-3/+4
| | | | | | | Enable auto self-refresh of MMDC to save power when memory idle. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00143438 [MX50 RD3]DCDC_3V15 GPIO changeAnson Huang2011-07-22-2/+2
| | | | | | | Change DCDC_3V15's GPIO setting for REV-D. Signed-off-by: Anson Huang <b20788@freescale.com> (cherry picked from commit 28a8e166c6a8fa001325f88ef06e5a81f6ed82a9)
* ENGR00151310 mx53 smd: force warm reset as cold resetLily Zhang2011-07-22-15/+9
| | | | | | | | | | This patch is used to support watchdog timeout in SMD RevA, RevB board. 1. Revert "ENGR00143469 mx53 smd: pull down GPIO_9 to reset the board". 2. Force warm reset as cold reset. Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00151695 mx53 ddr3: update ESDREF and MR0Lily Zhang2011-07-21-9/+9
| | | | | | | | | | | Updated mx53 ddr3 script according to MX53_TO2_DDR3_LCB_SMD_ARDb_v1.inc from Michael J Kjar on July 8, 2011: -change ESDREF[REF_SEL]=01 (for 32KHz), from incorrect setting of 00 (64KHz) -change DDR3 MR0 write to "setmem /32 0x63fd901c = 0x052080b0" from "0x092080b0". This chagned write recovery from 8 clocks to 6 clocks (in line with ESDCFG1[tWR]) Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00152843 mx51/3: align the android default env with documentXinyu Chen2011-07-21-61/+21
| | | | | | | | | Use simple enviroment to implement the default boot command. The original one is too complex, and not readable. For MX51BBG, only SD card boot env is supportd by default. For MX53SMD, only eMMC boot env is supportd by default. Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
* ENGR00153394 mx50 rd3: make SDHC1 as default boot device for androidXinyu Chen2011-07-20-48/+50
| | | | | | | Drop NAND/SPI boot support. Enable fastboot. Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
* ENGR00152907 MX5X: update GPU default cmdline.Zhang Jiejing2011-07-14-39/+39
| | | | | | update default cmdline to align with Document. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
* ENGR00152755 MX6 Switch DRAM init script from plugin to DCD for emmc fastbootAnish Trivedi2011-07-06-265/+146
| | | | | | | | | | | | | | | | | ROM requires DCD table instead of plugin to initialize DRAM if emmc fastboot mode is to be used. Therefore, switched the DRAM script from plugin to DCD table. The DCD table created is based on the following RVD script: Arik_init_DDR3_528MHz_002.inc found at http://compass.freescale.net/livelink/livelink?func=ll&objId=222928845 When fastboot mode is used by ROM, the MMC_BOOT register of USDHC does not get reset when RSTA bit is set by uboot driver. Therefore, need to write 0 to it manually during driver init. This brings USDHC out of fastboot mode, allowing normal communication with emmc to proceed in uboot. Changed comments for DLL delay to be more accurate. Signed-off-by: Anish Trivedi <anish@freescale.com>
* ENGR00139206 MX6 USDHC eMMC 4.4 supportAnish Trivedi2011-07-05-24/+75
| | | | | | | | | | | New bit definitions in USDHC. Added is_usdhc variable to fsl_esdhc_cfg to distinguish between ESDHC and USDHC. Enabled DDR mode support in USDHC. Created a config to customize target delay for DDR mode. Modified USDHC pad settings to make DDR mode work for all emmcs at 50 MHz. Signed-off-by: Anish Trivedi <anish@freescale.com>
* ENGR00152439: MX51: PLL workaround should be implemented only for PLL1Ranjani Vaidyanathan2011-07-01-2/+15
| | | | | | Make sure the PLL workaround is done only for PLL1. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
* ENGR00152241 MX6: enable 1G speed mode for PHY and ENETZeng Zhaoming2011-06-29-10/+41
| | | | | | | | | | | | | In precode, PHY forced to work at 100M even connect to 1G switch. In this commit, let PHY auto negotiate it working speed. Enet tx work at store-and-forward mode. BTW, AR8031 take quite a long time, about 1.6s from negotiation to link up. we have to wait and then set ENET correctly. Signed-off-by: Zeng Zhaoming <b32542@freescale.com>
* ENGR00139198: iMX61 uBoot add ENET supportZeng Zhaoming2011-06-27-69/+139
| | | | | | | | | | | | | | | | Add ENET and AR8031 PHY support to uboot. To make it works on sabreauto, need do following changes: 1. rework phy to output 125M clock from CLK_25M signal, and the 125M clock input to SoC as reference clock to generate RGMII_TXC clock. 2. Enable TXC delay in PHY debug register. 3. set ENET working in RMII mode. 4. set ENET working at 1000M or 100M/10M. 5. set ENET TX fifo to maximum to avoid underrun error. 6. force AR8031 PHY working at 100M Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Zeng Zhaoming <b32542@freescale.com>
* ENGR00144424 MX6: enable uboot for ARM2(SABREAUTO) CPU boardAnson Huang2011-06-24-8/+10711
| | | | | | | | | | | | | Use 528M DDR script Disable L2 cache because rom enable L2 cache when use plug-in Fix usdhc pad settings Remove mac address hardcode Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Richard Zhu <r65037@freescale.com> Signed-off-by: Terry Lv <r65388@freescale.com> Signed-off-by: Anish Trivedi <anish@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00151966: MX51 - Apply SW workaround for the PLL1 unlock HW issue.Ranjani Vaidyanathan2011-06-22-10/+43
| | | | | | | | | | | | | | | | | | | | | | Apply the following SW workaround to fix the PLL unlock issue. 1.Move all the clock sources which are currently running on PLL1 from PLL1 to PLL2 2.Clear AREN bit in PLL1 (to avoid restart during MFN change) 3.Program the PLL1 to the next settings: a. MFI = 8 b. MFD = 179 c. MFN = 180 d. PLM = 1 4.Manually restart the PLL1 5.Wait to PLL1 to lock 6.Reprogram the PLL1 to the next settings: a. MFI = 60, others keep same 7.Load the MFN 8.Wait for LDREQ and delay ~4.6us 9.Switch the clocks which were previously moved from PLL1 to PLL2 back to PLL1 Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
* ENGR00151892 MX50: Workaround to prevent PLL1 from losing lockAnish Trivedi2011-06-21-24/+59
| | | | | | | | | | | | | | | PLL1 workaround to prevent it from losing lock: (1) Disable AREN bit to avoid PLL1 restart during MFN change (2) set PLL1 to ~864Mhz with MFI = 8, MFN = 180, MFD = 179, PDF = 0 (3) Manual restart PLL1 (4) Wait PLL1 lock (5) Set PLL1 to 800Mhz with only change MFN to 60, others keep (6) Set LDREQ bit to load new MFN (7) Poll on LDREQ bit for MFN update to be completed (8) Delay at least 4 us to avoid PLL1 instability window (9) Switch ARM back to PLL1 Signed-off-by: Anish Trivedi <anish@freescale.com>
* ENGR00151187 MX53 SMD: Kernal stopped Usb driver after reseting in stop modeWayne Zou2011-06-10-1/+14
| | | | | | | After reseting in stop mode, the VUSB_2V5 voltage is disable by pmic. It needs to be enable manually in u-boot. Signed-off-by: Wayne Zou <b36644@freescale.com>
* ENGR00144224: MX53: Add MMU mapping for all peripheralsTerry Lv2011-06-09-36/+84
| | | | | | | Not all peripherals are mapped in MMU. Thus we add those missed mapped area. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00144389 mx53 QS Ripley: change VCC from 1.35V to 1.3V QS Ripley boardWayne Zou2011-06-01-2/+2
| | | | | | Change VCC from 1.35V to 1.3V QS Ripley board Signed-off-by: Wayne Zou <b36644@freescale.com>
* ENGR00144060 MX53_SMD: recovery android, update recovery command for emmc.Zhang Jiejing2011-05-26-1/+1
| | | | | | Change the recovery boot for MX53_SMD to emmc 's device 1. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
* ENGR00143837 mx50 rd3: support android boot from RD3 NAND deviceXinyu Chen2011-05-23-12/+7
| | | | | | | | | Enable NAND gpio, recovery mode detect after boot from spi nor. Change default env for loading kernel and uramdisk from NAND, disabling elcdif lcd driver to support EPDC eink panel as default. Enable recovery mode support and NAND/UBI/UBIFS command. Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
* ENGR00143704: U_BOOT: Nand oobsize is wrong in some nand chipsTerry Lv2011-05-20-7/+11
| | | | | | Nand oobsize is wrong in some nand chips. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00143298: Reinit uart after using clk commandTerry Lv2011-05-20-0/+6
| | | | | | | For clk command always make console output mess characters, here we reinitilize it after clock is changed. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00143302 Add mc34708 pmic support on loco/Ripley boardZou Weihua -wayne zou2011-05-20-10/+47
| | | | | | Add mc34708 pmic support on loco/Ripley board Signed-off-by: Zou Weihua -wayne zou <b36644@freescale.com>
* ENGR00143570 mx53: change the default environment settingLily Zhang2011-05-19-10/+14
| | | | | | | Change the default environment setting as sd boot for mx53 loco, mx53 smd and mx53 ard boards. Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00143613 uboot: update the android ramdisk load addressXinyu Chen2011-05-18-3/+3
| | | | | | | update the ramdisk load address due to android kernel size enlarge. the ramdisk memory load address is 5MB offset to kernel. Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
* ENGR00143469 mx53 smd: pull down GPIO_9 to reset the boardLily Zhang2011-05-16-0/+15
| | | | | | | | | In mx53 smd, to type "reset" command in u-boot console can not reset the system. It hangs in ROM with unknown reason. This patch adds one workaround to configure GPIO_9 (WDT_OUTPUT_B) as GPIO and pull down it to reset DA9053 PMIC. Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00143461 mx51 evk: increase VDDGP as 1.1v for 800MHZLily Zhang2011-05-16-0/+5
| | | | | | | | The default VDDGP output voltage is 1.05V in mx51 evk board According to mx51 datasheet (Rev 0.4), the VDDGP for 800MHZ should be 1.1v for 800MHZ Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00143457: Don't let ROM copy .bss sectionJason Liu2011-05-16-5/+9
| | | | | | | | | | | Don't need let ROM copy the .bss section since it will all be zeroed by u-boot at start up, thus it can speed up the boot up time. Need add CONFIG_FLASH_HEADER_OFFSET to the size since ROM will copy from the beginning of the MMC card. Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00143442 uboot: support android spi boot and mfg on mx50 rd3 boardXinyu Chen2011-05-16-4/+443
| | | | | | | | | | | | Add mx50_rd3_android default config file Add basic support for UBI partition mount and UBIFS file read for recovery Add gpmi nand enable in MFG kernel commandline by uboot configure, which enable MFG tool to flash system images on NAND. The total NAND boot and NAND recovery has been disabled. They will be enabled later. Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
* ENGR00143428 mx53 ard RevB: use internal clock for sataLily Zhang2011-05-14-0/+19
| | | | | | Switch to use SATA internal clock in mx53 ARD RevB board. Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00142995 MX50: Enable uSDHC instead of eSDHC for SDR modeAnish Trivedi2011-05-10-13/+103
| | | | | | | | | | | | | | | | | | On SD3 on MX50, there is an option to choose eSDHC or uSDHC controller. By default eSDHC is selected. However, eSDHC shows some borderline timing in SDR mode at 50 MHz, whereas uSDHC shows borderline timing in DDR mode at 50 MHz. Therefore, add a compile time option to uboot for MX50 to select uSDHC in SDR mode or eSDHC in DDR mode on SD3 port. By default the compile time option, CONFIG_MX50_ENABLE_USDHC_SDR, is commented out in the include/configs/mx50_<board>.h file to select eSDHC with DDR mode enabled. Uncomment the define to select uSDHC with only SDR mode enabled. Also increased max frequency supported by ESDHC to 52 MHz instead of 50 MHz. Signed-off-by: Anish Trivedi <anish@freescale.com>
* ENGR00143178 mx53 ARD DDR3 board: add MFG tool supportLily Zhang2011-05-10-0/+231
| | | | | | Add MFG tool support for MX53 ARD DDR3 board. Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00142740 mx50 rdp: mfg support GPMI nand by command lineXinyu Chen2011-04-29-2/+2
| | | | | | | | As android make UBIFS as default file system on MX508 RDP, we must enable MFG tool to support UBIFS image update. So enable GPMI nand in default commandline to detect nand devices. Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
* ENGR00142497 Android: MX53_SMD: check eMMC and SD recovery file.Zhang Jiejing2011-04-22-38/+42
| | | | | | | | | | Check eMMC and SD cards recovery file, if it exist, enter recovery mode. original code only check SD card, since we already change main storage to eMMC, so we check it both, since most of customer still test it under SD card, check them to avoid support effert. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
* ENGR00142322: mx53-smd: spi nor: can't erase 0x200000 sizeTerry Lv2011-04-20-14/+14
| | | | | | | | | | | | | Spi nor can't erase 0x200000 size. There are two issues in this CR. 1. Spi nor can't erase 0x200000 size. 2. Whole chip erase don't work. The solution will be: 1. Delay more time for WIP check. 2. Use normal erase for whole chip erase. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00141885: mx50 and mx53 reboot fail when booting from spi norTerry Lv2011-04-20-2/+15
| | | | | | | mx50 reboot fail when booting from spi nor. Reconfigure eCSPI SS signal as GPIO before reset. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00142259 set UART2_RXD (GP6_11) to highRobby Cai2011-04-18-0/+10
| | | | | | | Isolate EIM signals and boot configuration signals. Without this setting, the chip's temperature will be high. Signed-off-by: Robby Cai <R63905@freescale.com>
* ENGR00142247 MX50: Add PD+3 routine for all DDR typesRobby Cai2011-04-16-18/+34
| | | | | | | | | | | PD+3 routine help test pass for ddr with higher freq. Tested on ARM2 board (mDDR, DDR2) RDP board (LPDDR2 from both vendors) RD3 board (LPDDR2) Signed-off-by: Robby Cai <R63905@freescale.com>
* ENGR00142246 MX50 Update DDR2 script to use more optimized settingsRobby Cai2011-04-16-123/+64
| | | | | | | | | | | | | | | New DDR2 initialization script from designer includes controller changes as well as very important PHY changes that increase internal sampling window to detect DQS edge. This increase compensates for possible jitter. The script, Codex_DDR2_266MHz.inc v3, is found at http://compass.freescale.net/livelink/ livelink?func=ll&objId=218722501&objAction=browse&viewType=1 Also corrected the DDR clock. (DDR mode changed from Sync to Async) Signed-off-by: Robby Cai <R63905@freescale.com>
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