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* ARM: Default to using optimized memset and memcpy routinesTom Rini2017-01-20-6/+48
| | | | | | | | | | | | | | | | | | | | | | We have long had available optimized versions of the memset and memcpy functions that are borrowed from the Linux kernel. We should use these in normal conditions as the speed wins in many workflows outweigh the relatively minor size increase. However, we have a number of places where we're simply too close to size limits in SPL and must be able to make the size vs performance trade-off in those cases. Cc: Philippe Reynes <tremyfr@yahoo.fr> Cc: Eric Jarrige <eric.jarrige@armadeus.org> Cc: Heiko Schocher <hs@denx.de> Cc: Magnus Lilja <lilja.magnus@gmail.com> Cc: Lokesh Vutla <lokeshvutla@ti.com> Cc: Chander Kashyap <k.chander@samsung.com> Cc: Akshay Saraswat <akshay.s@samsung.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* mach-omap2: Fix secure boot media generationAndrew F. Davis2017-01-20-5/+1
| | | | | | | | | | | While moving OMAP related files to mach-omap2 the functionality relating to generating secure boot files was modified. This change prevents secure platforms other than AM33xx and OMAP54XX from correctly building files for all needed media types. Fixes: 983e37007da5 ("arm: Introduce arch/arm/mach-omap2 for OMAP2 derivative platforms") Signed-off-by: Andrew F. Davis <afd@ti.com> Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
* spl: Add some missing newlinesAndrew F. Davis2017-01-20-2/+2
| | | | | | Signed-off-by: Andrew F. Davis <afd@ti.com> Acked-by: Lokesh Vutla <lokeshvutla@ti.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
* spl: Remove inline ifdef check for EXT and FAT supportAndrew F. Davis2017-01-20-4/+0
| | | | | | | | | | These files are only included for build by the make system when CONFIG_SPL_{EXT,FAT}_SUPPORT is enabled, remove the unneed checks for these in the source files. Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* common/image.c: Use correct suffixes for binary sizesxypron.glpk@gmx.de2017-01-20-1/+1
| | | | | | | | | | | | | | IEC 80000-13:2008 Quantities and units Part 13: Information science and technology defines the prefixes to use for binary multiples. So instead of writing Data Size: 6726132 Bytes = 6568.49 kB = 6.41 MB in dumpimage we should write Data Size: 6726132 Bytes = 6568.49 KiB = 6.41 MiB. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
* api: storage: Test all block device in dev_stor_getEmmanuel Vadot2017-01-20-64/+34
| | | | | | | | | | | In a config with one MMC at device id '1' and no MMC at device id '0' (a BeagleBone Black with no sd inserted for example), the current code will first test to access the MMC 0 (sd port), seeing that no device is present it will simply return that no more device are present for this class. This patch fixes this by testing all devices for each class. Signed-off-by: Emmanuel Vadot <manu@bidouilliste.com>
* api: Use hashtable function for API_env_enumEmmanuel Vadot2017-01-20-29/+31
| | | | | | | | | | The current code can loop undefinitly as it doesn't parse correctly the env data. Since the env is an hashtable, use the hashtable function for the API_ENV_ENUM api call. Signed-off-by: Emmanuel Vadot <manu@bidouilliste.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* cmd/host: add missing \n in help textSébastien Szymanski2017-01-20-1/+1
| | | | Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
* ARM: omap3_logic: Refactor Boot Environmental variablesAdam Ford2017-01-20-32/+42
| | | | | | | | | | Some scripts are calling the same functions, so these changes consolidate common scripts together to reduce redundancy and shrink size a bit. This also keeps the 'bootargs' variable from growing if manually called more than one time. This also adds NAND booting scripts based on newly consolidated scripts. Signed-off-by: Adam Ford <aford173@gmail.com>
* bootm: relocate ramdisk if CONFIG_SYS_BOOT_RAMDISK_HIGH setRick Altherr2017-01-20-16/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | In 35fc84f, bootm was refactored so plain 'bootm' and 'bootm <subcommand>' shared a common implementation. The 'bootm ramdisk' command implementation is now part of the common implementation but not invoke by plain 'bootm' since the original implementation never did ramdisk relocation. Instead, ramdisk relocation happened in image_setup_linux() which is typically called during the OS portion of 'bootm'. On ARM, parameters to the Linux kernel can either be passed by FDT or ATAGS. When using FDT, image_setup_linux() is called which also triggers ramdisk relocation. When using ATAGS, image_setup_linux() is _not_ called because it mostly does FDT setup. Instead of calling image_setup_linux() in both FDT and ATAGS cases, include BOOTM_STATE_RAMDISK in the requested states during a plain 'bootm' if CONFIG_SYS_BOOT_RAMDISK_HIGH is set and remove the ramdisk relocation from image_setup_linux(). This causes ramdisk relocation to happen on any system where CONFIG_SYS_BOOT_RAMDISK_HIGH regardless of the OS being booted. Also remove IMAGE_ENABLE_RAMDISK_HIGH as it was only used by the now-removed code from image_setup_linux(). Signed-off-by: Rick Altherr <raltherr@google.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joel Stanley <joel@jms.id.au>
* serial, ns16550: bugfix: ns16550 fifo not enabledHeiko Schocher2017-01-20-24/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit: 65f83802b7a5b "serial: 16550: Add getfcr accessor" breaks u-boot commandline working with long commands sending to the board. Since the above patch, you have to setup the fcr register. For board/archs which enable OF_PLATDATA, the new field fcr in struct ns16550_platdata is not filled with a default value ... This leads in not setting up the uarts fifo, which ends in problems, when you send long commands to u-boots commandline. Detected this issue with automated tbot tests on am335x based shc board. The error does not popup, if you type commands. You need to copy&paste a long command to u-boots commandshell (or send a long command with tbot) Possible boards/plattforms with problems: ./arch/arm/cpu/arm926ejs/lpc32xx/devices.c ./arch/arm/mach-tegra/board.c ./board/overo/overo.c ./board/quipos/cairo/cairo.c ./board/logicpd/omap3som/omap3logic.c ./board/logicpd/zoom1/zoom1.c ./board/timll/devkit8000/devkit8000.c ./board/lg/sniper/sniper.c ./board/ti/beagle/beagle.c ./drivers/serial/serial_rockchip.c Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Tested-by: Adam Ford <aford173@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2017-01-19-969/+2834
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| * armv8: ls1012a: define esdhc_status_fixup for RDB boardYangbo Lu2017-01-18-0/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On LS1012ARDB board, three dual 1:4 mux/demux devices drive the SDHC2 signals to eMMC, SDIO wifi, SPI and Ardiuno shield. Only when we select eMMC and SDIO wifi, the SDHC2 could be used. Otherwise, the command inhibit bits of eSDHC2_PRSSTAT register will never release. This would cause below continious error messages in linux since it uses polling mode to detect card. "mmc1: Controller never released inhibit bit(s)." "mmc1: Controller never released inhibit bit(s)." "mmc1: Controller never released inhibit bit(s)." This patch is to define esdhc_status_fixup function for RDB to disable SDHC2 status if no SDIO wifi or eMMC is selected. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls1012a: define esdhc_status_fixup for QDS boardYangbo Lu2017-01-18-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The LS1012AQDS board has a hardware issue. When there is no eMMC adapter card inserted in SDHC2 adapter slot, the command inhibit bits of eSDHC2_PRSSTAT register will never release. This would cause below continious error messages in linux since it uses polling mode to detect card. "mmc1: Controller never released inhibit bit(s)." "mmc1: Controller never released inhibit bit(s)." "mmc1: Controller never released inhibit bit(s)." This patch is to define esdhc_status_fixup function for QDS to disable SDHC2 status if no eMMC adapter card is detected. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * mmc: fsl_esdhc: move 'status' property fixup into a weak functionYangbo Lu2017-01-18-7/+14
| | | | | | | | | | | | | | | | Move fdt fixup of 'status' property into a weak function. This allows board to define 'status' fdt fixup by themselves. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * fsl PPA: enable PPA for ls1043ardb and ls1046ardbHou Zhiqiang2017-01-18-0/+2
| | | | | | | | | | | | | | Enable PPA for ls1043ardb NOR boot and ls1046ardb QSPI boot. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * kconfig: fsl PPA: move CONFIG_* to KconfigHou Zhiqiang2017-01-18-16/+26
| | | | | | | | | | Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * ARMv8/sec_firmware: relocated and renamed the config FSL_PPA_ARMV8_PSCIHou Zhiqiang2017-01-18-17/+17
| | | | | | | | | | | | | | | | Moved the config FSL_PPA_ARMV8_PSCI from fsl-layerscape's Kconfig to Kconfig under armv8 and renamed it to SEC_FIRMWARE_ARMV8_PSCI. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * kconfig: armv8: move armv8 sec_firmware CONFIG_* to KconfigHou Zhiqiang2017-01-18-11/+36
| | | | | | | | | | | | Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> [York S: clean up scripts/config_whitelist.txt] Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: aarch64: Fix the warning about x1-x3 nonzero issueAlison Wang2017-01-18-45/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | For 64-bit kernel, there is a warning about x1-x3 nonzero in violation of boot protocol. To fix this issue, input argument 4 is added for armv8_switch_to_el2 and armv8_switch_to_el1. The input argument 4 will be set to the right value, such as zero. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: Alexander Graf <agraf@suse.de> Tested-by: Ryan Harkin <ryan.harkin@linaro.org> Tested-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8/fsl-layerscape: fdt: fixup LS1043A rev1 MSI nodeWenbin Song2017-01-18-0/+157
| | | | | | | | | | | | | | | | | | | | The default MSI node in kernel tree is for LS1043A rev1.0 silicon, if rev1.1 silicon used, need to fixup the MSI node to match it. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8/ls1043a: fixup GIC offset for ls1043a rev1Wenbin Song2017-01-18-6/+150
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The LS1043A rev1.1 silicon supports two types of GIC offset: 4K alignment and 64K alignment. The bit SCFG_GIC400_ALIGN[GIC_ADDR_BIT] is used to choose which offset will be used. The LS1043A rev1.0 silicon only supports the CIG offset with 4K alignment. If GIC_ADDR_BIT bit is set, 4K alignment is used, or else 64K alignment is used. 64K alignment is the default setting. Overriding the weak smp_kick_all_cpus, the new impletment is able to detect GIC offset. The default GIC offset in kernel device tree is using 4K alignment, it need to be fixed if 64K alignment is detected. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: fsl-lsch3: enable snoopable sata read and writeTang Yuantian2017-01-18-0/+2
| | | | | | | | | | | | | | | | | | By default the SATA IP on the ls208Xa SoCs does not generating coherent/snoopable transactions. This patch enable it in the sata axicc register. Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * ls1046ardb: Add support power initializationHou Zhiqiang2017-01-18-0/+41
| | | | | | | | | | | | | | | | | | Add the chip power supply voltage initialization on LS1046ARDB. Add function power_init_board(), and it will initialize the PMIC and call the chip power initialization function. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8/fsl_lsch2: Add chip power supply voltage setupHou Zhiqiang2017-01-18-0/+373
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Set up chip power supply voltage according to voltage ID. The fuse status register provides the values from on-chip voltage ID fuses programmed at the factory. These values define the voltage requirements for the chip. Main operations: 1. Set up the core voltage 2. Set up the SERDES voltage and reset SERDES lanes 3. Enable/disable DDR controller support 0.9V if needed Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * ls1046ardb: cpld: add API for selecting core voltHou Zhiqiang2017-01-18-0/+10
| | | | | | | | | | Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * pmic: pmic_mc34vr500: Add APIs to set/get SWx voltHou Zhiqiang2017-01-18-0/+105
| | | | | | | | | | | | Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * pmic: pmic_mc34vr500: Add a driver for the mc34vr500 pmicHou Zhiqiang2017-01-18-0/+206
| | | | | | | | | | | | | | | | | | This patch adds a simple pmic driver for the mc34vr500 pmic which is used in conjunction with the fsl T1 and LS1 series SoC. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: fsl-layerscape: Fix SECURE_BOOT configYork Sun2017-01-18-1/+4
| | | | | | | | | | | | | | | | | | | | | | Without a prompt in Kconfig, SECURE_BOOT cannot be selected by defconfig. The option was dropped unintentionally when defconfig files were cleaned up. Three targets were impacted ls1043ardb_SECURE_BOOT, ls2080ardb_SECURE_BOOT, ls2080aqds_SECURE_BOOT. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * LS2080A: Add validation of MC & DPC images.Udit Agarwal2017-01-18-3/+48
| | | | | | | | | | | | | | | | | | Add secure boot validation of MC, DPC images using esbc_validate command. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * SECURE_BOOT: Update bootscript and its hdr addressesUdit Agarwal2017-01-18-6/+6
| | | | | | | | | | | | | | | | | | Update bootscript and its hdr addresses for Layerscape Chasis 3 based platforms instead of individual SoCs. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * configs: ls1012a: enable driver model for eSDHCYangbo Lu2017-01-18-0/+6
| | | | | | | | | | | | | | Enable driver model for eSDHC on ls1012a rdb and qds boards. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls1012a: add eSDHC nodesYangbo Lu2017-01-18-0/+16
| | | | | | | | | | | | | | This patch is to add eSDHC nodes for ls1012a. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * mmc: fsl_esdhc: add 'fsl, esdhc' into of_match tableYangbo Lu2017-01-18-0/+1
| | | | | | | | | | | | | | | | This patch is to add 'fsl,esdhc' into of_match table to support driver model for QorIQ eSDHC. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * mmc: fsl_esdhc: make GPIO support optionalYangbo Lu2017-01-18-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | There would be compiling error as below when enable driver model for esdhc. undefined reference to `dm_gpio_get_value' undefined reference to `gpio_request_by_name_nodev' This patch is to make GPIO support optional with CONFIG_DM_GPIO. Because all boards of QorIQ platform don't need it and they just check register for CD/WP status, only some boards of i.MX platform require this. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8/fsl-lsch3: consolidate the clock system initializationHou Zhiqiang2017-01-18-8/+23
| | | | | | | | | | | | | | | | This patch binds the sys_info->freq_systembus to Platform PLL, and implements the IPs' clock function individually. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8/fsl-lsch2: refactor the clock system initializationHou Zhiqiang2017-01-18-29/+136
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Up to now, there are 3 kind of SoCs under Layerscape Chassis 2, like LS1043A, LS1046A and LS1012A. But the clocks tree has a lot of differences, for instance, the IP modules have different dividers to derive its clock from Platform PLL. And the core cluster PLL and platform PLL maybe have different reference clocks, such as LS1012A. Another problem is which clock/PLL should be described by sys_info->freq_systembus, it is confused in Layerscape Chissis 2. This patch is to bind the sys_info->freq_systembus to the Platform PLL, and handle the different divider of IP modules separately between different SoCs, and separate reference clocks of core cluster PLL and platform PLL. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * ARMv8/fsl-layerscape: Enable data coherency between cores in clusterHou Zhiqiang2017-01-18-0/+4
| | | | | | | | | | Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: Enable CPUECTLR.SMPEN for coherencyMingkai Hu2017-01-18-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For A53, data coherency is enabled only when the CPUECTLR.SMPEN bit is set. The SMPEN bit should be set before enabling the data cache. If not enabled, the cache is not coherent with other cores and data corruption could occur. For A57/A72, SMPEN bit enables the processor to receive instruction cache and TLB maintenance operations broadcast from other processors in the cluster. This bit should be set before enabling the caches and MMU, or performing any cache and TLB maintenance operations. Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * arm: layerscape: Enable UUID & GPT partition for NXP's ARM SoCPrabhakar Kushwaha2017-01-18-0/+44
| | | | | | | | | | | | | | | | | | | | Enable UUID and GPT partition support for NXP's ARM based SoCs i.e. LS1012A, LS1021A, LS1043A, LS1046A and LS2080A. Also enable DOS partition for LS1012AFRDM boards. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls1012: Enable CONFIG_DM_USB in defconfigsTang Yuantian2017-01-18-0/+3
| | | | | | | | | | | | | | | | Enables driver model flag CONFIG_DM_USB for LS1012A platform in defconfigs. Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls1012: added usb nodes in dtsTang Yuantian2017-01-18-0/+15
| | | | | | | | | | | | | | | | | | | | The LS1012A processor has two integrated USB controllers. One is USB2.0 controller, the other is USB3.0 controller that allow direct connection to the USB ports with appropriate protection circuitry and power supplies. Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8/fsl_lsch2: Add the OCRAM initializationHou Zhiqiang2017-01-18-0/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Clear the content to zero and the ECC error bit of OCRAM1/2. The OCRAM must be initialized to ZERO by the unit of 8-Byte before accessing it, or else it will generate ECC error. And the IBR has accessed the OCRAM before this initialization, so the ECC error status bit should to be cleared. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Pratiyush Srivastava <pratiyush.srivastava@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * ARMv8/fsl-layerscape: Correct the OCRAM sizeHou Zhiqiang2017-01-18-7/+9
| | | | | | | | | | | | | | | | | | The real size of OCRAM is 128KiB, so correct the size of OCRAM. And OCRAM reserved 2MiB space, then add a new macro to describe it, which is used for MMU setup. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * kconfig: move FSL_PCIE_COMPAT to platform KconfigHou Zhiqiang2017-01-18-12/+23
| | | | | | | | | | | | Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
| * pci: layerscape: remove unnecessary legacy codeMinghuan Lian2017-01-18-716/+1
| | | | | | | | | | | | | | | | | | | | All Layerscape SoCs have supported new PCIe driver based on DM. The lagecy PCIe driver code is unused and can be removed. Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls2080a: Enable PCIe in defconfigsMinghuan Lian2017-01-18-39/+28
| | | | | | | | | | | | | | | | | | The patch enables PCIe in ls2080a defconfigs and removes unused PCIe related macro defines. Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls1046a: Enable PCIe and E1000 in defconfigsMinghuan Lian2017-01-18-0/+48
| | | | | | | | | | | | | | | | The patch enables PCIe and E1000 in ls1046a related defconfigs. Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls1043a: Enable PCIe and E1000 in defconfigsMinghuan Lian2017-01-18-28/+66
| | | | | | | | | | | | | | | | | | The patch enables PCIe and E1000 in ls1043a defconfigs and removes unused PCIe related macro defines. Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * arm: ls1012a: Enable PCIe and E1000 in defconfigsMinghuan Lian2017-01-18-34/+13
| | | | | | | | | | | | | | | | | | The patch enables PCIe and E1000 in ls1012a defconfigs and removes unused PCIe related macro defines Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
generated by cgit v1.1 at 2024-07-07 19:40:23 +0000