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| * | defconfigs: am57xx_hs_evm: Add default OPTEE load addressAndrew F. Davis2016-12-09-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Currently we let U-Boot find a spot at the end of DRAM at runtime, this forces us to build an OPTEE image based on the size of DRAM for an EVM. Add a default address that works across all current AM57xx EVMs. Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | defconfigs: dra7xx_hs_evm: Add default OPTEE load addressAndrew F. Davis2016-12-09-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Currently we let U-Boot find a spot at the end of DRAM at runtime, this forces us to build an OPTEE image based on the size of DRAM for an EVM. Add a default address that works across all current DRA7xx EVMs. Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | davinci: omapl138_lcdk: fix bad NAND ECC configFabien Parent2016-12-09-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The configuration used to error correction was not in line with what linux and the ROM code is using. Fix it by using the correct configuration. Now u-boot and the SPL are able to read correctly anything written by them. Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | davinci: omapl138_lcdk: increase u-boot load sizeFabien Parent2016-12-09-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | A size of 0x200 seems way too short for u-boot. Increase the size to 512k. Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | cmd: pci: add option to parse and display BAR informationYehuda Yitschak2016-12-09-0/+83
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the PCI command only allows to see the BAR register values but not the size and actual base address. This little extension parses the BAR registers and displays the base, size and type of each BAR. Signed-off-by: Yehuda Yitschak <yehuday@marvell.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | spl: sandbox: Drop spl_board_announce_boot_device()Simon Glass2016-12-09-14/+3
| | | | | | | | | | | | | | | | | | This function is not used anymore. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | spl: uniphier: Drop spl_board_announce_boot_device()Simon Glass2016-12-09-5/+0
| | | | | | | | | | | | | | | | | | This function is not used anymore. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | spl: sunxi: Drop spl_board_announce_boot_device()Simon Glass2016-12-09-9/+0
| | | | | | | | | | | | | | | | | | This function is not used anymore. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | spl: Drop announce_boot_device()Simon Glass2016-12-09-83/+3
| | | | | | | | | | | | | | | | | | This task can be handled by inline code now. Drop this function. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | spl: Pass the loader into spl_load_image()Simon Glass2016-12-09-4/+4
| | | | | | | | | | | | | | | | | | | | | Rather than have this function figure out the correct loader again, pass it in as a parameter. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | spl: Move the loading code into its own functionSimon Glass2016-12-09-12/+29
| | | | | | | | | | | | | | | | | | | | | Create a boot_from_devices() function to handle trying each device. This helps to reduce the size of the already-large board_init_r() function. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | spl: Add a name to the SPL load-image methodsSimon Glass2016-12-09-21/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is useful to name each method so that we can print out this name when using the method. Currently this happens using a separate function. In preparation for unifying this, add a name to each method. The name is only available if we have libcommon support (i.e can use printf()). Signed-off-by: Simon Glass <sjg@chromium.org>
| * | spl: Use a single underscore in the SPL_LOAD_IMAGE_METHOD() macroSimon Glass2016-12-09-7/+7
| | | | | | | | | | | | | | | | | | | | | A double underscore is normally reserved for compiler predefines. Use a single underscore instead. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | am57xx: Set tps659038 PMIC GPIO7 pad mux value to POWERHOLDKeerthy2016-12-09-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GPIO7 pad mux should be programmed to POWERHOLD value as per board design. In cases where the PMIC is shut off the mux is set to GPIO7 mode. So during initialization to be on the safer side set the mode to POWERHOLD. Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | configs: omap5_uevm_defconfig: Enable LPAE modeKeerthy2016-12-09-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Enable Linear Physical Address Extension mode which is a prerequisite for hypervisor mode. Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | arm: armv7: add us timer for bootstagePatrick Delaunay2016-12-09-1/+6
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | solve issue when bootstage is used with armV7 generic timer first call of timer_get_boot_us() use the function get_timer() before timer initialization (arch.timer_rate_hz = 0) => div by 0 Commit-notes When I activate bootstage on ARMV7 architecture with platform using the generic armv7 timer defined in file ./arch/arm/cpu/armv7m/timer.c I have a issue because gd->arch.timer_rate_hz = 0 For me the get_timer() function should not used before timer_init (which initialize gd->arch.timer_rate_hz) at least for the ARMV7 timer. But in the init sequence, the first bootstage fucntion is called before timer_init and this function use the timer function. For me it is a error in the generic init sequence : mark_bootstage is called before timer_init. static init_fnc_t init_sequence_f[] = { .... arch_cpu_init_dm, mark_bootstage, /* need timer, go after init dm */ ... #if defined(CONFIG_ARM) || defined(CONFIG_MIPS) || \ defined(CONFIG_BLACKFIN) || defined(CONFIG_NDS32) || \ defined(CONFIG_SPARC) timer_init, /* initialize timer */ #endif ....... To solve the issue for all the paltform, we can move timer_init() call just before mark_bootstage() in this array... It should be ok for ARMV7 but I don't sure for other platform impacted - the other ARM platform or ARMV7 wich don't use generic timer - MIPS BLACKFIN NDS32 or SPARC and I don't sure of impact for other function called (board_early_init_f for example....) => This patch solve issue only in timer armv7 get_boot_us() can be called everytime without div by 0 issue (gd->arch.timer_rate_hz is not used) END Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay73@gmail.com>
| * Revert "Merge branch 'master' of git://www.denx.de/git/u-boot-microblaze"Tom Rini2016-12-09-54329/+251
| | | | | | | | | | This reverts commit 3edc0c252257e4afed163a3a74aba24a5509b198, reversing changes made to bb135a0180c31fbd7456021fb9700b49bba7f533.
| * Merge branch 'master' of git://www.denx.de/git/u-boot-microblazeTom Rini2016-12-09-251/+54329
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| | * net: xilinx: Use mdio_register_seq() to support multiple instancesMichal Simek2016-12-08-6/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | axi_emac, emaclite and gem have the same issue with registering multiple instances with mdio busses. mdio bus name has to be uniq but drivers are setting up only one name for all. Use mdio_register_seq() and pass dev->seq number to allow multiple mdio instances registration. Reported-by: Phani Kiran Kara <phanikiran.kara@gmail.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Series-to: u-boot Series-cc: Phani Kiran Kara <phanikiran.kara@gmail.com>
| | * common: miiphyutil: Add helper function for mdio bus nameMichal Simek2016-12-08-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The most of ethernet drivers are using this mdio registration sequence. strcpy(priv->bus->name, "emac"); mdio_register(priv->bus); Where driver can be used only with one MDIO bus because only unique name should be used. Other drivers are using unique device name for MDIO registration to support multiple instances. snprintf(priv->bus->name, sizeof(bus->name), "%s", name); With DM dev->seq is used more even in logs (like random MAC address generation: printf("\nWarning: %s (eth%d) using random MAC address - %pM\n", dev->name, dev->seq, pdata->enetaddr); ) where eth%d prefix is used. Simplify driver code to register mdio device with dev->seq number to simplify mdio registration and reduce code duplication across all drivers. With DM_SEQ_ALIAS enabled dev->seq reflects alias setting. Signed-off-by: Michal Simek <michal.simek@xilinx.com> --- For example: Board: Xilinx Zynq Net: ZYNQ GEM: e000b000, phyaddr 7, interface rgmii-id Warning: ethernet@e000b000 (eth0) using random MAC address - 7a:fc:90:53:6a:41 eth0: ethernet@e000b000ZYNQ GEM: e000c000, phyaddr ffffffff, interface rgmii-id Warning: ethernet@e000c000 (eth3) using random MAC address - 1a:ff:d7:1a:a1:b2 , eth3: ethernet@e000c000 ** Bad device size - mmc 0 ** Checking if uenvcmd is set ... Hit any key to stop autoboot: 0 Zynq> mdio list eth0: 17 - Marvell 88E1111S <--> ethernet@e000b000 eth3: 17 - Marvell 88E1111S <--> ethernet@e000c000 Zynq>
| | * ARM64: zynqmp: Add updated psu_init_gpl* filesMichal Simek2016-12-08-0/+53957
| | | | | | | | | | | | | | | | | | With origin files there was an issue with serdes setting for SCSI. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| | * zynqmp worksMichal Simek2016-12-08-130/+82
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| | * ARM: zynq: Replace dram_init* functions with board_init_f safe onesNathan Rossi2016-12-08-98/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The dram_init* functions for the zynq board are not safe for use from the board_init_f stage due to its use of the 'tmp' static variable. This incorrect use of a static variable was causing rare issues where the dram_init function would overwrite some parts the __rel_dyn section which caused obscure failures. Using the zynq_zybo configuration, U-Boot would generate the following error during image load. This was caused due to dram_init overwriting the relocations for the "image" variable within the do_bootm function. Out of coincidence the un-initialized memory has a compression type which is the same as the value for the relocation type R_ARM_RELATIVE. Uncompressing Invalid Image ... Unimplemented compression type 23 It should be noted that this is just one way the issue could surface, other cases my not be observed in normal boot flow. This change removes the existing code and copies the implementation of the dram_init and dram_init_banksize from the arch/arm/mach-uniphier/dram_init.c source. This version of these functions does not use static variables and behaves the same (reading banks from fdt, and using the first bank as the ram_size). Signed-off-by: Nathan Rossi <nathan@nathanrossi.com> Fixes: 758f29d0f8 ("ARM: zynq: Support systems with more memory banks") Cc: Michal Simek <monstr@monstr.eu> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| | * travis-ci: Add zynq_zc702 target supportMichal Simek2016-12-08-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Michal Simek <michal.simek@xilinx.com> Use embded option because of qemu Use my repo till Stephen merge it. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| | * tools: mkimage: Use fstat instead of stat to avoid malicious hacksMichal Simek2016-12-08-8/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch is fixing: "tools: mkimage: Check if file is regular file" (sha1: 56c7e8015509312240b1ee15f2ff74510939a45d) which contains two issues reported by Coverity Unchecked return value from stat and incorrect calling sequence where attack can happen between calling stat and fopen. Using pair in opposite order (fopen and fstat) is fixing this issue because fstat is using the same file descriptor (FILE *). Also fixing issue with: "tools: mkimage: Add support for initialization table for Zynq and ZynqMP" (sha1: 3b6460809c2a28360029c1c48247648fac4455c9) where file wasn't checked that it is regular file. Reported-by: Coverity (CID: 154711, 154712) Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com> Series-to: trini Series-cc: u-boot
| | * block: Move ceva driver to DMMichal Simek2016-12-08-19/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch also includes ARM64 zynqmp changes: - Remove platform non DM initialization - Remove hardcoded sata base address Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> Series-to: sjg, agraf@suse.de Series-cc: uboot Series-version: 4 Series-changes: 2 - make ceva_init_sata static - Move SATA_CEVA to defconfig - Initalized max_lun and max_id platdata Series-changes: 3 - Extend Kconfig help description - sort dm.h - Remove SPL undefinition from board file - Fix Kconfig dependecies
| | * dm: Add support for scsi/sata based devicesMichal Simek2016-12-08-13/+165
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All sata based drivers are bind and corresponding block device is created. Based on this find_scsi_device() is able to get back block device based on scsi_curr_dev pointer. intr_scsi() is commented now but it can be replaced by calling find_scsi_device() and scsi_scan(). scsi_dev_desc[] is commented out but common/scsi.c heavily depends on it. That's why CONFIG_SYS_SCSI_MAX_DEVICE is hardcoded to 1 and symbol is reassigned to a block description allocated by uclass. There is only one block description by device now but it doesn't need to be correct when more devices are present. scsi_bind() ensures corresponding block device creation. uclass post_probe (scsi_post_probe()) is doing low level init. SCSI/SATA DM based drivers requires to have 64bit base address as the first entry in platform data structure to setup mmio_base. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> Series-changes: 2 - Use CONFIG_DM_SCSI instead of mix of DM_SCSI and DM_SATA Ceva sata has never used sata commands that's why keep it in SCSI part only. - Separate scsi_scan() for DM_SCSI and do not change cmd/scsi.c - Extend platdata Series-changes: 3 - Fix scsi_scan return path - Fix header location uclass-internal.h - Add scsi_max_devs under !DM_SCSI - Add new header device-internal because of device_probe() - Redesign block device creation algorithm - Use device_unbind in error path - Create block device with id and lun numbers (lun was there in v2) - Cleanup dev_num initialization in block device description with fixing parameters in blk_create_devicef - Create new Kconfig menu for SATA/SCSI drivers - Extend description for DM_SCSI - Fix Kconfig dependencies - Fix kernel doc format in scsi_platdata - Fix ahci_init_one - vendor variable Series-changes: 4 - Fix Kconfig entry - Remove SPL ifdef around SCSI uclass - Clean ahci_print_info() ifdef logic
| * | net/phy/vitesse: Rework RGMII skew configuration for VSC8601Alex2016-12-08-19/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The VSC8601 config tried to add an RGMII skew based on #defines that no config defines. That's quite an ugly way to do it. Since the skew is only needed on RGMII interfaces, check the interface mode at runtime, and apply the settings accordingly. Tested on custom board with AM3352 SOC and VSC801 PHY. Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: usb: r8152: Use ALLOC_CACHE_ALIGN_BUFFER() to allocate the buffersStefan Roese2016-12-08-6/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Testing on theadorable (Armada XP) has shown, that using this driver results in many cache misaligned warning, such as: CACHE: Misaligned operation at range [7fabd8fc, 7fabd900] This patch now uses the ALLOC_CACHE_ALIGN_BUFFER() macro to allocate the buffers on a cache aligned boundary. This fixes all warnings seen on the Armada XP platform. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Ted Chen <tedchen@realtek.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: fman: fix 2.5G SGMII settingsshaohui xie2016-12-08-10/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | The settings for 2.5G SGMII are wrong, which the 2.5G case is missed in set_if_mode(), and the serdes PCS configuration are wrong, this patch uses the correct settings took from Linux. Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: phy: realtek: Only force master mode on rtl8211b/coliver@schinagl.nl2016-12-08-8/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 525d187af ("net: phy: Optionally force master mode for RTL PHY") added the define to force the PHY into master mode. Unfortunatly this is an all or nothing switch. So it applies to either all PHY's or no PHY's. The bug that define tried to solve was a buggy PLL in the RTL8211C only. The Olimex OLinuXino Lime2 has gotten an upgrade where the PHY was replaced with an RTL8211E. With this define however, both lime2 boards are either forced to master mode or not. We could of course have a binary for each board, but the following patch fixes this by adding a 'quirk' to the flags to the rtl8211b and rtl8211c only. It is now possible to force master mode, but only have it apply to the rtl8211b and rtl8211c. Signed-off-by: Olliver Schinagl <oliver@schinagl.nl> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: phy: realtek: make define more consistentoliver@schinagl.nl2016-12-08-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | All internal defines in the realtek phy are with a small X, except MIIM_RTL8211X_CTRL1000T_MASTER. Make this more consistent Signed-off-by: Olliver Schinagl <oliver@schinagl.nl> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: phy: realtek: Use the BIT() macrooliver@schinagl.nl2016-12-08-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | The BIT macro is the preferred method to set bits. This patch adds the bit macro and converts bit invocations. Signed-off-by: Olliver Schinagl <oliver@schinagl.nl> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: phy: micrel: Fix error handlingMarek Vasut2016-12-08-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the following error, the $ret variable handling must be part of the loop, while due to the missing parenthesis it was not. drivers/net/phy/micrel.c: In function ‘ksz9021_of_config’: drivers/net/phy/micrel.c:303:2: warning: this ‘for’ clause does not guard... [-Wmisleading-indentation] for (i = 0; i < ARRAY_SIZE(ofcfg); i++) ^~~ drivers/net/phy/micrel.c:305:3: note: ...this statement, but the latter is misleadingly indented as if it is guarded by the ‘for’ if (ret) ^~ drivers/net/phy/micrel.c: In function ‘ksz9031_of_config’: drivers/net/phy/micrel.c:411:2: warning: this ‘for’ clause does not guard... [-Wmisleading-indentation] for (i = 0; i < ARRAY_SIZE(ofcfg); i++) ^~~ drivers/net/phy/micrel.c:413:3: note: ...this statement, but the latter is misleadingly indented as if it is guarded by the ‘for’ if (ret) ^~ Signed-off-by: Marek Vasut <marex@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2016-12-06-0/+81
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| | * | usb: xhci-pci: Add DM supportStefan Roese2016-12-06-0/+81
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds DM support to the xHCI PCI driver. Enabling its use e.g. in x86 platforms. Status: On the congatec BayTrail SoM, xHCI still does not work correctly with this patch. Some internal timeouts lead to resets (BUG). Additional work is needed here. I'm posting this version as WIP so that other developers interested in this support might use it as a start. I might get back to it in a few weeks as well. Signed-off-by: Stefan Roese <sr@denx.de> Cc: George McCollister <george.mccollister@gmail.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Marek Vasut <marex@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | MAINTAINERS: Fix ALTERA SOCFPGA FilesJagan Teki2016-12-06-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace arch/arm/cpu/armv7/socfpga/ path with arch/arm/mach-socfpga/ and removed board file path since board/altera has different boards with relevant board maintainers. Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@openedev.com>
| * | MAINTAINERS: socfpga: update email address for Dinh NguyenDinh Nguyen2016-12-06-4/+5
| | | | | | | | | | | | | | | | | | | | | With the acquisition of Altera by Intel, my Altera email may be going away soon. Update the contact to a more reliable address. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
| * | qts-filter.sh: strip DOS line endings and handle continuation linesBill Randle2016-12-06-15/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | Some Altera Quartus generated files have long lines that are split with a '\' at the end of the line. It also wOn Windows, rites files in DOS format, which can confuse some of the processing scripts in this file. This patch solves both issues. Signed-off-by: Bill Randle <bill.randle@gmail.com> Cc: Marek Vasut <marex@denx.de>
| * | ARM: socfpga: Add boot0 hook to prevent SPL corruptionMarek Vasut2016-12-06-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Valid Altera SoCFPGA preloader image must contain special data at offsets 0x40, 0x44, 0x48 and valid instructions at address 0x4c or 0x50. These addresses are by default used by U-Boot's vector table and a piece of reset handler, thus a valid preloader corrupts those addresses slightly. While this works most of the time, this can and does prevent the board from rebooting sometimes and triggering this issue may even depend on compiler. The problem is that when SoCFPGA performs warm reset, it checks the addresses 0x40..0x4b in SRAM for a valid preloader signature and header checksum. If those are found, it jumps to address 0x4c or 0x50 (this is unclear). These addresses are populated by the first few instructions of arch/arm/cpu/armv7/start.S: ffff0040 <data_abort>: ffff0040: ebfffffe bl ffff0040 <data_abort> ffff0044 <reset>: ffff0044: ea000012 b ffff0094 <save_boot_params> ffff0048 <save_boot_params_ret>: ffff0048: e10f0000 mrs r0, CPSR ffff004c: e200101f and r1, r0, #31 ffff0050: e331001a teq r1, #26 Without this patch, the CPU will enter the code at 0xffff004c or 0xffff0050 , at which point the value of r0 and r1 registers is undefined. Moreover, jumping directly to the preloader entry point at address 0xffff0000 will also fail, because address 0xffff004. is invalid and contains the preloader magic. Add BOOT0 hook which reserves the area at offset 0x40..0x5f and populates offset 0x50 with jump to the entry point. This way, the preloader signature is stored in reserved space and can not corrupt the SPL code. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Stefan Roese <sr@denx.de> Tested-by: Dinh Nguyen <dinguyen@opensource.altera.com>
| * | socfpga: add support for Terasic DE1-SoC boardAnatolij Gustschin2016-12-06-0/+1528
| |/ | | | | | | | | | | | | | | Add CycloneV based Terasic DE1-SoC board. The board boots from SD/MMC. Ethernet and USB host is supported. Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Marek Vasut <marex@denx.de>
| * Prepare v2017.01-rc1Tom Rini2016-12-05-3/+3
| | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com>
| * Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-12-05-62/+233
| |\
| | * armv8: QSPI: Add AHB bus 16MB+ size supportYuan Yao2016-12-05-0/+55
| | | | | | | | | | | | | | | | | | | | | | | | The default configuration for QSPI AHB bus can't support 16MB+. But some flash on NXP layerscape board are more than 16MB. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| | * fsl/usb: enable the errata-a005697 for ls1012ajerry.huang@nxp.com2016-12-05-0/+4
| | | | | | | | | | | | | | | | | | | | | Enable the errata-a005697 for ls1012a Signed-off-by: Changming Huang <jerry.huang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| | * ls1021a: QSPI: update the node for QSPI supportYuan Yao2016-12-05-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add the name for register space and memory space. <0x1550000 0x10000 > is the QSPI register space. <0x40000000 0x4000000> is the QSPI memory space. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| | * armv8: ls2080a: Add serdes1 protocol 0x3b supportPriyanka Jain2016-12-05-0/+1
| | | | | | | | | | | | | | | Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| | * fsl/ddr: Add erratum_a009942_check_cpo and clean related erratumShengzhou Liu2016-12-05-38/+155
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - add additional function erratum_a009942_check_cpo to check if the board needs tuning CPO calibration for optimal setting. - move ERRATUM_A009942(with revision to check cpo_sample option) from fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts. - move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c - remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> [YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500] Reviewed-by: York Sun <york.sun@nxp.com>
| | * fsl/ddr: Fix compiling warningShengzhou Liu2016-12-05-32/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | Fix following warning in case multiple erratum macro was not defined. warning: unused variable 'tmp' warning: unused variable 'ddr_freq' Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | travis-ci: Build mvebu boards (arm & aarch64) in separate jobStefan Roese2016-12-05-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Its easier to watch the output of the build process when the platforms specific boards are grouped in a separate job. This patch adds a job for all mvebu boards (arm and aarch64). Signed-off-by: Stefan Roese <sr@denx.de> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
generated by cgit v1.1 at 2024-11-10 04:55:29 +0000