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* | | mmc: Extend dependencies for zynq sdhciMichal Simek2016-12-22-1/+1
| | | | | | | | | | | | | | | | | | | | | There is hard dependency on BLK and DM_MMC which is also used by ATMEL and ROCKCHIP. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | mmc: spear: remove the entire spear_sdhci.c fileJaehoon Chung2016-12-22-28/+0
|/ / | | | | | | | | | | | | | | | | Remove the entire spear_sdhci.c file. There is no use case. This is dead codes. Also there is no place to call "spear_sdhci_init()" anywhere. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | arm64: mvebu: Fix A8K memory mapping and add documentationKonstantin Porotchkin2016-12-21-13/+101
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the MMU mapping for A8K device family: - Separate A7K and A8K memory mappings - Fix memory regions by including IO mapping for all 3 PCIe interfaces existing on each connected CP110 controller Add A8K memory mapping documentation with all regions configured by Marvell ATF. Change-Id: I9c930569b1853900f5fba2d5db319b092cc7a2a6 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com>
* | Merge git://git.denx.de/u-boot-mpc85xxTom Rini2016-12-20-25/+36
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| * | powerpc: Retain compatible property for L2 cacheChris Packham2016-12-20-25/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | When setting the compatible property for the L2 cache ensure that we follow the documented binding by setting both "<chip>-l2-cache-controller" and "cache" as values. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | | Merge branch 'master' of git://www.denx.de/git/u-boot-microblazeTom Rini2016-12-20-263/+346
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| * | | ARM64: zynqmp: Replace board specific with generic memory bank decodingNathan Rossi2016-12-20-109/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The dram_init and dram_init_banksize functions were using a board specific implementation for decoding the memory banks from the fdt. This board specific implementation uses a static variable 'tmp' which makes these functions unsafe for execution from within the board_init_f context. This change makes the dram_init* functions use a generic implementation of decoding and populating memory bank and size data. Signed-off-by: Nathan Rossi <nathan@nathanrossi.com> Fixes: 8d59d7f63b ("ARM64: zynqmp: Read RAM information from DT") Cc: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | ARM: zynq: Replace board specific with generic memory bank decodingNathan Rossi2016-12-20-109/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The dram_init and dram_init_banksize functions were using a board specific implementation for decoding the memory banks from the fdt. This board specific implementation uses a static variable 'tmp' which makes these functions unsafe for execution from within the board_init_f context. This unsafe use of a static variable was causing a specific bug when using the zynq_zybo configuration, U-Boot would generate the following error during image load. This was caused due to dram_init overwriting the relocations for the 'image' variable within the do_bootm function. Out of coincidence the un-initialized memory has a compression type which is the same as the value for the relocation type R_ARM_RELATIVE. Uncompressing Invalid Image ... Unimplemented compression type 23 It should be noted that this is just one way the issue could surface, other cases my not be observed in normal boot flow. Depending on the size of various sections, and location of relocations within __rel_dyn and the compiler/linker the outcome of this bug can differ greatly. This change makes the dram_init* functions use a generic implementation of decoding and populating memory bank and size data. Signed-off-by: Nathan Rossi <nathan@nathanrossi.com> Fixes: 758f29d0f8 ("ARM: zynq: Support systems with more memory banks") Cc: Michal Simek <monstr@monstr.eu> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | fdt: add memory bank decoding functions for board setupNathan Rossi2016-12-20-0/+90
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add two functions for use by board implementations to decode the memory banks of the /memory node so as to populate the global data with ram_size and board info for memory banks. The fdtdec_setup_memory_size() function decodes the first memory bank and sets up the gd->ram_size with the size of the memory bank. This function should be called from the boards dram_init(). The fdtdec_setup_memory_banksize() function decode the memory banks (up to the CONFIG_NR_DRAM_BANKS) and populates the base address and size into the gd->bd->bi_dram array of banks. This function should be called from the boards dram_init_banksize(). Signed-off-by: Nathan Rossi <nathan@nathanrossi.com> Cc: Simon Glass <sjg@chromium.org> Cc: Michal Simek <monstr@monstr.eu> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | ARM64: zynqmp: Add one empty line between license and nodesMichal Simek2016-12-20-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Sync with Linux kernel. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | ARM64: zynqmp: Add missing SPL dependency for boot.bin generationMichal Simek2016-12-20-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | boot.bin file is generated only when SPL is selected. Reflect this depency in Kconfig. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | common: Fix logic in fpga programmingMichal Simek2016-12-20-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Stop boot process if fpga programming fails. Without this patch boot process continues even if fpga programming failed. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | gpio: zynq: Remove empty lineMichal Simek2016-12-20-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | Trivial coding style fix. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | block: Move ceva driver to DMMichal Simek2016-12-20-19/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch also includes ARM64 zynqmp changes: - Remove platform non DM initialization - Remove hardcoded sata base address Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | dm: Add support for scsi/sata based devicesMichal Simek2016-12-20-13/+165
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All sata based drivers are bind and corresponding block device is created. Based on this find_scsi_device() is able to get back block device based on scsi_curr_dev pointer. intr_scsi() is commented now but it can be replaced by calling find_scsi_device() and scsi_scan(). scsi_dev_desc[] is commented out but common/scsi.c heavily depends on it. That's why CONFIG_SYS_SCSI_MAX_DEVICE is hardcoded to 1 and symbol is reassigned to a block description allocated by uclass. There is only one block description by device now but it doesn't need to be correct when more devices are present. scsi_bind() ensures corresponding block device creation. uclass post_probe (scsi_post_probe()) is doing low level init. SCSI/SATA DM based drivers requires to have 64bit base address as the first entry in platform data structure to setup mmio_base. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | ARM: dt: zynq: Add labels to cpu nodes to allow overriding OPPs.Moritz Fischer2016-12-20-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | By adding labels to the cpu nodes in the dtsi, a dts that includes it can change the OPPs by referencing the cpu0 through the label. [Based on linux (400b6a0cbef55d1ae32808eaa1ef1c28820bf6ac)] Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: u-boot@lists.denx.de Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | net: xilinx: Use mdio_register_seq() to support multiple instancesMichal Simek2016-12-20-6/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | axi_emac, emaclite and gem have the same issue with registering multiple instances with mdio busses. mdio bus name has to be uniq but drivers are setting up only one name for all. Use mdio_register_seq() and pass dev->seq number to allow multiple mdio instances registration. Reported-by: Phani Kiran Kara <phanikiran.kara@gmail.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | | common: miiphyutil: Add helper function for mdio bus nameMichal Simek2016-12-20-0/+21
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The most of ethernet drivers are using this mdio registration sequence. strcpy(priv->bus->name, "emac"); mdio_register(priv->bus); Where driver can be used only with one MDIO bus because only unique name should be used. Other drivers are using unique device name for MDIO registration to support multiple instances. snprintf(priv->bus->name, sizeof(bus->name), "%s", name); With DM dev->seq is used more even in logs (like random MAC address generation: printf("\nWarning: %s (eth%d) using random MAC address - %pM\n", dev->name, dev->seq, pdata->enetaddr); ) where eth%d prefix is used. Simplify driver code to register mdio device with dev->seq number to simplify mdio registration and reduce code duplication across all drivers. With DM_SEQ_ALIAS enabled dev->seq reflects alias setting. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | Merge git://git.denx.de/u-boot-dmTom Rini2016-12-20-300/+3709
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| * | | binman: Drop microcode features from ifdtoolSimon Glass2016-12-20-249/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that binman supports creating images with microcode, drop the code from ifdtool. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * | | x86: Use binman all x86 boardsSimon Glass2016-12-20-42/+83
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change x86 boards to use binman to produce the ROM. This involves adding the image definition to the device tree and using it in the Makefile. The existing ifdtool features are no-longer needed. Note that the u-boot.dtsi file is common and is used for all x86 boards which use microcode. A separate emulation-u-boot-dtsi is used for the others. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * | | sunxi: Use binman for sunxi boardsSimon Glass2016-12-20-6/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move sunxi boards to use binman. This involves adding the image definition to the device tree and using it in the Makefile. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | | tegra: Use a U-Boot-specific .dtsi fileSimon Glass2016-12-20-4/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the new device-tree rules it is possible to put device-tree changes needed by U-Boot into their own file. As an example of this approach, move Tegra over to use it. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | binman: Automatically include a U-Boot .dtsi fileSimon Glass2016-12-20-1/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For boards that need U-Boot-specific additions to the device tree, it is a minor annoyance to have to add these each time the tree is synced with upstream. Add a means to include a file (e.g. u-boot.dtsi) automatically into the .dts file before it is compiled. The file uses is the first one that exists in this list: arch/<arch>/dts/<board.dts>-u-boot.dtsi arch/<arch>/dts/<soc>-u-boot.dtsi arch/<arch>/dts/<cpu>-u-boot.dtsi arch/<arch>/dts/<vendor>-u-boot.dtsi arch/<arch>/dts/u-boot.dtsi Signed-off-by: Simon Glass <sjg@chromium.org> Suggested-by: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * | | binman: Allow configuration options to be used in .dts filesSimon Glass2016-12-20-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is sometimes useful to be able to reference configuration options in a device tree source file. Add the necessary includes so that this works. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * | | binman: Add a build rule for binmanSimon Glass2016-12-20-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a standard command definition for binman so that it can be used in makefiles. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * | | binman: Add support for building x86 images with FSP/CMCSimon Glass2016-12-20-0/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for two more from the inexhaustible supply of x86 binary blob types. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * | | binman: Add support for building x86 ROMs with SPLSimon Glass2016-12-20-1/+315
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When building for 64-bit x86 we need an SPL binary in the ROM. Add support for this. Also increase entry test code coverage to 100%. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * | | binman: Add support for u-boot.img as an input binarySimon Glass2016-12-20-0/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add an entry type for u-boot.img (a legacy U-Boot image) and a simple test. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * | | binman: Add support for building x86 ROMsSimon Glass2016-12-20-3/+760
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The structure of x86 ROMs is pretty complex. There are various binary blobs to place in the image. Microcode requires special handling so that it is available to very early code and can be used without any memory whatsoever. Add support for the various entry types that are currently needed, along with some tests. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * | | binman: Add basic entry types for U-BootSimon Glass2016-12-20-0/+1080
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add entries to support some standard U-Boot binaries, such as u-boot.bin, u-boot.dtb, etc. Also add some tests for these. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * | | binman: Introduce binman, a tool for building binary imagesSimon Glass2016-12-20-0/+1255
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds the basic code for binman, including command parsing, processing of entries and generation of images. So far no entry types are supported. These will be added in future commits as examples of how to add new types. See the README for documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-i2cTom Rini2016-12-20-2/+2
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| * | i2c: mv_i2c.c: Correct address endiannessBradley Bolen2016-12-19-2/+2
| |/ | | | | | | | | | | | | | | | | | | 0c0f719ad2f46c8566a56daee37ebdb7c078c3b1 accidentally changed the endianness of the i2c read and write addresses. This was noticable when accessing EEPROMs that use 2 byte addressing as the LSB was being sent first. Signed-off-by: Bradley Bolen <bradleybolen@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
* | Prepare v2017.01-rc2Tom Rini2016-12-19-1/+1
| | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com>
* | tools: mxsimage: Fix build with OpenSSL 1.1.xMarek Vasut2016-12-19-34/+70
| | | | | | | | | | | | | | | | | | | | The EVP_MD_CTX and EVP_CIPHER_CTX are made opaque since 1.1.x , so instead of embedding them directly into struct sb_image_ctx and initializing them using EVP_*_CTX_init(), we use pointers and allocate the crypto contexts using EVP_*_CTX_new(). Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com>
* | ARM: mxs: Remove unused variable warningMarek Vasut2016-12-19-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Shuffle the macros around a little to remove the following warning when building for i.MX28: arch/arm/cpu/arm926ejs/mxs/spl_boot.c:44:26: warning: ‘iomux_boot’ defined but not used [-Wunused-const-variable=] static const iomux_cfg_t iomux_boot[] = { ^~~~~~~~~~ Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Stefano Babic <sbabic@denx.de>
* | serial: 16550: Add Ingenic JZ4780 supportMarek Vasut2016-12-19-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | Add compatibility string for the Ingenic JZ4780 SoC, the necessary UART enable bit into FCR and register shift. Neither are encoded in the DTS coming from Linux, so we need to support it this way. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | serial: 16550: Add port type as driver dataMarek Vasut2016-12-19-10/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add driver data to each compatible string to identify the type of the port. Since all the ports in the driver are entirely compatible with 16550 for now, all are marked with PORT_NS16550. But, there are ports which have specific quirks, like the JZ4780 UART, which do not have any DT property to denote the quirks. Instead, Linux uses the compatible string to discern such ports and enable the necessary quirks. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org>
* | serial: 16550: Add getfcr accessorMarek Vasut2016-12-19-2/+17
| | | | | | | | | | | | | | | | | | | | | | Add function which allows fetching the default FCR register setting from platform data for DM , while retaining old behavior for non-DM by returning UART_FCRVAL. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2016-12-18-473/+16818
|\ \ | |/ |/| | | | | | | Migrate CONFIG_ARCH_USE_MEMSET/MEMCPY with this merge. Signed-off-by: Tom Rini <trini@konsulko.com>
| * imx6: icorem6_rqs: Add FEC supportJagan Teki2016-12-16-0/+18
| | | | | | | | | | | | | | | | | | Add FEC support for Engicam i.CoreM6 RQS modules. Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * arm: dts: imx6qdl-icore-rqs: Add FEC nodeJagan Teki2016-12-16-0/+46
| | | | | | | | | | | | | | | | | | Add FEC node for Engicam i.CoreM6 RQS modules. Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * imx6: geam6ul: Add FEC supportJagan Teki2016-12-16-0/+17
| | | | | | | | | | | | | | | | | | Add FEC support for Engicam GEAM6UL module. Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * arm: dts: imx6ul-geam: Add FEC nodeJagan Teki2016-12-16-0/+21
| | | | | | | | | | | | | | | | | | Add FEC node for Engicam GEAM6UL module. Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * imx6: icorem6_rqs: Add I2C supportJagan Teki2016-12-16-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add I2C support for Engicam i.CoreM6 RQS modules. icorem6qdl-rqs> i2c bus Bus 0: i2c@021a0000 Bus 1: i2c@021a4000 Bus 2: i2c@021a8000 icorem6qdl-rqs> i2c dev 0 Setting bus to 0 icorem6qdl-rqs> i2c speed 100000 Setting bus speed to 100000 Hz icorem6qdl-rqs> i2c probe Valid chip addresses: 4F icorem6qdl-rqs> i2c md 4F 0xff 00ff: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................ icorem6qdl-rqs> i2c bus Bus 0: i2c@021a0000 (active 0) 4f: generic_4f, offset len 1, flags 0 Bus 1: i2c@021a4000 Bus 2: i2c@021a8000 Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * arm: dts: imx6qdl-icore-rqs: Add I2C node'sJagan Teki2016-12-16-0/+41
| | | | | | | | | | | | | | | | | | Add I2C nodes for Engicam i.CoreM6 RQS modules. Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * imx6: icorem6: Rename engicam icorem6 defconfig filesJagan Teki2016-12-16-14/+100
| | | | | | | | | | | | | | | | | | | | Rename defconfig files for better compatible with respective board names and dts files. Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * arm: imx6q: Add Engicam i.CoreM6 Solo/Duallite RQS Starter Kit initial supportJagan Teki2016-12-16-2/+95
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Boot from MMC: ------------- U-Boot SPL 2016.11-rc2-g217bd8e-dirty (Nov 08 2016 - 22:56:07) Trying to boot from MMC1 U-Boot 2016.11-rc2-g217bd8e-dirty (Nov 08 2016 - 22:56:07 +0530) CPU: Freescale i.MX6DL rev1.3 at 792 MHz Reset cause: POR Model: Engicam i.CoreM6 DualLite/Solo RQS Starter Kit DRAM: 512 MiB MMC: FSL_SDHC: 0 *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: CPU Net Initialization Failed No ethernet found. Hit any key to stop autoboot: 0 icorem6qdl-rqs> Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * arm: imx6q: Add Engicam i.CoreM6 Quad/Dual RQS Starter Kit initial supportJagan Teki2016-12-16-0/+760
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Boot from MMC: ------------- U-Boot SPL 2016.11-rc2-g217bd8e-dirty (Nov 08 2016 - 22:59:44) Trying to boot from MMC1 U-Boot 2016.11-rc2-g217bd8e-dirty (Nov 08 2016 - 22:59:44 +0530) CPU: Freescale i.MX6D rev1.2 at 792 MHz Reset cause: POR Model: Engicam i.CoreM6 Quad/Dual RQS Starter Kit DRAM: 512 MiB MMC: FSL_SDHC: 0 *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: CPU Net Initialization Failed No ethernet found. Hit any key to stop autoboot: 0 icorem6qdl-rqs> Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
generated by cgit v1.1 at 2024-07-17 03:27:33 +0000