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| * mx6: soc: Set the VDDSOC at 1.175 VFabio Estevam2014-01-02-1/+1
| | | | | | | | | | | | | | | | | | | | mx6 datasheet specifies that the minimum VDDSOC at 792 MHz is 1.15 V. Add a 25 mV margin and set it to 1.175V. This also matches the VDDSOC voltages for 792MHz operation that the kernel configures: http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/tree/arch/arm/mach-mx6/cpu_op-mx6.c?h=imx_3.0.35_4.1.0 Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * mx6: soc: Clear the LDO ramp values up prior to setting the LDO voltagesFabio Estevam2014-01-02-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Since ROM may modify the LDO ramp up time according to fuse setting, it is safer to reset the ramp up field to its default value of 00: 00: 64 cycles of 24MHz clock; 01: 128 cycles of 24MHz clock; 02: 256 cycles of 24MHz clock; 03: 512 cycles of 24MHz clock; Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * mx6: soc: Staticize set_vddsoc()Fabio Estevam2014-01-02-3/+1
| | | | | | | | | | | | set_vddsoc() is not used anywhere else, so make it static. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * mx6sabre_common.h: Add CONFIG_CMD_FUSE supportFabio Estevam2014-01-02-0/+5
| | | | | | | | | | | | | | Add CONFIG_CMD_FUSE option, so that the fuse API can be used. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
| * doc: README.fuse: Add an example on how to use the fuse API on mx6qFabio Estevam2014-01-02-0/+76
| | | | | | | | | | | | | | | | | | | | When using the fuse API in U-boot user must calculate the 'bank' and 'word' values. Provide a real example on how to calculate such values for the mx6q. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
| * MX6: fix sata compilation for i.MX6Stefano Babic2013-12-19-1/+2
| | | | | | | | | | | | | | Commit 164d98466103a46b7c881149e92ec2a28a6375be breaks board with SATA support, because sata is not compiled. Signed-off-by: Stefano Babic <sbabic@denx.de>
| * imx6: fix random hang when download by usbFrank Li2013-12-17-0/+2
| | | | | | | | | | | | | | | | ROM did not invalidate L1 cache when download by usb Need invalidate L1 cache before enable cache Signed-off-by: Huang yongcai <b20788@freescale.com> Signed-off-by: Frank Li <Frank.Li@freescale.com>
| * ARM: mxs: tools: Fix errno handling in strtoul() invocationMarek Vasut2013-12-17-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to NOTE in strtoul(3), the errno must be zeroed before strtoul() is called. Zero the errno. The NOTE reads as such: Since strtoul() can legitimately return 0 or ULONG_MAX (ULLONG_MAX for strtoull()) on both success and failure, the calling program should set errno to 0 before the call, and then determine if an error occurred by checking whether errno has a nonzero value after the call. This issue was detected on Fedora 19 with glibc 2.17 . Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Tom Rini <trini@ti.com>
| * mx6sabresd: Fix LVDS width and color formatFabio Estevam2013-12-17-3/+3
| | | | | | | | | | | | | | | | mx6sabresd boards have a 18-bit LVDS data width and the correct color format is RGB666. Suggested-by: Liu Ying <Ying.Liu@freescale.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * mx6sabresd: Allow probing HSYNC, VSYNC and DISP_CLK signalsFabio Estevam2013-12-17-0/+9
| | | | | | | | | | | | | | | | HSYNC, VSYNC and DISP_CLK are very useful display signals for debugging. Configure them as active pins. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * mx6: clock: Fix the calculation of PLL_ENET frequencyFabio Estevam2013-12-17-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the mx6 quad reference manual, the DIV_SELECT field of register CCM_ANALOG_PLL_ENETn has the following meaning: "Controls the frequency of the ethernet reference clock. - 00 - 25MHz - 01 - 50MHz - 10 - 100MHz - 11 - 125MHz" Current logic does not handle the 25MHz case correctly, so fix it. Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * ARM: mx53: video: Add IPUv3 LCD support for M53EVKMarek Vasut2013-12-17-0/+89
| | | | | | | | | | | | | | | | This patch adds support for the AMPIRE 800x480 LCD panel that is available for M53EVK. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
| * MX6 SabreSD: Use readl() to read the CCM_CCGR3 registerLiu Ying2013-12-17-1/+1
| | | | | | | | | | | | | | | | Align with the context to use readl() to read the CCM_CCGR3 register with memory barrier instead of __raw_readl(). Signed-off-by: Liu Ying <Ying.Liu@freescale.com> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
| * ARM: mx6: Update non-Freescale boards to include CPU errata.Eric Nelson2013-12-17-0/+4
| | | | | | | | | | | | | | | | | | The CPU errata expressed in include/configs/mx6_common.h apply to all i.MX6DQ and i.MX6DLS parts. Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefan Roese <sr@denx.de>
| * configs: imx: Remove CONFIG_SYS_SPD_BUS_NUM optionFabio Estevam2013-12-17-7/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the README: "- CONFIG_SYS_SPD_BUS_NUM If SPD EEPROM is on an I2C bus other than the first one, specify here. Note that the value must resolve to something your driver can deal with." There is no SPD EEPROM on the imx boards, so ged rid of this option. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
| * udoo: Add SATA support on uDoo Board.Giuseppe Pagano2013-12-17-0/+16
| | | | | | | | | | | | | | | | Add SATA support on uDoo Board. Signed-off-by: Giuseppe Pagano <giuseppe.pagano@seco.com> CC: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@freescale.com>
| * nitrogen6x: Move setup_sata to common partGiuseppe Pagano2013-12-17-26/+53
| | | | | | | | | | | | | | | | | | | | Move setup_sata function definition from platform file nitrogen6x.c to arch/arm/imx-common/sata.c to avoid code duplication. Signed-off-by: Giuseppe Pagano <giuseppe.pagano@seco.com> CC: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@freescale.com> CC: Eric Nelson <eric.nelson@boundarydevices.com>
| * i.MX6 (DQ/DLS): use macros for mux and pad declarationsEric Nelson2013-12-17-2109/+2121
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This allows the use of either or both declarations from the files mx6q_pins.h and mx6dl_pins.h. All board files should include <asm/arch/mx6-pins.h> with one of the following defined in boards.cfg MX6Q - for boards targeting i.MX6Q or i.MX6D MX6DL - for boards targeting i.MX6DL MX6S - for boards targeting i.MX6S MX6QDL - for boards that support any of the above with run-time detection Pad declarations will be MX6_PAD_x for single-variant boards and MX6Q_PAD_x and MX6DL_PAD_x for boards supporting both processor classes. Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Acked-by: Stefano Babic <sbabic@denx.de>
| * imx: Explicitly pass the I2C bus number in pmic_init()Fabio Estevam2013-12-17-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pmic_init() function has the I2C or SPI bus number that is connected to the PMIC. Instead of passing I2C_PMIC, explicitly pass the I2C bus number via I2C_x definition. The motivation for doing this is to avoid people just doing a copy and paste of I2C_PMIC into their board file when another I2C bus is actually used to interface to their PMIC. This also makes more obvious which is the I2C bus connected to the PMIC, without having to search in the source code for the meaning of the 'I2C_PMIC' number. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
| * udoo: Fix watchdog during kernel boot.Giuseppe Pagano2013-11-28-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | uDoo uses APX823-31W5 watchdog chip. Timeout is about 1.2 seconds. To disabled watchdog during kernel boot, WDI pin of that chip needs to be in "high impedance" state. I.mx6 gpio configuration does not contemplate tristate, so pin is set as input in high impedance. Signed-off-by: Giuseppe Pagano <giuseppe.pagano@seco.com> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com> CC: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@freescale.com>
| * udoo: Add ethernet support (FEC + Micrel KSZ9031).Giuseppe Pagano2013-11-28-0/+161
| | | | | | | | | | | | | | | | | | | | Add Ethernet and networking support on uDoo board (FEC +phy Micrel KSZ9031). Ethernet speed is currently limited to 10/100Mbps. Signed-off-by: Giuseppe Pagano <giuseppe.pagano@seco.com> Tested-by: Fabio Estevam <fabio.estevam@freescale.com> CC: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@freescale.com>
| * udoo: Move and optimize platform register setting.Giuseppe Pagano2013-11-28-1/+204
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previous uDoo configuration adopts register settings for DDR3, clock, muxing, etc. taken from Nitrogen6x. uDoo schematics is rather different from that board, and it needs customized setting for most of the registers. All this changes can be considered atomical since it is part of initial support of the board. Patch changes uDoo configuration files path to a specific one, and adopt optimized value for every configured register. Signed-off-by: Giuseppe Pagano <giuseppe.pagano@seco.com> Tested-by: Fabio Estevam <fabio.estevam@freescale.com> CC: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@freescale.com>
| * mx6sabresd: Add SPI NOR supportFabio Estevam2013-11-28-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | mx6sabre board has a m25p32 SPI NOR connected to ECSPI1 port. Add support for it. This patch allows the SPI NOR flash to be succesfully detected: => sf probe SF: Detected M25P32 with page size 256 Bytes, erase size 64 KiB, total 4 MiB Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * mx6sabresd: Fix wrong colors in LVDS splashFabio Estevam2013-11-28-8/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | Currently HDMI splash screen is selected by default on mx6sabresd boards. As LVDS is also enabled, this causes incorrect colors to be displayed im the LVDS panel. Fix this by selecting the LVDS panel as the default splash output and only keep HDMI or LVDS turned on at the same time. Acked-by: Liu Ying <Ying.Liu@freescale.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * power: power_fsl: Pass p->bus in the same way for SPI and I2C casesFabio Estevam2013-11-27-2/+1
| | | | | | | | | | | | | | | | | | There is no need to pass p->bus differently when the PMIC is connected via SPI or via I2C. Handle the both cases in the same way. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * efikamx: Fix pmic_init() argumentFabio Estevam2013-11-27-1/+1
| | | | | | | | | | | | | | | | | | On efikamx board the PMIC is connected via SPI interface, so it does not make sense to pass I2C_PMIC into the pmic_init() interface. Pass the SPI bus number via CONFIG_FSL_PMIC_BUS option instead. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * mx31pdk: Fix pmic_init() argumentFabio Estevam2013-11-27-1/+1
| | | | | | | | | | | | | | | | | | On mx31pdk board the PMIC is connected via SPI interface, so it does not make sense to pass I2C_PMIC into the pmic_init() interface. Pass the SPI bus number via CONFIG_FSL_PMIC_BUS option instead. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * mx51evk: Fix pmic_init() argumentFabio Estevam2013-11-27-1/+1
| | | | | | | | | | | | | | | | | | | | On mx51evk board the PMIC is connected via SPI interface, so it does not make sense to pass I2C_PMIC into the pmic_init() interface. Pass the SPI bus number via CONFIG_FSL_PMIC_BUS option instead. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
| * imx-common: remove extraneous semicolon from macroEric Nelson2013-11-27-2/+2
| | | | | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
| * nitrogen6x: Remove unused OCOTP optionsFabio Estevam2013-11-27-10/+0
| | | | | | | | | | | | | | | | | | OCOTP driver is currently selected via CONFIG_MXC_OCOTP option. Remove the old OCOTP related options, as they are not used anymore. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Eric Nelson <eric.nelson@boundarydevices.com>
| * Net: FEC: Fix huge memory leakMarek Vasut2013-11-21-78/+99
| | | | | | | | | | | | | | | | | | | | | | The fec_halt() never free'd both RX and TX DMA descriptors that were allocated in fec_init(), nor did it free the RX buffers. Rework the FEC driver so that these descriptors and buffers are allocated only once in fec_probe(). Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
| * i.MX6DQ/DLS: whitespace: Align IOMUX_PAD column in declarationsEric Nelson2013-11-13-490/+490
| | | | | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
| * i.MX6DQ/DLS: remove unused pad declarationsEric Nelson2013-11-13-1043/+0
| | | | | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
| * i.MX6DQ: Add Pinmux settings that are present in mainline and Dual-Lite/SoloEric Nelson2013-11-13-0/+24
| | | | | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
| * i.MX6DQ/DLS: remove useless mux/pad declarationsEric Nelson2013-11-13-160/+0
| | | | | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
| * i.MX6DQ/DLS: replace pad names with their Linux kernel equivalentsEric Nelson2013-11-13-2064/+2064
| | | | | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
| * mx6: titanium: Move BSP code to barco board directoryStefan Roese2013-11-13-1/+1
| | | | | | | | | | | | | | | | | | | | | | Since the titanium board is not a Freescale board, move its BSP code from the freescale board directory to the newly created barco board directory. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Peter Korsgaard <peter.korsgaard@barco.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Peter Korsgaard <peter.korsgaard@barco.com>
| * titanium: Return the error when cpu_eth_init() failsFabio Estevam2013-11-13-1/+1
| | | | | | | | | | | | | | When cpu_eth_init() fails we should not return success. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefan Roese <sr@denx.de>
| * wandboard: Return the error when cpu_eth_init() failsFabio Estevam2013-11-13-1/+1
| | | | | | | | | | | | When cpu_eth_init() fails we should not return success. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * wandboard: Return the error immediately when ipuv3_fb_init() failsFabio Estevam2013-11-13-1/+3
| | | | | | | | | | | | If ipuv3_fb_init() fails, we should return the error immediately. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * mxs_gpio: fix the handling in gpio_direction_output()Michael Heimpold2013-11-13-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Setting the direction and an output value should be done by 1) set the desired output value, 2) switch to output. If this is done in the inverse order, there can be a glitch on the GPIO line. This patch fixes this by using the order as described above. Signed-off-by: Michael Heimpold <mhei@heimpold.de> Acked-by: Stefano Babic <sbabic@denx.de>
| * configs: imx: Make CONFIG_SYS_PROMPT uniform across FSL boardsFabio Estevam2013-11-13-10/+0
| | | | | | | | | | | | | | | | There is no real benefit in adding the board name into U-boot's prompt, so remove the custom CONFIG_SYS_PROMPT definitions so that the standard "=> " prompt is used across FSL boards. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | ARM: AM43xx: Add MaintainerLokesh Vutla2013-12-18-1/+1
| | | | | | | | | | | | Adding Maintainer for AM43xx. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | ARM: AM43xx: GP_EVM: Add support for DDR3Lokesh Vutla2013-12-18-19/+136
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GP EVM has 1GB DDR3 attached(Part no: MT41K512M8RH). Adding details for the same. Below is the brief description of DDR3 init sequence(SW leveling): -> Enable VTT regulator -> Configure VTP -> Configure DDR IO settings -> Disable initialization and refreshes until EMIF registers are programmed. -> Program Timing registers -> Program leveling registers -> Program PHY control and Temp alert and ZQ config registers. -> Enable initialization and refreshes and configure SDRAM CONFIG register Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | ARM: AM43xx: EPOS_EVM: Add support for LPDDR2Lokesh Vutla2013-12-18-3/+256
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AM4372 EPOS EVM has 1GB LPDDR2(Part no: MT42L256M32D2LG-25 WT:A) Adding LPDDR2 init sequence and register details for the same. Below is the brief description of LPDDR2 init sequence: -> Configure VTP -> Configure DDR IO settings -> Disable initialization and refreshes until EMIF registers are programmed. -> Program Timing registers -> Program PHY control and Temp alert and ZQ config registers. -> Enable initialization and refreshes and configure SDRAM CONFIG register -> Wait till initialization is complete and the configure MR registers. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | ARM: AM33xx+: Update ioregs to pass different valuesLokesh Vutla2013-12-18-26/+134
| | | | | | | | | | | | | | | | | | | | | | Currently same value is programmed for all ioregs. This is not the case for all SoC's like AM4372. So adding a structure for ioregs and updating in all board files. And also return from config_cmd_ctrl() and config_ddr_data() functions if data is not passed. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> [trini: Fixup dxr2, cm_t335, adapt pcm051 rev3] Signed-off-by: Tom Rini <trini@ti.com>
* | ARM: AM43xx: clocks: Update DPLL detailsLokesh Vutla2013-12-18-17/+187
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Updating the Multiplier and Dividers value for all DPLLs. Safest OPP is read from DEV ATTRIBUTE register. Accoring to the value returned the MPU DPLL is locked. At different OPPs follwoing are the MPU locked frequencies. OPP50 300MHz OPP100 600MHz OPP120 720MHz OPPTB 800MHz OPPNT 1000MHz According to the latest DM following is the OPP table dependencies: VDD_CORE VDD_MPU OPP50 OPP50 OPP50 OPP100 OPP100 OPP50 OPP100 OPP100 OPP100 OPP120 So at different OPPs of MPU it is safest to lock CORE at OPP_NOM. Following are the DPLL locking frequencies at OPP NOM: Core locks at 1000MHz Per locks at 960MHz LPDDR2 locks at 266MHz DDR3 locks at 400MHz Touching AM33xx files also to get DPLL values specific to board but no functionality difference. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | ARM: AM43xx: mux: Update mux dataLokesh Vutla2013-12-18-2/+65
| | | | | | | | | | | | | | Updating the mux data for UART, adding data for i2c0 and mmc. And also updating pad_signals structure. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | ARM: AM43xx: Update Current Booting devices listLokesh Vutla2013-12-18-3/+10
| | | | | | | | | | | | | | Current Booting devices list is different from that of AM33xx. Updating the same. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | ARM: AM43xx: Select clk source for Timer2Lokesh Vutla2013-12-18-0/+4
| | | | | | | | | | | | Selecting the Master osc clk as Timer2 clock source. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
generated by cgit v1.1 at 2024-10-13 17:11:59 +0000