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* picosam9g45: adopt CONFIG_SYS_PROMPTAndreas Bießmann2015-08-28-1/+1
| | | | | | | | Commit 181bd9dc61d2da88b78f1c1138a685dae39354d6 introduced Kconfig selection for SYS_PROMPT. When applying the new picosam9g45 board this change slipped through, adopt it. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* at91sam9260ek: add missing files to MAINTAINERSAndreas Bießmann2015-08-28-0/+1
| | | | | | | | | | | This fixes the following genboardscfg.py warnings: ---8<--- WARNING: no status for 'at91sam9g20ek_2mmc' WARNING: no maintainers for 'at91sam9g20ek_2mmc' --->8--- Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* at91sam9rlek: add missing files to MAINTAINERSAndreas Bießmann2015-08-28-0/+1
| | | | | | | | | | | This fixes following genboardscfg.py warning: ---8<--- WARNING: no status for 'at91sam9rlek_mmc' WARNING: no maintainers for 'at91sam9rlek_mmc' --->8--- Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* omap-common: SYS_BOOT fallback logic correction and support for more devicesPaul Kocialkowski2015-08-28-10/+22
| | | | | | | | | | | | | | | | | | | | | The SYS_BOOT-based fallback shouldn't only check for one of the conditions of use and then let the switch/case handle each boot device without enforcing the conditions for each type of boot device again. For instance, this behaviour would trigger the fallback for UART when BOOT_DEVICE_UART is defined, CONFIG_SPL_YMODEM_SUPPORT is enabled (which should be a show-stopper) and e.g. BOOT_DEVICE_USB is enabled and not CONFIG_SPL_USB_SUPPORT. Separating the logic for USB and UART solves this. In addition, this adds support for more peripheral devices (USBETH and CPGMAC) to the fallback mechanism. Note that the USBETH boot device should always be different from the USB boot device (each should match a different bootrom handoff case). Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Acked-by: Hannes Schmelzer <oe5hpm@oevsv.at> Tested-by: Hannes Schmelzer <oe5hpm@oevsv.at>
* mtd/nand/ubi: assortment of alignment fixesMarcel Ziswiler2015-08-28-7/+19
| | | | | | | | | | | | | | Various U-Boot adoptions/extensions to MTD/NAND/UBI did not take buffer alignment into account which led to failures of the following form: ERROR: v7_dcache_inval_range - start address is not aligned - 0x1f7f0108 ERROR: v7_dcache_inval_range - stop address is not aligned - 0x1f7f1108 Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Scott Wood <scottwood@freescale.com> [trini: Add __UBOOT__ hunk to lib/zlib/zutil.c due to malloc.h in common.h] Signed-off-by: Tom Rini <trini@konsulko.com>
* arm: spear: Some changes / updates to the x600 config headerStefan Roese2015-08-28-5/+16
| | | | | | | | | | | | | | | This patch brings the following changes to the x600 board support: - Add USB EHCI support - Add VFAT support for USB key file access - Increase malloc size (for UBI / UBIFS usage) - Enable Thumb mode to save some image space - Remove unreferenced CONFIG_STACKSIZE - Remove unreferenced CONFIG_SPL_NO_PRINTF Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Cc: Vipin Kumar <vk.vipin@gmail.com>
* arm: spear: Enable caches on SPEArStefan Roese2015-08-28-0/+10
| | | | | | | | | | | The designware ethernet driver supports d-cache now. So there is nothing stopping us now to enable the caches completely on SPEAr. Tested on SPEAr600 x600 board. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Cc: Vipin Kumar <vk.vipin@gmail.com>
* arm: spear: Move to common SPL infrastructureStefan Roese2015-08-28-271/+85
| | | | | | | | | | | | | The SPL implementation for SPEAr600 is older than the common SPL infrastructure. This patch now moves the SPEAr600 SPL over to the common SPL code. Tested on the only SPEAr board that currently uses SPL in mainline U-Boot, the x600. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Cc: Vipin Kumar <vk.vipin@gmail.com>
* arm: spear: Fix booting - relocate vector table to 0 (low-vector)Stefan Roese2015-08-28-5/+0
| | | | | | | | | | | | Booting SPEAr600 eval board doesn't work with current mainline U-Boot. With this patch the low-vector bit is left to '0'. Resulting in the common relocation of the vectors to 0 (SDRAM) to work correctly. Tested on the SPEAr600 EVB. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Cc: Vipin Kumar <vk.vipin@gmail.com>
* ARM: k2l: Fix device speedsLokesh Vutla2015-08-28-3/+3
| | | | | | | | | | | ARM supported speeds and init value of core_pll for SDP1200 are programmed wrong as part for the device speed cleanups. Fixing it here. Thanks to "Vitaly Andrianov <vitalya@ti.com>" for bisecting this issue Fixes: c37ed9f11b61 ("ARM: keystone2: Fix dev and arm speed detection") Tested-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: keystone2: Update READMELokesh Vutla2015-08-28-11/+15
| | | | | | | Update README to include uart boot mode support and makefile changes. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: keystone2: Build MLO by defaultLokesh Vutla2015-08-28-0/+4
| | | | | | | | | | | MLO(NAND/MMC boot image), is used for all the ks2 platforms. Enabling it in config.mk so that these images will be automatically built upon calling make. u-boot-spi.gph is already the build target, so not including here. Reported-by: Nishanth Menon <nm@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: keystone2: Rename u-boot-nand.gph to MLOLokesh Vutla2015-08-28-7/+9
| | | | | | | | | | | | | | NAND boot mode, ROM expects an image with a gp header in the beginning and an 8bytes filled with zeros at the end. The same is true for SD boot on K2G platforms but the file name should be MLO. Renaming u-boot-nand.gph to MLO, so that same image can be used for NAND and SD boots. And also not including all the u-boot only images under CONFIG_SPL_BUILD. Reported-by: Nishanth Menon <nm@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: keystone2: move the custom build rules out to keystone specific makefileNishanth Menon2015-08-28-16/+22
| | | | | | | | | | | | | | | Keystone has build rules introduced by commit ef509b9063fb7 ("k2hk: add support for k2hk SOC and EVM") and commit 0e7f2dbac6ead ("keystone: add support for NAND gpheader image"). These are not reused by other platforms for the build, hence there is no clear benefit is maintaining them in the generic makefile as a build target. move these to the keystone specific make option Original idea of using config.mk by Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: keystone2: configs: Move SP to end of u-boot sectionLokesh Vutla2015-08-28-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Currently u-boot stack is defined at the beginning of MSMC RAM. This is a problem for uart boot mode as ROM downloads directly to starting of MSMC RAM. Fixing it by moving stack to the end of u-boot section and shifting SYS_TEXT_BASE to the start of MSMC RAM. Updated division of MSMC RAM is shown below: ----------------------------------------- | | | | | U-Boot text |U-Boot | SPL text | | download | Stack | Download + | | | | SPL_BSS + | | | | SPL_STACK | ----------------------------------------- [1] [2] [3] [4] [1] SYS_TEXT_BASE (Start of MSMC RAM) [2] SPL_TEXT_BASE - GBL_DATA_SIZE [3] SPL_TEXT_BASE [4] END of SPL [1] + [2] is at least 1M on all platforms, so no chance of overlap. Reviewed-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* env_mmc: Properly prefix mmc errors with '!'Hans de Goede2015-08-28-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | The set_default_env() function from env_common.c expects either a fully formatted error msg, e.g.: "## Resetting to default environment\n" or an error msg prefixed with an !, in which case it will format it. Fix the init_mmc_for_env() error messages to be prefixed with a ! this changes the bootup-log on sunxi when no mmc card is found from: MMC: SUNXI SD/MMC: 0 No MMC card foundIn: serial Out: serial To: MMC: SUNXI SD/MMC: 0 *** Warning - No MMC card found, using default environment In: serial Out: serial Which clearly is how things should look. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* malloc_simple: Correct the alignment logic in memalign_simple()Simon Glass2015-08-28-1/+1
| | | | | | | | This should use the align parameter, not bytes. Natural alignment is one use case but should not be the only one supported by this function. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* kconfiglib: update to the latest versionUlf Magnusson2015-08-28-2252/+1906
| | | | | | | | | | | | | | | Corresponds to ba71a0e (Fix _parse_block() 'parent' documentation re. ifs.) from upstream, just adding the SPDX tag. Has performance improvements, code cleanup, Python 3 support, and various small fixes, including the following: - Unset user values when loading a zero-byte .config. (5e54e2c) - Ignore indented .config assignments. (f8a7510) - Do not require $srctree to be set for non-kernel projects. (d56e9c1) - Report correct locations in the presence of continuation lines. (0cebc87) Signed-off-by: Ulf Magnusson <ulfalizer@gmail.com>
* ARM: DRA74-evm: Use SMA_1 spare register to workaround DP83865 phy on SR2.0Nishanth Menon2015-08-28-0/+19
| | | | | | | | | | | | | | | | | | | DP83865 ethernet phy used on DRA74x-evm is quirky and the datasheet provided IODELAY values for standard RGMII phys do not work. Silicon Revision(SR) 2.0 provides an alternative bit configuration that allows us to do a "gross adjustment" to launch the data off a different internal clock edge. Manual IO Delay overrides are still necessary to fine tune the clock-to-data delays. This is a necessary workaround for the quirky ethernet Phy we have on the platform. NOTE: SMA registers are spare "kitchen sink" registers that does contain bits for other workaround as necessary as well. Hence the control for the same is introduced in a generic SoC specific, board generic location. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: DRA74-evm: Add iodelay values for SR2.0Nishanth Menon2015-08-28-11/+83
| | | | | | | | | | | | | | | Silicon revision 2.0 has new signal routing hence has an updated set of iodelay parameters to be used. Update the configuration for the same. Padmux remains the same. Based on data from VayuES2_EVM_Base_Config-20150807. NOTE: With respect to the RGMII values, the Manual IODelay values are used for the fine adjusments needed to meet the tight RGMII specification. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: DRA7: Add detection of ES2.0Nishanth Menon2015-08-28-0/+11
| | | | | | | | | | | | | | | | | Add support for detection of ES2.0 version of DRA7 family of processors. ES2.0 is an incremental revision with various fixes including the following: - reset logic fixes - few assymetric aging logic fixes - MMC clock rate fixes - Ethernet speed fixes - edma fixes for mcasp [ravibabu@ti.com: posted internal for an older bootloader] Signed-off-by: Ravi Babu <ravibabu@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* Makefile: Use correct timezone for U_BOOT_TZChris Packham2015-08-28-4/+10
| | | | | | | | | | | When building with SOURCE_DATE_EPOCH the timezone is in UTC. When building normally the timezone is taken from the build machine's locale setting. Signed-off-by: Chris Packham <judge.packham@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Paul Kocialkowski <contact@paulk.fr> Tested-by: Andreas Bießmann <andreas.devel@googlemail.com>
* lib/display_options: Fix print_freqSuriyan Ramasami2015-08-28-9/+1
| | | | | | | | | | | | | | | | | Build without CONFIG_SPL_SERIAL_SUPPORT does not print the cpu freq. I have seen this in the odroid U3 board, where on boot one sees this: CPU: Exynos4412 @ GHz instead of: CPU: Exynos4412 @ 1 GHz I am assuming that this change was done to get rid of compiler warnings related to unused variables when building with CONFIG_SPL_SERIAL_SUPPORT not being defined in an SPL build. Signed-off-by: Suriyan Ramasami <suriyan.r@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
* NDS32: Generic Board Support and UnsupportKun-Hua Huang2015-08-28-1731/+0
| | | | | | Remove ag101 and ag102 support Signed-off-by: Kun-Hua Huang <kunhua@andestech.com>
* NDS32: Generic Board Support and UnsupportKun-Hua Huang2015-08-28-427/+104
| | | | | | Add nds32 ag101p generic board support. Signed-off-by: Kun-Hua Huang <kunhua@andestech.com>
* rpi: set fdt_addr_r to 0x00000100 to match default device_tree_addressJonathan Liu2015-08-28-2/+2
| | | | | | | Raspberry Pi by default loads the FDT to 0x00000100 so set fdt_addr_r to match and move scriptaddr to 0x02000000 to avoid clobbering the FDT. Signed-off-by: Jonathan Liu <net147@gmail.com>
* image: Fix loop condition to avoid warningThierry Reding2015-08-28-2/+2
| | | | | | | | | | | | | | GCC 5.1 starts warning for comparisons such as !a > 0, assuming that the negation was meant to apply to the whole expression rather than just the left operand. Indeed the comparison in the FIT loadable code is confusingly written, though it does end up doing the right thing. Rewrite the condition to be more explicit, that is, iterate over strings until they're exhausted. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* Merge git://git.denx.de/u-boot-x86Tom Rini2015-08-26-635/+5954
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| * dm: pci: Document binding of pci device driversBin Meng2015-08-26-3/+68
| | | | | | | | | | | | | | Document how pci devices are bound to device drivers. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: crownbay: Support Topcliff integrated pci uart devices with driver modelBin Meng2015-08-26-5/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to make a pci uart device node to be properly bound to its driver, we need make sure its parent node has a compatible string which matches a driver that scans all of its child device nodes in the device tree. Change all pci bridge nodes under root pci node to use "pci-bridge" compatible driver, as well as corresponding <reg> properties to indicate its devfn. At last, adding "u-boot,dm-pre-reloc" to each of these nodes for driver model to initialize them before relocation. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * dm: core: Fix code reentrancy issue in device_probe_child()Bin Meng2015-08-26-5/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The device might have already been probed during the call to device_probe() on its parent device (e.g. PCI bridge devices). In its parent device's probe routine, it might probe all of its child devices via device_probe() thus the codes reenter device_probe_child(). To support code reentrancy, test these allocated memory against NULL to avoid memory leak, and return to the caller if dev->flags has DM_FLAG_ACTIVATED set after device_probe() returns, so that we don't mess up the device. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * dm: pci: Optimize pci_uclass_post_bind()Bin Meng2015-08-26-0/+7
| | | | | | | | | | | | | | | | If there is no pci device listed in the device tree, don't bother scanning the device tree. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * video: ct69000: Remove unused codesBin Meng2015-08-26-21/+0
| | | | | | | | | | | | | | | | Remove unused CONFIG_USE_CPCIDVI wrapped codes. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de>
| * x86: crownbay: Enable on-board SMSC superio keyboard controllerBin Meng2015-08-26-7/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | So far we only enabled one legacy serial port on the SMSC LPC47m superio chipset on Intel Crown Bay board. As the board also has dual PS/2 ports routed out, enable the keyboard controller which is i8042 compatible so that we can use PS/2 keyboard and mouse. In order to make PS/2 keyboard work with the VGA console, remove CONFIG_VGA_AS_SINGLE_DEVICE. To boot Linux kernel with PIC mode using PIRQ routing table, adjust the mask in the device tree to reserve irq12 which is used by PS/2 mouse. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * video: cfb_console: Allow VGA device to work without i8042 keyboardBin Meng2015-08-26-6/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | So far if CONFIG_VGA_AS_SINGLE_DEVICE is not defined, the VGA device will try to initialize a keyboard device (for x86, it is i8042). But if i8042 controller initialization fails (eg: there is no keyboard connected to the PS/2 port), drv_video_init() just simply returns. This kills the opportunity of using a usb keyboard later with the vga console, as the vga initialization part is actually ok, only keyboard part fails. Change the code logic to allow this. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de>
| * x86: i8042: Correctly initialize the controllerBin Meng2015-08-26-22/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The existing i8042 keyboard controller driver has some issues. First of all, it does not issue a self-test command (0xaa) to the controller at the very beginning. Without this, the controller does not respond to any command at all. Secondly, it initializes the configuration byte register to turn on the keyboard's interrupt, as U-Boot does not normally allow interrupts to be processed. Finally, at the end of the initialization routine, it wrongly sets the controller to disable all interfaces including both keyboard and mouse. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: i8042: Clean up the driver per coding conventionBin Meng2015-08-26-156/+177
| | | | | | | | | | | | | | | | | | - Rename CamelCase variables to conform U-Boot coding convention - Rename wait_until_kbd_output_full() to kbd_output_full() - Change to use macros for i8042 command and control register bits Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: i8042: Reorder static functionsBin Meng2015-08-26-268/+222
| | | | | | | | | | | | | | | | Reorder those static function so that their declarations can be removed. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: i8042: Remove unused codesBin Meng2015-08-26-17/+0
| | | | | | | | | | | | | | Remove unused CONFIG_USE_CPCIDVI wrapped codes. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: gpio: Tidy up gpio_ich6_get_base() and callersSimon Glass2015-08-26-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | This function can return an error. Correct the detection of this error so that it works even with large 32-bit addresses. The return value is set up for returning an I/O address but the function is also used to return a memory-mapped address. Adjust the return code to make this work. Also add a bit more debugging. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: gpio: Correct calls to _ich6_gpio_set_direction()Simon Glass2015-08-26-2/+2
| | | | | | | | | | | | | | These calls seem to be incorrect. The function expects an I/O address but the existing callers pass the value at an I/O address. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: minnowmax: Correct pad-offset value for host_en1Simon Glass2015-08-26-1/+1
| | | | | | | | | | | | | | This should be 0x250, not 0x258. Fix it. Reported-by: Andrew Bradford <andrew.bradford@kodakalaris.com> Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: pci: Add a comment to help find pci_hose_read_config_byte, etc.Simon Glass2015-08-26-0/+1
| | | | | | | | | | | | | | | | These functions are defined by macros so do not show up with grep. Add a comment to help. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: minnowmax: Add access to GPIOs E0, E1, E2Simon Glass2015-08-26-0/+27
| | | | | | | | | | | | | | These GPIOs are accessible on the pin header. Add pinctrl settings for them so that we they can be adjusted using the 'gpio' command. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: Add DSDT table for supporting ACPI on QEMUSaket Sinha2015-08-26-1/+712
| | | | | | | | | | | | | | | | The DSDT table contains a bytecode that is executed by a driver in the kernel. Signed-off-by: Saket Sinha <saket.sinha89@gmail.com> Tested with QEMU '-M q35' Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Add ACPI table support to QEMUSaket Sinha2015-08-26-0/+177
| | | | | | | | | | | | | | | | | | This patch mainly adds ACPI support to QEMU. Verified by booting Linux kernel on QEMU Q35. Signed-off-by: Saket Sinha <saket.sinha89@gmail.com> Minor whitespace fixes and dropped mention of i440FX in commit message: Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: Generate a valid ACPI tableSaket Sinha2015-08-26-0/+855
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement write_acpi_table() to create a minimal working ACPI table. This includes writing FACS, XSDT, RSDP, FADT, MCFG, MADT, DSDT & SSDT ACPI table entries. Use a Kconfig option GENERATE_ACPI_TABLE to tell U-Boot whether we need actually write the APCI table just like we did for PIRQ routing, MP table and SFI tables. With ACPI table existence, linux kernel gets control of power management, thermal management, configuration management and monitoring in hardware. Signed-off-by: Saket Sinha <saket.sinha89@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tidied up whitespace and aligned some tabs: Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: pci: Save devfn without bus number in pci_uclass_child_post_bind()Bin Meng2015-08-26-2/+2
| | | | | | | | | | | | | | | | In pci_uclass_child_post_bind(), bdf is extracted from fdt_pci_addr. Mask bus number before save it to pplat->devfn. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * fdtdec: Fix possible infinite loop in fdtdec_get_pci_vendev()Bin Meng2015-08-26-2/+1
| | | | | | | | | | | | | | | | When there is no valid compatible string in current list, we should advance to next one in the compatible string list. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * patman: use -D option for git format-patchMasahiro Yamada2015-08-26-1/+1
| | | | | | | | | | | | | | | | This allows Patman to generate smaller patches for file removal. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de>
generated by cgit v1.1 at 2024-12-29 18:00:45 +0000