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* mx35: Fix typo on EDIOBenoît Thébaudeau2012-09-01-4/+4
| | | | | | Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
* mx5: Enable dcacheBenoît Thébaudeau2012-09-01-0/+8
| | | | | | | | | Now that the main i.MX features work fine with dcache enabled, enabled it by default if CONFIG_SYS_DCACHE_OFF is not defined. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
* mx25: Enable dcacheBenoît Thébaudeau2012-09-01-0/+8
| | | | | | | | | Now that the main i.MX features work fine with dcache enabled, enabled it by default if CONFIG_SYS_DCACHE_OFF is not defined. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
* mxc_spi: Round up clock dividerBenoît Thébaudeau2012-09-01-2/+2
| | | | | | | | | | | Since the input frequency of the API is a maximum that should not be exceeded in order for the devices to operate properly, the SPI clock divider should be rounded up, not truncated. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
* rtc: add support of mx27 rtctrem2012-09-01-0/+127
| | | | | | | This driver has been tested on board armadeus apf27. Signed-off-by: Philippe Reynes <tremyfr@yahoo.fr> Acked-by: Stefano Babic <sbabic@denx.de>
* MX28: Shuffle around the power management codeMarek Vasut2012-09-01-6/+3
| | | | | | | | | | Move some function calls to a more appropriate place, so they're called only when needed. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
* MX28: Drop the cp15 reconfiguration from SPLMarek Vasut2012-09-01-42/+0
| | | | | | | | | | | | | | | The SPL doesn't need the CP15 reconfiguration, as that's what the BootROM does for us already. Moreover, when the CP15 is reconfigured and the code returns control to BootROM, the USB boot works no more. Remove the code and allow [1] to work properly as well. [1] http://git.bfuser.eu/?p=marex/mxsldr.git;a=summary Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
* tx25: Use generic gpio_* callsVikram Narayanan2012-09-01-16/+9
| | | | | | | | | | | | Instead of manipulating gpio registers directly, use the calls from the gpio library. Signed-off-by: Vikram Narayanan <vikram186@gmail.com> Acked-by: Stefano Babic <sbabic@denx.de> Cc: John Rigby <jcrigby@gmail.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
* mxs: Convert sys_proto.h prefixes to 'mxs'Otavio Salvador2012-09-01-44/+44
| | | | | | | The sys_proto.h functions (except the boot modes) are compatible with i.MX233 and i.MX28 so we use 'mxs' prefix for its methods. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* mxs: rename regs-clkctrl.h to regs-clkctrl-mx28.hOtavio Salvador2012-09-01-2/+2
| | | | | | | The CLKCTRL registers are SoC specific so we ought to have it clear on filename. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* mxs: Remove not required include of iomux-mx28.hOtavio Salvador2012-09-01-1/+0
| | | | | | | The iomux-mx28.h include is not required on spl_mem_init.c so it has been droped. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* mxs: Remove not required explicit iomux-mx28.h includeOtavio Salvador2012-09-01-1/+0
| | | | | | | | The iomux header is included on sys_proto.h so to avoid SoC specific header inclusion. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Acked-by: Marek Vasut <marex@denx.de>
* apx4devkit: Turn on cachesFabio Estevam2012-09-01-2/+0
| | | | | | | | | Turn on data and instruction caches. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> include/configs/apx4devkit.h | 2 -- 1 files changed, 0 insertions(+), 2 deletions(-) Acked-by: Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com>
* m28evk: Turn on cachesFabio Estevam2012-09-01-2/+0
| | | | | | Turn on data and instruction caches. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* arm:cache:trats: Enable PL310 L2 Cache Controller at TRATS Samsung boardŁukasz Majewski2012-09-01-2/+4
| | | | | | | | Enable the PL310 L2 cache controller at TRATS Samsung board. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* arm:exynos: Enable data cache at exynos based processors.Łukasz Majewski2012-09-01-0/+8
| | | | | | | | | This patch enables the L1 data cache for systems based on Samsung Exynos processor. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* video: support exynos pwm backlight driverDonghwa Lee2012-09-01-0/+92
| | | | | | | | | This patch support exynos pwm backlight driver. It can control backlight power and brightness by using pwm. Signed-off-by: Donghwa Lee <dh09.lee@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* video: exynos fb driver supports display port featureDonghwa Lee2012-09-01-1/+21
| | | | | | | | | | | | If dp_enabled was set, exynos fb driver support display port feature. This patch depends on [PATCH] video: support exynos fimd driver for various exynos series. http://marc.info/?l=u-boot&m=134119605104467&w=2 Signed-off-by: Donghwa Lee <dh09.lee@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* video: add dp_enabled variable in vidinfo structureDonghwa Lee2012-09-01-0/+1
| | | | | | | | | To support display port in exynos fb driver, added dp_enabled variable in vidinfo structure that set in board file. Signed-off-by: Donghwa Lee <dh09.lee@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* video: support exynos display port driversDonghwa Lee2012-09-01-0/+3262
| | | | | | | | | | | | | This patch set supports exynos display port drivers. DisplayPort is an industry standard device to accommodate the increasing board adoption of digital display technology within the PC and consumer electronics. The interface supports internal chip-to-chip and external box-to-box digital display connections. Signed-off-by: Donghwa Lee <dh09.lee@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* EXYNOS5: add display port base addressDonghwa Lee2012-09-01-0/+3
| | | | | | | | | This patch add display port base address for EXYNOS5. In case of EXYNOS4, use DEVICE_NOT_AVAILABLE macro because DP is not supported. Signed-off-by: Donghwa Lee <dh09.lee@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* EXYNOS5: support display port phy control functionDonghwa Lee2012-09-01-0/+26
| | | | | | | | This patch support display port phy control function. Signed-off-by: Donghwa Lee <dh09.lee@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* EXYNOS5: support display system register controlDonghwa Lee2012-09-01-0/+18
| | | | | | | | This patch supports display block system regisger control. Signed-off-by: Donghwa Lee <dh09.lee@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* EXYNOS5: support exynos5 lcd clock controlDonghwa Lee2012-09-01-1/+107
| | | | | | | | This patch support exynos5 lcd clock control. Signed-off-by: Donghwa Lee <dh09.lee@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* video: support exynos fimd driver for various exynos seriesDonghwa Lee2012-09-01-34/+67
| | | | | | | | | This patch supports exynos fimd driver for various exynos series different from existing it supports only exynos4 chip. Signed-off-by: Donghwa Lee <dh09.lee@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* ARM: EXYNOS: fixed compiler warning messageJaehoon Chung2012-09-01-1/+4
| | | | | | | | | | | Removed [-Wuninitialized] warning message. The fout_sel is assigned to "-1" by default. And start, gpio_func is initialized to 0. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* arm/s5pxx: Fix get_timer_masked to get the time.Zhong Hongbo2012-09-01-5/+17
| | | | | | | | | | | In general, The get_timer_masked function get the system time, no the number of ticks. Such as the nand_wait_ready will use get_timer_masked to delay the operations. And change the system time to adopt to the CONFIG_SYS_HZ. Signed-off-by: Hongbo Zhong <bocui107@gmail.com> Tested-by: Jaehoon Chung<jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* arm:trats: loaduimage environment variable defied for TRATS targetŁukasz Majewski2012-09-01-0/+1
| | | | | | Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* SMDK5250: Enable UART and MMC for Exynos5250 Rev 1.0Rajeshwari Shinde2012-09-01-4/+4
| | | | | | | This patch sets UART3 and MMC channle 0 for Exynos5250 Rev 1.0 Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* EXYNOS5 : Modify pinnumx settings as per Exynos5250 Rev 1.0Rajeshwari Shinde2012-09-01-11/+18
| | | | | | | | | | This patch modifies the pinmux settings of MMC and UART as per Exynos5250 Rev 1.0. It also corrects the gpio offset calculations. Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* EXYNOS5: CLOCK: Add BPLL supportRajeshwari Shinde2012-09-01-7/+24
| | | | | | | | This patch adds support for BPLL clock. Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* EXYNOS5: CLOCK: Modify MPLL clock out for Exynos5250 Rev 1.0Rajeshwari Shinde2012-09-01-1/+14
| | | | | | | | | | | MPLL clock-out of Exynos5250 Rev 1.0 is always at 1.6GHz. Adjust the divisor value to get 800MHz as needed by devices like UART etc Signed-off-by: Hatim Ali <hatim.rv@samsung.com> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* Exynos5: DDR3: Add DDR3 memory setup for Exynos5250 Rev 1.0Rajeshwari Shinde2012-09-01-464/+551
| | | | | | | | The patch adds the memory initialization sequence of DDR3. Signed-off-by: Hatim Ali <hatim.rv@samsung.com> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* EXYNOS5: CLOCK: Add clock support for Exynos5250 Rev 1.0Rajeshwari Shinde2012-09-01-440/+1139
| | | | | | | | Add new clock values for Exynos5250 Rev 1.0 Signed-off-by: Hatim Ali <hatim.rv@samsung.com> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* EXYNOS5: CLOCK: define additional clock registers for Exynos5250 Rev 1.0Rajeshwari Shinde2012-09-01-108/+126
| | | | | | | | | Define additional registers for clock control in Exynos5250 Rev 1.0 Signed-off-by: Hatim Ali <hatim.rv@samsung.com> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* SMDK5250: Add smdk5250-uboot-spl.ldsRajeshwari Shinde2012-09-01-0/+71
| | | | | | | | | | | | | Default spl/u-boot-spl.lds created by spl/Makefile resolves the spl text load addr to 0x0. As 0x0 belongs to iROM addr so Global variables can not be used. Adding specific smdk5250-uboot-spl.lds makes possible to use Global Variables in spl. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* SMDK5250: SPL: Define parametric board initializerRajeshwari Shinde2012-09-01-0/+69
| | | | | | | | | | | | Define table-driven configuration mechanism for SMDK5250 rather than hard-coding board initialization parameters. Signed-off-by: Che-Liang Chiou <clchiou@chromium.org> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Signed-off-by: Tom Wai-Hong Tam <waihong@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* ARCH: SPL: Add parametric board initializerRajeshwari Shinde2012-09-01-0/+97
| | | | | | | | | | | | | Add a structure for table-driven configuration mechanism such that no recompilation is needed to update the configuration parameters, rather than hard-coding board initialization parameters. Signed-off-by: Che-Liang Chiou <clchiou@chromium.org> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Signed-off-by: Tom Wai-Hong Tam <waihong@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* ARM: Remove unused stack and irq config definesRob Herring2012-09-01-888/+2
| | | | | | | | | | | CONFIG_STACKSIZE is not referenced anywhere except on AVR32, but present in most ARM board config files. IRQs are only enabled for 1 config, so remove the unused config options for IRQ and FIQ stack size as well. Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Rob Herring <rob.herring@calxeda.com>
* arm: bugfix: save_boot_params_default accesses uninitalized stack when -O0Tetsuyuki Kobayashi2012-09-01-7/+14
| | | | | | | | | save_boot_params_default() in cpu.c accesses uninitialized stack area when it compiled with -O0 (not optimized). This patch removes save_boot_params_default() and put the equivalent in start.S Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp> Acked-by: Tom Rini <trini@ti.com>
* tegra20: Remove armv4t build flagsAllen Martin2012-09-01-14/+0
| | | | | | | | | | | These flags were necessary when building tegra20 as a single binary that supported ARM7TDMI and Cortex A9. Now that the ARM7TDMI support is split into a separate SPL, this is no longer necessary. Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* spl: fix SPL build of private libgccAllen Martin2012-09-01-0/+6
| | | | | | | | | | | | This fixes the SPL build to link with the SPL version of libgcc if USE_PRIVATE_LIBGCC is set to "yes". Previously it was linking with the libgcc from the normal u-boot build because it gets set in PLATFORM_LIBS and passed down the to the SPL build. Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* arm: enable libgcc build for SPLAllen Martin2012-09-01-1/+1
| | | | | | | | | Enable the building of private libgcc for SPL Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra20: enable SPL for tegra20 boardsAllen Martin2012-09-01-294/+105
| | | | | | | | | | | Add SPL options to tegra20 config files and enable SPL build for tegra20 boards. Also remove redundant code from u-boot that is not contained in SPL. Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra20: move SDRAM param save to later in bootAllen Martin2012-09-01-5/+3
| | | | | | | | | | | | Move warmboot_save_sdram_params() to later in the boot sequence. This code relies on devicetree to get the address of the memory controller and with upcoming changes for SPL boot it gets called early in the boot process when devicetree is not initialized yet. Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra20: add u-boot-*-tegra.bin targetsAllen Martin2012-09-01-0/+14
| | | | | | | | | | | | Add target for tegra20 u-boot image. This is a concatenation of tegra spl and normal u-boot binaries. For non-devicetree builds this is named "u-boot-nodtb-tegra.bin" for devicetree builds is named "u-boot-dtb-tegra.bin". Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: add tegra20 support to arm720tAllen Martin2012-09-01-1/+637
| | | | | | | | | | | | | Add support for tegra20 arm7 boot processor. This processor is used to power on the Cortex A9 and transfer control to it. In tegra this processor is an ARM7TDMI not an ARM720T, but since we don't use cache it was easier to just reuse the ARM720T code as the processors are otherwise identical except for cache and MMU. Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra20: remove timer_init from SPL buildAllen Martin2012-09-01-0/+2
| | | | | | | | | | Don't use timer_init from tegra board.c. This comes out of arm720t for the SPL build. Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: Fix arm720t SPL buildAllen Martin2012-09-01-0/+13
| | | | | | | | | | | | Take a few SPL fixes from armv7 and apply them to arm720t: -Use dummy exception handlers for SPL build -Initialize relocation register r9 to 0 for the case of no relocation -ifdef out interrupt handler code Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* MAKEALL: update to work with new boards.cfg syntaxAllen Martin2012-09-01-3/+6
| | | | | | | | | | Update MAKEALL to handle the optional SPL CPU field that was added to boards.cfg. This impacts the cases in MAKEALL that have to match against CPU type (field 3). In these cases use ':' as a field separator to split the u-boot CPU from the SPL CPU. Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
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