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* ARM: UniPhier: add PH1-sLD3 SoC supportMasahiro Yamada2015-07-23-16/+494
| | | | | | | The init code for UMC (Unified Memory Controller) and PLL has not been mainlined yet, but U-boot proper should work. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: UniPhier: update CONFIG_BOOTARGSMasahiro Yamada2015-07-23-1/+1
| | | | | | | Both "earlyprintk" and "loglevel=8" should be useful for the development. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: UniPhier: disable CONFIG_FITMasahiro Yamada2015-07-23-6/+0
| | | | | | | To use FIT boot, we have to describe Image Tree Source in addition. So, it is not intended for beginners. Disable it by default. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: UniPhier: add environment variable for TFTP bootMasahiro Yamada2015-07-23-0/+10
| | | | | | | The command "run tftpboot" downloads some files onto the RAM via TFTP and boots the kernel. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: UniPhier: add environment sets for non-FIT Linux bootMasahiro Yamada2015-07-23-18/+43
| | | | | | | | | | | Currently, the environment variables "norboot" and "nandboot" only work with CONFIG_FIT, but we do not want to depend on CONFIG_FIT to boot the kernel. This commit adds environments useful for booting Linux with separate uImage + ramdisk + DTB. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: dts: UniPhier: add device-specific compatible string for EEPROMMasahiro Yamada2015-07-23-1/+1
| | | | | | | | | | For the record, describe exactly which device of which vendor is used on this board. I2C EEPROM is bound by the generic compatible string, "i2c-eeprom", so this commit has no impact on the functionality. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2015-07-20-377/+1673
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| * armv8/fsl-lsch3: Fix TCR_EL3 for the final MMU setup.Zhichun Hua2015-07-20-15/+8
| | | | | | | | | | | | | | | | When final MMU table is setup in DDR, TCR attributes must match those of the memroy for cacheability and shareability. Signed-off-by: Zhichun Hua <zhichun.hua@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
| * armv8: Fix TCR macros for shareability attributeZhichun Hua2015-07-20-2/+2
| | | | | | | | | | | | | | | | For ARMv8, outer shareable is 0b10, inner shareable is 0b11 at bit position [13:12] of TCR_ELx register. Signed-off-by: Zhichun Hua <zhichun.hua@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
| * armv8/ls2085a/defconfig: Enable FSL_DSPI, OF_CONTROL and DM supportHaikun.Wang@freescale.com2015-07-20-0/+14
| | | | | | | | | | | | | | | | | | Freescale DSPI driver has been converted to Driver Model. The new driver depends on OF_CONTROL, DM, DM_SPI. This patch enable FSL_DSPI and its dependence configure options. Signed-off-by: Haikun Wang <haikun.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls2085ardb: Enable DSPI flash support for LS2085ARDBHaikun Wang2015-07-20-0/+8
| | | | | | | | | | | | | | Enable DSPI flash related configurations for LS2085ARDB. Signed-off-by: Haikun Wang <haikun.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls2085aqds: Enable DSPI flash support for LS2085AQDSHaikun Wang2015-07-20-0/+9
| | | | | | | | | | | | | | Enable DSPI flash related configurations. Signed-off-by: Haikun Wang <haikun.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls2085ardb: DSPI pin muxing configure through QIXIS CPLDHaikun.Wang@freescale.com2015-07-20-20/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | DSPI has pin muxing with SDHC and other IPs, this patch check the value of RCW SPI_PCS_BASE and SPI_BASE_BASE fields, it also check the "hwconfig" variable. If those pins are configured to DSPI and "hwconfig" enable DSPI, set the BRDCFG5 of QIXIS CPLD to configure the routing to on-board SPI memory. Otherwise will configure to SDHC. DSPI is enabled in "hwconfig" by appending "dspi", eg. setenv hwconfig "$hwconfig;dspi" Signed-off-by: Haikun Wang <Haikun.Wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls2085aqds: DSPI pin muxing configure through QIXISHaikun Wang2015-07-20-0/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | DSPI has pin muxing with SDHC and other IPs, this patch check the value of RCW SPI_PCS_BASE and SPI_BASE_BASE fields, it also check the "hwconfig" variable. If those pins are configured to DSPI and "hwconfig" enable DSPI, set the BRDCFG5 of QIXIS FPGA to configure the routing to on-board SPI memory. Otherwise will configure to SDHC. DSPI is enabled in "hwconfig" by appending "dspi", eg. setenv hwconfig "$hwconfig;dspi" Signed-off-by: Haikun Wang <haikun.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls2085a: Enable DSPI get input clk form 'mxc_get_clock'Haikun Wang2015-07-20-0/+3
| | | | | | | | | | Signed-off-by: Haikun Wang <haikun.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * arm/dts/ls2085a: Add dts files for LS2085AQDS and LS2085ARDBHaikun Wang2015-07-20-0/+90
| | | | | | | | | | | | | | Add dts source files for LS2085AQDS and LS2085ARDB boards. Signed-off-by: Haikun Wang <haikun.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * arm/dts/ls2085a: Add DSPI dts nodeHaikun Wang2015-07-20-0/+9
| | | | | | | | | | | | | | Add DSPI controller dts node in fsl-ls2085a.dtsi Signed-off-by: Haikun Wang <haikun.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * arm/dts/ls2085a: Bring in ls2085a dts files from linux kernelHaikun Wang2015-07-20-0/+120
| | | | | | | | | | | | | | | | Bring in required device tree files for ls2085a from Linux. These are initially unchanged and have a number of pieces not needed by U-Boot. Signed-off-by: Haikun Wang <Haikun.Wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * arm/ls102xa: Add little-endian mode support for audio IPsAlison Wang2015-07-20-1/+8
| | | | | | | | | | | | | | | | As SCFG_ENDIANCR register is added to choose little-endian or big-endian for audio IPs on Rev2.0 silion, little-endian mode is selected. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * arm/ls102xa: Add PSCI support for ls102xaWang Dongsheng2015-07-20-0/+134
| | | | | | | | | | | | | | | | | | | | | | | | Base on PSCI services, implement CPU_ON/CPU_OFF for ls102xa platform. Tested on LS1021AQDS, LS1021ATWR. Test CPU hotplug times: 60K Test kernel boot times: 1.2K Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Acked-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * ARMv7: Factor out reusable timer_wait from sunxi/psci_sun7i.SWang Dongsheng2015-07-20-40/+54
| | | | | | | | | | | | | | | | | | | | timer_wait is moved from sunxi/psci_sun7i.S, and it can be converted completely into a reusable armv7 generic timer. LS1021A will use it as well. Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * arm: ls1021a: Remove the inappropriate use of the function 'sprintf'Alison Wang2015-07-20-10/+11
| | | | | | | | | | | | | | | | | | | | | | As the function 'sprintf' does not check buffer boundaries but outputs to the buffer 'enet' of fixed size (16), this patch removes the function 'sprintf', and uses 'strcpy' instead. It will assign the character arrays 'enet' and 'phy' the corresponding character strings. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * board/ls2085a: Increase kernel_size value in env variablePrabhakar Kushwaha2015-07-20-3/+3
| | | | | | | | | | | | | | | | | | Linux itb image size has been increased from 30MB. So updating kernel_size to 40MB in env variable. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * board/ls2085rdb: Export functions for standalone AQ FW load appsPrabhakar Kushwaha2015-07-20-1/+48
| | | | | | | | | | | | | | | | | | Export functions required by Aquntia PHY firmware load application. functions are memset, strcpy, mdelay, mdio_get_current_dev, phy_find_by_mask, mdio_phydev_for_ethname and miiphy_set_current_dev Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * driver/ldpaa_eth:Avoid infinite loop in ldpaa_eth_rxPrabhakar Kushwaha2015-07-20-1/+8
| | | | | | | | | | | | | | | | Change infinite loop mechanism to timer based polling for QBMAN release in ldpaa_eth_rx. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * driver/ldpaa_eth: Avoid TX conf framesPrabhakar Kushwaha2015-07-20-111/+4
| | | | | | | | | | | | | | | | | | | | | | Polling of TX conf frames is not a mandatory option. Packets can be transferred via WRIOP without TX conf frame. Configure ldpaa_eth driver to use TX path without confirmation frame Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * driver/ldpaa_eth: Add timeout handling DQRR entry readPrabhakar Kushwaha2015-07-20-14/+22
| | | | | | | | | | | | | | | | | | | | | | Volatile command does not return frame immidiately, need to wait till a frame is available in DQRR. Ideally it should be a blocking call. Add timeout handling for DQRR frame instead of retry counter. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * driver/ldpaa_eth: Retry enqueue if portal was busyPrabhakar Kushwaha2015-07-20-2/+30
| | | | | | | | | | | | | | | | | | | | | | Do not immediately return if the enqueue function returns -EBUSY; re-try mulitple times. if timeout occures, release the buffer. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/fsl-lsch3: device tree fixups for PCI stream IDsStuart Yoder2015-07-20-0/+182
| | | | | | | | | | | | | | | | | | | | | | This patch adds the infrastructure to update device tree nodes to convey SMMU stream IDs in the device tree. Fixups are implemented for PCI controllers initially. Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * drivers/fsl-mc: dynamically create ICID pool in DPCStuart Yoder2015-07-20-0/+36
| | | | | | | | | | | | | | | | | | | | delete any existing ICID pools in the DPC and create a new one based on the stream ID partitioning for the SoC Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/fsl-lsch3: partition stream IDsStuart Yoder2015-07-20-5/+66
| | | | | | | | | | | | | | | | | | | | | | | | Stream IDs on ls2085a devices are not hardwired and are programmed by sw. There are a limited number of stream IDs available, and the partitioning of them is scenario dependent. This header defines the partitioning between legacy, PCI, and DPAA2 devices. Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * drivers: fsl-mc: Return error for major version mismatchPrabhakar Kushwaha2015-07-20-2/+7
| | | | | | | | | | | | | | | | | | | | Management complex major version should match to the firmware present in flash. Return error during mismatch of major version. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * drivers: fsl-mc: Update qbman driverPrabhakar Kushwaha2015-07-20-37/+53
| | | | | | | | | | | | | | | | | | | | | | | | Update qbman driver - As per latest available qbman driver - Use of atomic APIs Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> CC: Geoff Thorpe <Geoff.Thorpe@freescale.com> CC: Haiying Wang <Haiying.Wang@freescale.com> CC: Roy Pledge <Roy.Pledge@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * drivers: fsl-mc: Update flibs to mc-0.6.0.1Prabhakar Kushwaha2015-07-20-58/+199
| | | | | | | | | | | | | | | | | | | | Update flibs changes to mc-0.6.0.1 for dpmang, dprc, dpni and dpio objects Also rename qbman_portal_ce/ci_paddr to qbman_portal_ce/ci_offset in dpio_attr. These are now offsets from the SoC QBMan portals base. Signed-off-by: J. German Rivera <German.Rivera@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * drivers/fsl-mc: Autoload AOIP image from NOR flashJ. German Rivera2015-07-20-0/+29
| | | | | | | | | | | | | | | | | | Load AIOP image from NOR flash into DDR so that the MC firmware the MC fw can start it at boot time Signed-off-by: J. German Rivera <German.Rivera@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * driver/ldpaa_eth:Flush buffer before seeding BMAN after TX_confPrabhakar Kushwaha2015-07-20-0/+1
| | | | | | | | | | | | | | | | Flush buffer before releasing to BMan after TX_conf to ensure, the core does not have any cachelines that the WRIOP will DMA to. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * drivers/fsl-mc: Make MC boot error messages more readableJ. German Rivera2015-07-20-18/+13
| | | | | | | | | | | | | | | | | | Make it easier for the user to notice when the MC firmware had problems booting. Signed-off-by: J. German Rivera <German.Rivera@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls2085a: enable debug serverStuart Yoder2015-07-20-0/+1
| | | | | | | | | | | | Signed-off-by: Stuart Yoder <stuart.yoder at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/fsl-lsch3: Support 256M mem split for MC & dbg-srvrPrabhakar Kushwaha2015-07-20-6/+27
| | | | | | | | | | | | | | | | | | | | | | | | The agreed split of the top of memory is 256M for debug server and 256M for MC. This patch implements the split. In addition, the MC mem must be 512MB aligned, so the amount of memory to hide must be 512MB to achieve that alignment. Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * arm/errata: Update required bits for A57 cores erratasBhupesh Sharma2015-07-20-4/+4
| | | | | | | | | | | | | | | | | | | | This patch updates the setting of required bits for A57 cores erratas - 828024 and 826974 Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com> Signed-off-by: Dai Haruki <dai.haruki at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * driver/fsl_debug_server: Fix the DDR hide logic for LS2085aBhupesh Sharma2015-07-20-8/+5
| | | | | | | | | | | | | | | | | | | | This patch fixes the DDR hide logic for LS2085a, correcting the way the Debug Server FW and MC FW images are placed on the top of system DDR and how the rest of the system DDR space is made visibile to Linux. Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls2085a: Update SoC README for DDR layoutPrabhakar Kushwaha2015-07-20-0/+25
| | | | | | | | | | | | | | | | | | | | Update SoC README to provide details of - Memory regions - Memory used by MC and Debug server Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls2085a: Expose all DDR region(s) to LinuxBhupesh Sharma2015-07-20-18/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch allows u-boot to expose the complete DDR region(s) to Linux (after subtracting the memory hidden via MEM_TOP_HIDE mechanism). This allows the u-boot to support the 48-bit VA support provided by ARM64 Linux in flavors 3.18 and above, by passing the appropriate 'memory' DTS nodes. Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls2085ardb: Fix SPD address error on early boardsYork Sun2015-07-20-2/+21
| | | | | | | | | | | | | | | | | | Board rev C and earlier has duplicated SPD address on 2nd DDR controller slots. It is fixed on rev D and later. SPD addresses need to be updated accordingly. Signed-off-by: York Sun <yorksun at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
| * driver/ddr/fsl: Add a hook to update SPD addressYork Sun2015-07-20-0/+11
| | | | | | | | | | | | | | | | In case SPD address changes between board revisions, updating SPD address can be called from board file. Signed-off-by: York Sun <yorksun at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
| * armv8/ls2085a: Avoid hard-coding for board name printPrabhakar Kushwaha2015-07-20-7/+9
| | | | | | | | | | | | | | | | | | | | | | LS2085A supports 6 personalities i.e. LS2045AE, LS2045A, LS2080AE, LS2080A, LS2085AE and LS2085A personlities. Instead of hard-coding, board name should change as per selected personality. Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/fsl-ch3: Add support to print SoC personalityPrabhakar Kushwaha2015-07-20-0/+57
| | | | | | | | | | | | | | | | | | | | | | This patch adds support to print out the SoC personality. Freescale LS20xx SoCs (compliant to Chassis-3 specifications) can have 6 personalities: LS2045AE, LS2045A, LS2080AE, LS2080A, LS2085AE and LS2085A Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/fsl-lsch3: Fix DDR speed messageYork Sun2015-07-20-2/+2
| | | | | | | | | | | | | | DDR speed should be in MT/s, not MHz. Signed-off-by: York Sun <yorksun at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
| * armv8/ls2085RDB: Update board version print logicPrabhakar Kushwaha2015-07-20-1/+1
| | | | | | | | | | | | | | | | | | | | As per updated board document, no need to substract 1 from arch[BRD] bit field. Default value + 'A' represents the board revision. So update board version print logic to reflect the same. Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * board/fsl/common: Fix eeprom system version endiannessJaiprakash Singh2015-07-20-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | SYSTEM ID EPPROM always store SYSTEM version info in big endian format. SoC with ARM or PowerPC core should read/write version info from eeprom in BIG endian format. So use cpu-specific APIs to read SYSTEM version. Signed-off-by: Jaiprakash Singh <b44839 at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
generated by cgit v1.1 at 2024-11-09 13:52:28 +0000