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| * rockchip: video: Correct VOP clock selectionSimon Glass2016-11-25-6/+1
| | | | | | | | | | | | | | | | This code incorrectly uses the oscillator. It should use the clock selected in the device tree. Signed-off-by: Simon Glass <sjg@chromium.org> Fixes: 135aa95 (clk: convert API to match reset/mailbox style)
| * rockchip: video: Correct HDMI data source selectionSimon Glass2016-11-25-1/+2
| | | | | | | | | | | | | | | | | | | | This code currently always selects the second source. It only worked because both sources are set up. With the change to only init video devices that are present in the stdout environment variable, this fails. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dts: arm: rk3036: add usb vbus nodeKever Yang2016-11-25-4/+33
| | | | | | | | | | | | | | add fix regulator node for usb vbus power control. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * config: rk3036: enable fix regulatorKever Yang2016-11-25-0/+1
| | | | | | | | | | | | | | usb host vbus power is using gpio fix regulator, enable it. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * config: rk3036: enable configs for USB HOSTKever Yang2016-11-25-0/+10
| | | | | | | | | | | | | | rk3036 using dwc2 usb controller, need enable relate configs for it. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * config: evb-rk3399: enable PWM_ROCKCHIPKever Yang2016-11-25-0/+1
| | | | | | | | | | | | | | | | PWM_ROCKCHIP need to enable for PWM regulator, this config is missing during rebase and new patch set in previous submission. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * evb-rk3399: deduced the dram node size when space reservedKever Yang2016-11-25-1/+1
| | | | | | | | | | | | | | The size dram node need to be deduced by the same amount of reserved space. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * arm: rockchip: Fix typo in ROCKCHIP_RK3288 helpAndreas Färber2016-11-25-1/+1
| | | | | | | | | | | | | | UART,s -> UARTs, to avoid this spreading via copy&paste. Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Simon Glass <sjg@chromium.org>
| * arm: dts: Fix Rockchip sort orderAndreas Färber2016-11-25-1/+1
| | | | | | | | | | | | | | Sort rk3036 before rk3288. Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Simon Glass <sjg@chromium.org>
| * power: regulator: Add limits checking while setting currentKeerthy2016-11-25-0/+7
| | | | | | | | | | | | | | | | | | | | Currently the specific set ops functions are directly called without any check for min/max current limits for a regulator. Check for them and proceed. Signed-off-by: Keerthy <j-keerthy@ti.com> Fixed checking of current limits: Signed-off-by: Simon Glass <sjg@chromium.org>
| * power: regulator: Add limits checking while setting voltageKeerthy2016-11-25-0/+7
| | | | | | | | | | | | | | | | | | | | | | Currently the specific set ops functions are directly called without any check for voltage limits for a regulator. Check for them and proceed. Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Fixed checking of voltate limits: Signed-off-by: Simon Glass <sjg@chromium.org>
| * power: regulator: Introduce regulator_set_value_force functionKeerthy2016-11-25-1/+28
| | | | | | | | | | | | | | | | | | In case we want to force a particular value on a regulator irrespective of the min/max constraints for testing purposes one can call regulator_set_value_force function. Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | Merge git://git.denx.de/u-boot-fdtTom Rini2016-11-25-1/+1
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| * | MAINTAINERS: Fix syntax and update filename for FDTAndreas Färber2016-11-25-1/+1
| |/ | | | | | | | | | | | | | | Let get_maintainers.pl pick up the new cmd/fdt.c. Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* | Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-11-25-145/+2025
|\ \ | | | | | | | | | | | | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: arch/arm/Kconfig
| * | image-fit: Fix compiling error caused by autoconf.hYork Sun2016-11-23-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit ec6617c3 includes autoconf.h in image-fit.c, causing conflict for board odroid-xu3 which overwrites CONFIG_SYS_BOARD in header file. Move the include higher and use linux/kconfig.h instead of generated/autoconf.h. Signed-off-by: York Sun <york.sun@nxp.com> CC: Alison Wang <alison.wang@nxp.com>
| * | armv7: ls1021aiot: Fixing SPL compiling issuesYork Sun2016-11-23-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | To align with SPL change 38fed8ab and 693d4c9f, add Kconfig option CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR to defconfig, and remove CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS. Signed-off-by: York Sun <york.sun@nxp.com> CC: Feng Li <feng.li_2@nxp.com>
| * | armv8: fsl-layerscape: Support loading 32-bit OS with PSCI enabledAlison Wang2016-11-22-0/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As PSCI and secure monitor firmware framework are enabled, this patch is to support loading 32-bit OS in such case. The default target exception level returned to U-Boot is EL2, so the corresponding work to switch to AArch32 EL2 and jump to 32-bit OS are done in U-Boot and secure firmware together. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: fsl-layerscape: SMP support for loading 32-bit OSAlison Wang2016-11-22-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Spin-table method is used for secondary cores to load 32-bit OS. The architecture information will be got through checking FIT image and saved in the os_arch element of spin-table, then the secondary cores will check os_arch and jump to 32-bit OS or 64-bit OS automatically. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: Support loading 32-bit OS in AArch32 execution stateAlison Wang2016-11-22-71/+416
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To support loading a 32-bit OS, the execution state will change from AArch64 to AArch32 when jumping to kernel. The architecture information will be got through checking FIT image, then U-Boot will load 32-bit OS or 64-bit OS automatically. Signed-off-by: Ebony Zhu <ebony.zhu@nxp.com> Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | arm: exynos7420: remove custome low level init functionThomas Abraham2016-11-22-8/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the custom low-level initialization function and reuse the default low-level initialization function. But this requires the ARMV8_MULTIENTRY config option to be enabled for Exynos7420. On Exynos7420, the boot CPU belongs to the second cluster and so with ARMV8_MULTIENTRY config option enabled, the 'branch_if_master' macro fails to detect the CPU as boot CPU. As a temporary workaround the CPU_RELEASE_ADDR is set to point to '_main'. Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Alison Wang <alison.wang@nxp.com> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Reviewed-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8/fsl-lsch3: Update code to release secondary coresPriyanka Jain2016-11-22-5/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | NXP ARMv8 SoC LS2080A release all secondary cores in one-go. But other new SoCs like LS2088A, LS1088A release secondary cores one by one. Update code to release secondary cores based on SoC SVR Add code to release cores one by one for non LS2080A SoCs Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: remove "inline" from declaration of initiator_type] Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: fsl-layerscape: Add NXP LS2088A SoC supportPriyanka Jain2016-11-22-15/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The QorIQ LS2088A SoC is built on layerscape architecture. It is similar to LS2080A SoC with some differences like 1)Timer controller offset is different 2)It has A72 cores 3)It supports TZASC module Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: fsl-layerscape : Check SVR for initializing TZASCPriyanka Jain2016-11-22-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS2080 SoC and its personalities does not support TZASC But other new SoCs like LS2088A, LS1088A supports TZASC Hence, skip initializing TZASC for Ls2080A based on SVR Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: fsl-layerscape: Update TZASC registers typePriyanka Jain2016-11-22-14/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TZASC registers like TZASC_GATE_KEEPER, TZASC_REGION_ATTRIBUTES are 32-bit regsiters. So while doing register load-store operations, 32-bit intermediate register, w0 should be used. Update x0 register to w0 register type. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: lsch3: Use SVR based timer base address detectionPriyanka Jain2016-11-22-3/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Timer controller base address has been changed from LS2080A SoC (and its personalities) to new SoCs like LS2088A, LS1088A. Use SVR based timer base address detection to avoid compile time #ifdef. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: lsch3: Add generic get_svr() in assemblyPriyanka Jain2016-11-22-3/+14
| | | | | | | | | | | | | | | Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8/fsl-layerscape: Update CONFIG_LS2080A to CONFIG_FSL_LSCH3Shengzhou Liu2016-11-21-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | Update CONFIG_LS2080A to CONFIG_FSL_LSCH3 to make those workaround implementing of erratum reusable for more SoCs. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: fsl-layerscape: Add README for deploying QSPI imageYuan Yao2016-11-21-0/+42
| | | | | | | | | | | | | | | | | | Signed-off-by: Yuan Yao <yao.yuan@nxp.com> [YS: Reviese commit subject] Reviewed-by: York Sun <york.sun@nxp.com>
| * | arm: ls1021a: improve the core frequency to 1.2GHZYuan Yao2016-11-21-7/+7
| | | | | | | | | | | | | | | | | | | | | Change core clock to 1.2GHz in the configurations for SD and NAND boot. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: ls2080aqds: fix SGMII repeater settingsShaohui Xie2016-11-21-5/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current value to check whether the PHY was configured has dependency on MC, it expects MC to start PCS AN, this is not true during boot up, so it should be changed to remove the dependency. The PHY's register space should be restore to default after accessing extended space. Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | fsl: serdes: fix a deadloop issue for P4080Hou Zhiqiang2016-11-21-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This deadloop is introduced by commit: 71fe222 fsl: serdes: ensure accessing the initialized maps of serdes protocol deadloop detail: cpu_init_r => fsl_serdes_init => p4080_erratum_serdes_a005 => is_serdes_configured => fsl_serdes_init Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | powerpc: mpc512x: Add support for get_svr() for mpc512x devicesSriram Dash2016-11-21-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | Defines get_svr() for mpc512x devices Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | driver: net: ldpaa_eth: Fix missing bracket issuePriyanka Jain2016-11-21-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: ls2080a: Update serdes protocol supportPriyanka Jain2016-11-21-3/+125
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add these serdes protocols Serdes1: 0x39, 0x4B, 0x4C, 0x4D Serdes2: 0x47, 0x57 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> [YS: Revise commit message] Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: ls1046aqds: add lpuart supportShaohui Xie2016-11-21-0/+131
| | | | | | | | | | | | | | | | | | | | | LPUART0 is used by default, and it's using platform clock. Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | lpuart: add a get_lpuart_clk functionShaohui Xie2016-11-21-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It's not always true that LPUART clock is CONFIG_SYS_CLK_FREQ. This patch provides a weak function get_lpuart_clk(), so that the clock can be ovreridden on a specific board which uses different clock for LPUART. Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> [YS: Reformat commit message] Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv7: Add support of ls1021a-iot boardFeng Li2016-11-21-1/+999
| | | | | | | | | | | | | | | | | | | | | | | | The patch adds support for Freescale ls1021a-iot board. Signed-off-by: Feng Li <feng.li_2@nxp.com> [YS: rewrite commit message, fix whitespace in Kconfig] Reviewed-by: York Sun <york.sun@nxp.com>
| * | configs: ls2080ardb: Enable DSPI flash supportYuan Yao2016-11-21-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | There is the stmicro DSPI flash on LS12080ARDB. Enable DSPI flash related configure options. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8:ls1012a: Update bootargs for fast-bootPratiyush Srivastava2016-11-21-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add optimization parameters like "quiet" in bootargs to reduce the system boot time Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com> Signed-off-by: Harninder Rai <harninder.rai@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | | colibri_pxa270: transition to driver model for serialMarcel Ziswiler2016-11-23-4/+18
| | | | | | | | | | | | | | | | | | | | | Add serial platform data to board file. Enable driver model for PXA serial driver. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
* | | colibri_pxa270: drop edit, elf, fpga, hush, regex et al. for space reasonMarcel Ziswiler2016-11-23-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | With em humble DM and Kconfig migraters U-Boot binary size keeps increasing. Drop a bunch of less needed stuff to save another precious 20+ KB. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
* | | serial: pxa: integrate optional driver model handlingMarcel Ziswiler2016-11-23-70/+169
| | | | | | | | | | | | | | | | | | | | | Optional driver model handling integration. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Marek Vasut <marex@denx.de>
* | | serial: pxa: use kconfig for serial configurationMarcel Ziswiler2016-11-23-5/+9
| |/ |/| | | | | | | | | | | Migrate the PXA serial driver to be configured via Kconfig. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Marek Vasut <marex@denx.de>
* | MAINTAINERS: SUNXI: Update maintainershipJagan Teki2016-11-22-2/+4
| | | | | | | | | | | | | | Add Jagan and Maxime as Maintainers for SUNXI Signed-off-by: Jagan Teki <jagan@openedev.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2016-11-22-460/+409
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| * | sf: Add support for MX66U51235F, MX66L1G45G, MT25QU02G, MT25QL02GRadu Bacrau2016-11-22-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds support for the Macronix MX66U51235F, MX66L1G45G and Micron MT25QU02G, MT25QL02G flash parts. Signed-off-by: Radu Bacrau <dumitru.bacrau@intel.com> Cc: Chin Liang See <clsee@altera.com> Cc: Radu Bacrau <radu.bacrau@gmail.com> [Update proper commit header and 80-line cut on body] Reviewed-by: Jagan Teki <jagan@openedev.com>
| * | drivers: SPI: sunxi SPL: fix warningAndre Przywara2016-11-21-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Somehow an int returning function without a return statement sneaked in, fix it. Also fix some whitespace damage on the way. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * | sf: Fix s25fs512s id tableJagan Teki2016-11-19-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | s25fs512s and s25fl512s_256k have common id information till 5 bytes and 6th byte have different family id like FS and FL-S as 0x81 and 0x80. Reported-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Jagan Teki <jagan@openedev.com>
| * | sf: dataflash: Minor cleanupsJagan Teki2016-11-19-23/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - fix single line comments - remove unneeded spaces - ascending order of include files - rename SPI DATAFLASH to dataflash - rename SPI DataFlash to dataflash - return NULL replaced with error code Cc: Bin Meng <bmeng.cn@gmail.com> Cc: York Sun <york.sun@nxp.com> Signed-off-by: Jagan Teki <jagan@openedev.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jagan@openedev.com>
generated by cgit v1.1 at 2024-10-07 07:20:26 +0000