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* ARM: Put target PC for PSCI CPU_ON on per-CPU stackJan Kiszka2015-05-13-9/+11
| | | | | | | | | | | | | | Use a per-CPU variable for saving the target PC during CPU_ON operations. This allows us to run this service independently on targets that have more than 2 cores and also core-local power control. CC: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Tested-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: Factor out reusable psci_get_cpu_stack_topJan Kiszka2015-05-13-10/+19
| | | | | | | | | | | | | This algorithm will be useful on Tegra as well, plus we will need it for making _psci_target_pc per-CPU. CC: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Tested-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: Factor out reusable psci_cpu_entryJan Kiszka2015-05-13-18/+25
| | | | | | | | | | | | | | | | _sunxi_cpu_entry can be converted completely into a reusable psci_cpu_entry. Tegra124 will use it as well. As with psci_disable_smp, also the enabling is designed to be overloaded in cased SMP is not controlled via ACTLR. CC: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Tested-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: Factor out reusable psci_cpu_off_commonJan Kiszka2015-05-13-62/+78
| | | | | | | | | | | | | | | | | | Move parts of sunxi's psci_cpu_off into psci_cpu_off_common, namely cache disabling and flushing, clrex and the disabling of SMP for the dying CPU. These steps are apparently generic for ARMv7 and will be reused for Tegra124 support. As the way of disabled SMP is not architectural, though commonly done via ACLTR, the related function can be overloaded. CC: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Tested-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: Factor out common psci_get_cpu_idJan Kiszka2015-05-13-5/+15
| | | | | | | | | | | | | | | | Will be required for obtaining the ID of the current CPU in shared PSCI functions. The default implementation requires a dense ID space and only supports a single cluster. Therefore, the functions can be overloaded in cases where these assumptions do not hold. CC: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Tested-by: Ian Campbell <ijc@hellion.org.uk> Acked-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: Clean up CONFIG_ARMV7_NONSEC/VIRT/PSCI conditionsJan Kiszka2015-05-13-13/+13
| | | | | | | | | | | | | | CONFIG_ARMV7_VIRT depends on CONFIG_ARMV7_NONSEC, thus doesn't need to be taken into account additionally. CONFIG_ARMV7_PSCI is only set on boards that support CONFIG_ARMV7_NONSEC, and it only works on those. CC: Tang Yuantian <Yuantian.Tang@freescale.com> CC: York Sun <yorksun@freescale.com> CC: Steve Rae <srae@broadcom.com> CC: Andre Przywara <andre.przywara@linaro.org> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Tested-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: enable STDIO deregistrationStephen Warren2015-05-13-0/+3
| | | | | | | | | | | At the very least when USB keyboard support is enabled, we need to enable CONFIG_SYS_STDIO_DEREGISTER, so the "usb reset" is able to re-scan USB ports and find new devices. Enable it everywhere per request from Simon Glass. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: CONFIG_{SYS_, }LOAD{_, }ADDR rationalizationStephen Warren2015-05-13-20/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As best I can tell, CONFIG_SYS_LOAD_ADDR and CONFIG_LOADADDR/$loadaddr serve essentially the same purpose. Roughly, if a command takes a load address, then CONFIG_SYS_LOAD_ADDR or $loadaddr (or both) are the default if the command-line does not specify the address. Different U-Boot commands are inconsistent re: which of the two default values they use. As such, set the two to the same value, and move the logic that does this into tegra-common-post.h so it's not duplicated. A number of other non- Tegra boards do this too. The values chosen for these macros are no longer consistent with anything in MEM_LAYOUT_ENV_SETTINGS. Regain consistency by setting $kernel_addr_r to CONFIG_LOADADDR. Older scripts tend to use $loadaddr for the default kernel load address, whereas newer scripts and features tend to use $kernel_addr_r, along with other variables for other purposes such as DTBs and initrds. Hence, it's logical they should share the same value. I had originally thought to make the $kernel_addr_r and CONFIG_LOADADDR have different values. This would guarantee no interference if a script used the two variables for different purposes. However, that scenario is unlikely given the semantic meaning associated with the two variables. The lowest available value is 0x90200000; see comments for MEM_LAYOUT_ENV_SETTINGS in tegra30-common-post.h for details. However, that value would be problematic for a script that loaded a raw zImage to $loadaddr, since it's more than 128MB beyond the start of SDRAM, which would interfere with the kernel's CONFIG_AUTO_ZRELADDR. So, let's not do that. The only potential fallout I could foresee from this patch is if someone has a script that loads the kernel to $loadaddr, but some other file (DTB, initrd) to a hard-coded address that the new value of $loadaddr interferes with. This seems unlikely. A user should not do that; they should either hard-code all load addresses, or use U-Boot-supplied variables for all load addresses. Equally, any fallout due to this change is trivial to fix; simply modify the load addresses in that script. Cc: Paul Walmsley <pwalmsley@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Paul Walmsley <pwalmsley@nvidia.com> Reviewed-by: Simon Glass Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra124: video: Add full link training for eDPSimon Glass2015-05-13-64/+1084
| | | | | | | | | Add full link training as a fallback in case the fast link training fails. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: config: nyan-big: Enable LCDSimon Glass2015-05-13-0/+16
| | | | | | | | Add the PMIC, LCD settings, PWM and also show the board info at the top of the LCD when starting up. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: video: support eDP displays on Tegra124 devicesSimon Glass2015-05-13-0/+523
| | | | | | | | | Connect up the clocks and the eDP driver to make these displays work with Tegra124-based devices. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: video: Add Embedded DisplayPort driverSimon Glass2015-05-13-0/+1265
| | | | | | | | | | This interface is used on laptop devices based on Tegra. Add a driver which provides access to the eDP interface. The driver uses the display port uclass. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: video: Support serial output resource (SOR) on tegra124Simon Glass2015-05-13-0/+1815
| | | | | | | | | The SOR is required for talking to eDP LCD panels. Add a driver for this which will be used by the DisplayPort driver. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: dts: nyan-big: Add definitions for eDP displaySimon Glass2015-05-13-0/+43
| | | | | | | Add the various host1x peripherals to allow an eDP display to be connected. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* dm: video: Add a uclass for display portSimon Glass2015-05-13-0/+106
| | | | | | | | | eDP (Embedded DisplayPort) is a standard widely used in laptops to drive LCD panels. Add a uclass for this which supports a few simple operations. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* edid: Add a function to read detailed monitor timingsSimon Glass2015-05-13-0/+124
| | | | | | | | | For digital displays (such as EDP LCDs) we would like to read the EDID information and use that to set display timings. Provide a function to do this. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* video: Add drm_dp_helper.hSimon Glass2015-05-13-0/+405
| | | | | | | | | This file (from Linux 3.17) provides defines for display port. Use it so that our naming is consistent with Linux. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: Move display controller header into commonSimon Glass2015-05-13-12/+55
| | | | | | | Allow this to be used by other Tegra SoCs. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra124: clock: Add display clocks and functionsSimon Glass2015-05-13-9/+173
| | | | | | | | Add functions to provide access to the display clocks on Tegra124 including setting the clock rate for an EDP display. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: clock: Split the clock source code into a separate functionSimon Glass2015-05-13-22/+40
| | | | | | | | | Create a function which sets the source clock for a peripheral, given the number of mux bits to adjust. This can then be used more generally. For now, don't export it. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: clock: Add checking for invalid clock IDsSimon Glass2015-05-13-4/+29
| | | | | | | | | The get_pll() function can do the wrong thing if passed values that are out of range. Add checks for this and add a function which can return a 'simple' PLL. This can be defined by SoCs with their own clocks. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: config: Use CONFIG_LCD to detect LCD presenceSimon Glass2015-05-13-1/+1
| | | | | | | | Instead of CONFIG_VIDEO_TEGRA, use CONFIG_LCD to determine whether an LCD is present. Tegra124 uses a different driver. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra124: dts: Add host1x node to provide display informationSimon Glass2015-05-13-0/+456
| | | | | | | | This peripheral is required to get the LCD display running. Add it to tegra124 and also bring in the binding file from Linux 3.18 Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: nyan-big: Add LCD PMIC init and board IDSimon Glass2015-05-13-1/+37
| | | | | | | | Add required setup for the LCD display, and a function to provide the board ID. This requires GPIOs to be available prior to relocation. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: Add support for setting up a as3722 PMICSimon Glass2015-05-13-0/+7
| | | | | | | Add support for this PMIC which is used on some Tegra124 boards. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: Provide a function to allow LCD PMIC setupSimon Glass2015-05-13-0/+18
| | | | | | | Some LCDs require a PMIC to be set up - add a function for this. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* power: Export register access functions from as3722Simon Glass2015-05-13-3/+16
| | | | | | | | With the full PMIC framework we may be able to avoid this. But for now we need access to the PMIC. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: Add a board ID functionSimon Glass2015-05-13-6/+17
| | | | | | | Add a way of displaying a numeric board ID on start-up. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: Move checkboard() into the board codeSimon Glass2015-05-13-12/+9
| | | | | | | | This is only used by Nvidia boards, so move it into nvidia/common to simplify things. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: pwm: Allow the clock rate to be left as isSimon Glass2015-05-13-2/+5
| | | | | | | | When enabling a PWM, allow the existing clock rate and source to stand unchanged. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: Move the pwm into tegra-commonSimon Glass2015-05-13-52/+80
| | | | | | | | This is needed for tegra124 also, so make it common and add a header file for tegra124. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* fdt: Add binding decode function for display-timingsSimon Glass2015-05-13-0/+279
| | | | | | | | This is useful for display parameters. Add a simple decode function to read from this device tree node. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* dm: gpio: Add error handling and a function to claim vector GPIOsSimon Glass2015-05-13-6/+47
| | | | | | | | | gpio_get_values_as_int() should return an error if something goes wrong. Also provide gpio_claim_vector(), a function to request the GPIOs and set them to input mode. Otherwise callers have to do this themselves. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* dm: core: Sort the uclassesSimon Glass2015-05-13-16/+16
| | | | | | | Sort uclasses into alphabetical order and tidy up the comments. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* Clean all defconfigs with savedefconfigJoe Hershberger2015-05-12-1614/+1335
| | | | | | | | | | | | | In order to reduce merge conflicts and to maintain the simplest possible defconfig files, we should be using the savedefconfig feature of Kconfig every time a new feature is added. This keeps the defconfig settings to a minimum (only those things not default) and keeps them in the same order as the Kconfig options. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Cc: Tom Rini <trini@konsulko.com>
* arch: Make board selection choices optionalJoe Hershberger2015-05-12-0/+56
| | | | | | | | | | | | By making the board selections optional, every defconfig will include the board selection when running savedefconfig so if a new board is added to the top of the list of choices the former top's defconfig will still be correct. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Cc: Tom Rini <trini@konsulko.com>
* Revert "stm32f4: fix serial output"Tom Rini2015-05-10-3/+0
| | | | | | | | | As per the author, we don't need this patch really since the other patch "stm32f4: fix serial output" superseded it. This reverts commit 85e5f5b7a7f8d889271f94791606cde62d81d53f. Signed-off-by: Tom Rini <trini@konsulko.com>
* kconfig: Move REGEX to KconfigJoe Hershberger2015-05-10-6/+40
| | | | | | | Having this as a Kconfig allows it to be a dependent feature. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* ppc4xx: Remove sc3 boardStefan Roese2015-05-10-1907/+1
| | | | | | | | | | | | | | | | As this board seems to be unmaintained for quite some time, and its not moved to the generic board ingrastructure, lets remove it. This will also enable us to remove the CONFIG_AUTOBOOT_DELAY_STR2 and CONFIG_AUTOBOOT_STOP_STR2 macros, as this sc3 board is the only one using one of this macros. A removal patch will follow soon. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Juergen Beisert <jbeisert@eurodsn.de> Acked-by: Heiko Schocher <hs@denx.de>
* serial: fdt: add device tree support for pl01xVikas Manocha2015-05-10-1/+36
| | | | | | | This patch adds device tree support for arm pl010/pl011 driver. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Acked-by: Simon Glass <sjg@chromium.org>
* Fix broken verify functionality in crc32 commandJoe Hershberger2015-05-10-1/+1
| | | | | | | | | | | | | | Introduced in change d20a40de9db07de1f1f06a79a4da1cdda5379b75 "Roll crc32 into hash infrastructure" The crc32 command with no -v expects an optional 3rd argument to be an address to store the result in. With the -v switch, the last argument is a crc, not an address. In the case where -v is set, we should set the HASH_FLAG_ENV flag since that will first look for the value to be a digest value, which matches the expected API for the crc32 command. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* Fix inconsistency of VERIFY defines in cmd_memJoe Hershberger2015-05-10-3/+3
| | | | | | | | | | Introduced in change d20a40de9db07de1f1f06a79a4da1cdda5379b75 "Roll crc32 into hash infrastructure" Use a consistent define to enable the verify feature in crc32 command. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Simon Glass <sjg@chromium.org>
* Makefile: add a symbol link tags for ctagsDu Huanpeng2015-05-10-0/+1
| | | | Signed-off-by: Du Huanpeng <u74147@gmail.com>
* stv0991: use fdt for serial port platform dataVikas Manocha2015-05-10-0/+2
| | | | | | | | This patch ignores the serial port static platform data at compilation time in case of device tree control. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* stv0991: fdt: add stv0991 device treeVikas Manocha2015-05-10-1/+28
| | | | | | | | | This patch adds device tree for the ST Micro stv0991 board & enables device tree control. Progressively device tree support for the drivers being used will also be added. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* overo: Fix regression introduced in a6b541bArun Bharadwaj2015-05-10-14/+0
| | | | | | | | | | | | | | | | U-Boot has been broken on Overo boards since commit a6b541b09022acb6f7c2754100ae26bd44eed1d9. This is because the gd pointer is not set early enough anymore, such that the i2c_set_bus_num in get_board_revision can safely execute. This results in a console hang at SPL and the boot does not proceed. This piece of code is anyway necessary only for really old Overo boards with revision numbers <= 2410 and not required for the newer boards. For these older boards, u-boot v2014.10 still works fine. Signed-off-by: Arun Bharadwaj <arun@gumstix.com>
* overo: Split overo.c into spl.c, common.c and overo.cArun Bharadwaj2015-05-10-379/+425
| | | | | | | | | | | This separates the SPL-specific code from the u-boot-specific code for the Overo board following the discussion at http://lists.denx.de/pipermail/u-boot/2015-April/211622.html The code is split up into spl.c, overo.c and common.c (which has the code common to both) Signed-off-by: Arun Bharadwaj <arun@gumstix.com>
* omap3: overo: Allow boot with kernel in UBI rootfsAsh Charles2015-05-10-0/+13
| | | | | | | | | | If regular NAND booting fails to find a valid uImage in the kernel partition in NAND, try to boot using a zImage and dtb found in a UBI volume in the rootfs partition. This is the NAND analog of mmc zImage booting for device-tree based kernels. Signed-off-by: Ash Charles <ashcharles@gmail.com> Signed-off-by: Arun Bharadwaj <arun@gumstix.com>
* omap3: overo: Use software BCH8 ECC for NANDAsh Charles2015-05-10-4/+15
| | | | | | | | | | | | | | | | | | | | | Overo COMs have NAND flash that requires 4-bit ECC or better except for the first sector which can use 1-bit ECC. The boot ROM expects to load a payload from NAND written using 1-bit hardware-based ECC. In short, write SPL to NAND something like this (4 times for redundancy): #> nandecc hw #> nand write ${loadaddr} 0x0 ${filesize} #> nand write ${loadaddr} 0x20000 ${filesize} #> nand write ${loadaddr} 0x40000 ${filesize} #> nand write ${loadaddr} 0x60000 ${filesize} Then, switch back to software-based BCH8 for everything else: #> nandecc sw bch8 After [1], enlarge the max size of the SPL so the BCH code can fit. [1] https://www.mail-archive.com/u-boot@lists.denx.de/msg163912.html Signed-off-by: Ash Charles <ashcharles@gmail.com>
* overo: Add support for Palo35 expansion boardAsh Charles2015-05-10-0/+1
| | | | Signed-off-by: Ash Charles <ashcharles@gmail.com>
generated by cgit v1.1 at 2024-11-09 20:51:33 +0000