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* armv8/ls2085ardb: Enable NAND SPL supportScott Wood2015-04-23-5/+58
| | | | | | | | | | Enable NAND boot support using SPL framework. To boot from NAND, either use DIP switches on board, or "qixis_reset nand" command. Details of forming NAND image can be found in README. Signed-off-by: Scott Wood <scottwood@freescale.com> [York Sun: Remove +S from defconfig after commit 252ed872] Signed-off-by: York Sun <yorksun@freescale.com>
* freescale/qixis: Add support for booting from NANDScott Wood2015-04-23-10/+21
| | | | | | | Use "qixis_reset nand" to reset the board to boot from NAND. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
* armv8/ls2085aqds: NAND boot supportScott Wood2015-04-23-8/+278
| | | | | | | | | This adds NAND boot support for LS2085AQDS, using SPL framework. Details of forming NAND image can be found in README. Signed-off-by: Scott Wood <scottwood@freescale.com> [York Sun: Remove +S from defconfig after commit 252ed872] Signed-off-by: York Sun <yorksun@freescale.com>
* driver/ifc: Add 64KB page supportJaiprakash Singh2015-04-23-71/+126
| | | | | | | | | | | | | | | | IFC has two register pages.Till IFC version 1.4 each register page is 4KB each.But IFC ver 2.0 register page size is 64KB each.IFC regiters structure is break into two viz FCM and RUNTIME.FCM(Flash control machine) registers are defined in PAGE0 and controls IFC generic functionality. RUNTIME registers are defined in PAGE1 and controls NAND and GPCM funcinality. FCM and RUNTIME structures defination is common for IFC version 1.4 and 2.0. Signed-off-by: Jaiprakash Singh <b44839@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
* board/ls2085qds: Add support ethernetPrabhakar Kushwaha2015-04-23-13/+488
| | | | | | | | | Add support of ethernet: - eth.c: mapping lane to slot for (0x2A, 0x07) - ls2085a.c: To enable/disable dpmac and get link type Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
* armv8/ls2085ardb: Add support of LS2085ARDB platformYork Sun2015-04-23-2/+975
| | | | | | | | | | The LS2085ARDB is a evaluation platform that supports LS2085A family SoCs. This patch add sbasic support for the platform. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* armv8/ls2085aqds: Add support of LS2085AQDS platformYork Sun2015-04-23-15/+1148
| | | | | | | | | The LS2085AQDS is an evaluatoin platform that supports the LS2085A family SoCs. This patch add basic support of the platform. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
* driver/ldpaa: Add support of WRIOP static data structurePrabhakar Kushwaha2015-04-23-6/+250
| | | | | | | | | | | | Wire rate IO Processor (WRIOP) provide support of receive and transmit ethernet frames from the ethernet MAC. Here Each WRIOP block supports upto 64 DPMACs. Create a house keeping data structure to support upto 16 DPMACs and store external phy related information. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
* armv8/fsl-ch3: Add support to print RCW configurationBhupesh Sharma2015-04-23-0/+14
| | | | | | | | This patch adds support to print out the Reset Configuration Word information. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
* net/memac_phy: reuse driver for little endian SoCsShaohui Xie2015-04-23-24/+46
| | | | | | | | | | | | | The memac for PHY management on little endian SoCs is similar on big endian SoCs, so we modify the driver by using I/O accessor function to handle the endianness, so the driver can be reused on little endian SoCs, we introduce CONFIG_SYS_MEMAC_LITTLE_ENDIAN for little endian SoCs, if the CONFIG_SYS_MEMAC_LITTLE_ENDIAN is defined, the I/O access is little endian, if not, the I/O access is big endian. Move fsl_memac.h out of powerpc include. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
* drivers/fsl-mc: Changed MC firmware loading for new boot architectureJ. German Rivera2015-04-23-131/+395
| | | | | | | | | | | Changed MC firmware loading to comply with the new MC boot architecture. Flush D-cache hierarchy after loading MC images. Add environment variables "mcboottimeout" for MC boot timeout in milliseconds, "mcmemsize" for MC DRAM block size. Check MC boot status before calling flib functions. Signed-off-by: J. German Rivera <German.Rivera@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
* net/phy/cortina: Fix compilation warningpankaj chauhan2015-04-23-2/+2
| | | | | | | | Fix comilation warning which is emitted when firmware address is more than 32 bit. Signed-off-by: pankaj chauhan <pankaj.chauhan@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
* armv8: Add SerDes framework for Layerscape ArchitectureMinghuan Lian2015-04-23-0/+313
| | | | | | | | | | | Add support of SerDes framework for Layerscape Architecture. - Add support of 2 SerDes block - Add SerDes protocol parsing and detection - Create table of SerDes protocol supported by LS2085A Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* driver/ldpaa_eth: Update ldpaa ethernet driverPrabhakar Kushwaha2015-04-23-24/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | Fix flush_dcache_range() input parameter to use start and end addresses. Change ethernet interface name to DPNI. Update entry criteria for ldpaa_eth_stop. Ethernet stack first stop the device before performing next operation. At the time of Ethernet driver registration, net_dev->state is set as ETH_STATE_INIT So take care net_dev->state as ETH_STATE_INIT in ldpaa_eth_stop. Undef CONFIG_PHYLIB temorarily because ldpaa_eth driver currently does not support PHYLIB. Instead of clearing pull descriptor one time, clear it before issuing any volatile dequeue command. Volatile command does not return frame immidiately, wait till a frame is available in DQRR. This frame can be valid or expired. Flush buffer before releasing to BMan ensure the core does not have any cachelines that the WRIOP will DMA to. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: pankaj chauhan <pankaj.chauhan@freescale.com> Signed-off-by: Roy Pledge <Roy.Pledge@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
* armv8/fsl-lsch3: Use correct compatible for serial clock fixupScott Wood2015-04-23-1/+1
| | | | | | | | The serial nodes in the fsl-lsch3 device trees have compatible = "fsl,ns16550", "ns16550a" -- so don't look for "ns16550". Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
* armv8/ls2085a: Add workaround for USB erratum A-008751Scott Wood2015-04-23-0/+16
| | | | | | | | Without this "USB may not work" according to the erratum text, though I did not notice a problem without it. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
* fsl-lsch3: Introduce place for common early SoC initScott Wood2015-04-23-2/+25
| | | | | Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
* armv8/fsl-lsch3: Update early MMU tableYork Sun2015-04-23-17/+45
| | | | | | | | | | | | | During booting, IFC is mapped to low region. After booting up, IFC is remapped to high region for larger space. The environmental variables are also stored at high region. In order to read the variables during booting, a virtual mapping is required. Cache was enabled for entire IFC space before. Actually the first two entries are big enough (4MB) to cover the boot code and environmental variables. Remove extra entries. Move OCRAM entry out of ifdef. Signed-off-by: York Sun <yorksun@freescale.com>
* armv8/fsl-lsch3: Set nodes in DVM domainScott Wood2015-04-23-0/+15
| | | | | | | This is required for TLB invalidation broadcasts to work. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
* armv8/ls2085a: Add support for reset requestpankaj chauhan2015-04-23-7/+11
| | | | | | | Add support for reset_cpu() by asserting RESET_REQ_B. Signed-off-by: pankaj chauhan <pankaj.chauhan@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
* armv8/ls2085a: Fix generic timer clock sourceYork Sun2015-04-23-19/+51
| | | | | | | | | | The timer clock is system clock divided by 4, not fixed 12MHz. This is common to the SoC, not board specific. Primary core is fixed when u-boot still runs in board_f. Secondary cores are fixed by reading a variable set by u-boot. Signed-off-by: York Sun <yorksun@freescale.com> CC: Mark Rutland <mark.rutland@arm.com>
* armv8/fsl-lsch3: Fix platform clock calculationYork Sun2015-04-23-4/+3
| | | | | | | Platform clock is half of platform PLL. There is an additional divisor in place. Clean up code copied from powerpc. Signed-off-by: York Sun <yorksun@freescale.com>
* armv8/ls2085a: Update common header filePrabhakar Kushwaha2015-04-23-109/+222
| | | | | | | | | | | | | | | | | | | | | | | | | | | | ls2085a_common.h contains hard-coded information for NOR/NAND flash, I2C, DDR, etc. These are platform specific. Move them out of common header file and placed into respective board header files. Move TEXTBASE to 1MB offset to fit NOR flash with up to 1MB sector size. Enable command auto complete. Update prompt symbol. Set fdt_high to 0xa0000000 because Linux requires that the fdt be 8-byte aligned and below 512 MiB. Besides ensuring compliance with the 512 MiB limit, this avoids problems with the dtb being misaligned within the FIT image. Change the MC FW, MC DPL and Debug server NOR addresses in compliance with the NOR flash layouts for 128MB flash. Add PCIe macros. Enable "loadb" command. Disable debug server. Enable workaround for erratum A008511. Stop reset on panic for postmortem debugging. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
* armv8/fsl-lsch3: Implement workaround for erratum A008585York Sun2015-04-23-0/+12
| | | | | | | Generic Timer may contain an erroneous value. The workaround is to read it twice until getting the same value. Signed-off-by: York Sun <yorksun@freescale.com>
* drivers/net/e1000.c: Cleanup whitespaceMinghuan Lian2015-04-23-4/+4
| | | | | | | | | The patch removes unnecessary whitespace to fix checkpatch's warning: unnecessary whitespace before a quoted newline Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <yorksun@freescale.com>
* cmd_mem: Store last address/size/etc as ulongScott Wood2015-04-23-3/+3
| | | | | | | | Otherwise the high 32 bits get truncated on 64-bit U-boot. Signed-off-by: Scott Wood <scottwood@freescale.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <yorksun@freescale.com>
* driver/ddr/fsl: Add workaround for DDR erratum A008511York Sun2015-04-23-1/+97
| | | | | | | | This erratum only applies to general purpose DDR controllers in LS2. It shouldn't be applied to DP-DDR controller. Check DDRC versoin number before applying workaround. Signed-off-by: York Sun <yorksun@freescale.com>
* driver/ddr/fsl: Add built-in memory test for DDR4 driverYork Sun2015-04-23-0/+76
| | | | | | | | | Add built-in memory test to catch errors after DDR is initialized, before any other transactions. To enable this test, define CONFIG_FSL_DDR_BIST. An environmental variable "ddr_bist" is checked before starting test. It takes a while (several seconds) depending on system memory size. Signed-off-by: York Sun <yorksun@freescale.com>
* driver/ddr/fsl: Fix driver to support empty first slotYork Sun2015-04-23-28/+56
| | | | | | | | CS0 was not allowed to be empty by u-boot driver in the past to simplify the driver. This may be inconvenient for some debugging. This patch lifts the restrictions. Controller interleaving still requires CS0 populated. Signed-off-by: York Sun <yorksun@freescale.com>
* drivers/ddr/fsl: Update DDR driver for DDR4York Sun2015-04-23-13/+89
| | | | | | | | | | Add/update registers for DDR4, including DQ mappings. Allow raw timing method used for all controllers. Update mode_9 register to 0x500 for improved stability. Check DDR controller version number individually in case a SoC has multiple DDR controllers of different versions. Increase read-write turnaround for DDR4 high speeds. Signed-off-by: York Sun <yorksun@freescale.com>
* driver/i2c/mxc: Enable I2C bus 3 and 4York Sun2015-04-23-3/+45
| | | | | | | | | Some SoCs have more than two I2C busses. Instead of adding ifdef to the driver, macros are put into board header file where CONFIG_SYS_I2C_MXC is defined. Signed-off-by: York Sun <yorksun@freescale.com> CC: Heiko Schocher <hs@denx.de>
* nand/fsl_ifc: Increase eccstat[] for IFC 2.0Scott Wood2015-04-23-2/+9
| | | | | | | | IFC 2.0 doubled the SRAM size, which means double the number of ECCSTAT registers. Fix the resulting array overflow. Signed-off-by: Scott Wood <scottwood@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* driver/fsl_ifc: Add support to finalize CS1, CS3 address bindingPrabhakar Kushwaha2015-04-23-0/+9
| | | | | | | | | For fsl-lsch3, IFC is binded with address within 32-bit at fist. After u-boot relocates to DDR, CS1, CS3 can be binded to higher address to support large space. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
* board/ls2085_common: Increase malloc lengthPrabhakar Kushwaha2015-04-23-1/+1
| | | | | | | Increase malloc length for more than 2M. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* driver/ldpaa_eth: Add LDPAA Ethernet driverPrabhakar Kushwaha2015-04-23-3/+879
| | | | | | | | | | | | | | | LDPAA Ethernet driver is a freescale's new ethernet driver based on Layerscape architecture. Every ethernet driver controls on DPNI object. Where all DPNIs share one common DPBP and DPIO object to support Rx and Tx flows. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> CC: Cristian Sovaiala <cristian.sovaiala@freescale.com> CC: Bogdan Hamciuc <bogdan.hamciuc@freescale.com> CC: J. German Rivera <German.Rivera@freescale.com> [York Sun: s/NetReceive/net_process_received_packet] Reviewed-by: York Sun <yorksun@freescale.com>
* driver/fsl-mc: Add support of MC FlibsPrabhakar Kushwaha2015-04-21-211/+4967
| | | | | | | | | | | | | | | | | | | | | | Freescale's Layerscape Management Complex (MC) provide support various objects like DPRC, DPNI, DPBP and DPIO. Where: DPRC: Place holdes for other MC objectes like DPNI, DPBP, DPIO DPBP: Management of buffer pool DPIO: Used for used to QBMan portal DPNI: Represents standard network interface These objects are used for DPAA ethernet drivers. Signed-off-by: J. German Rivera <German.Rivera@freescale.com> Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com> Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com> Signed-off-by: Geoff Thorpe <Geoff.Thorpe@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Cristian Sovaiala <cristian.sovaiala@freescale.com> Signed-off-by: pankaj chauhan <pankaj.chauhan@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* fsl-ch3/README: Add description for NOR flash layout (firmware images)Bhupesh Sharma2015-04-21-0/+25
| | | | | | | | This patch adds description for NOR flash layout (firmware images) in the README file for LS2085A platforms. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* armv8/fsl-lsch3: Add Freescale Debug Server driverBhupesh Sharma2015-04-21-7/+338
| | | | | | | | | | | | | The Debug Server driver is responsible for loading the Debug server FW on the Service Processor (Cortex-A5 core) on LS2085A like SoCs and then polling for the successful initialization of the same. TOP MEM HIDE is adjusted to ensure the space required by Debug Server FW is accounted for. MC uses the DDR area which is calculated as: MC DDR region start = Top of DDR - area reserved by Debug Server FW Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* QE/DeepSleep: add QE deepsleep support for armZhao Qiang2015-04-21-0/+6
| | | | | | | | Muram will power off during deepsleep, and the microcode of qe in muram will be lost, it should be reload when resume. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* QE/DeepSleep: add QE deepsleep support for mpc85xxZhao Qiang2015-04-21-4/+108
| | | | | | | | Muram will power off during deepsleep, and the microcode of qe in muram will be lost, it should be reload when resume. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* drivers:usb: Check if USB Erratum A005697 is applicable on BSC913xNikhil Badola2015-04-21-0/+27
| | | | | | | | | Check if USB Erratum A005697 is applicable on BSC913x and add corresponding property in the device tree via device tree fixup which is used by linux driver Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* pci/layerscape: fix link and class issues to support ls2085aMinghuan Lian2015-04-21-14/+33
| | | | | | | | | | | | | | 1. LS2085a provides PCIE_LUT_DBG register rather than PCIE_LDBG to show the link status, so the patch fixes it. 2. Increase the delay time to make sure that link training has finished. 3. Return invalid value when accessing multi-function device 4. For LS2085a DBI_RO_WR_EN bit is cleared as default, so we must set this bit before change DBI register value. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* pci/layerscape: remove unnecessary pcie_layerscape.hMinghuan Lian2015-04-21-22/+6
| | | | | | | | | | The patch uses the common function name ft_pci_setup to replace ft_pcie_setup, then removes unnecessary pcie_layerscape.h because all the functions have been declared in common.h. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <yorksun@freescale.com>
* drivers:usb:fsl: Add affected SOCs for USB Erratum A007792Nikhil Badola2015-04-21-1/+6
| | | | | | | | | | Add following affected SOCs and their personalities for USB Erratum A007792 : T1040 Rev 1.1 T1024 Rev 1.0 Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* drivers:usb: Add device-tree fixup to identify socs having dual phyNikhil Badola2015-04-21-1/+38
| | | | | | | | | | Identify soc(s) having dual phy so as to add "utmi_dual" as phy_mode for all these socs. This is required for supporting deel-sleep feature in linux for usb driver Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* Add bootscript support to esbc_validate.gaurav rana2015-04-21-0/+150
| | | | | | | | | | | | | | | | | | | | | | | | 1. Default environment will be used for secure boot flow which can't be edited or saved. 2. Command for secure boot is predefined in the default environment which will run on autoboot (and autoboot is the only option allowed in case of secure boot) and it looks like this: #define CONFIG_SECBOOT \ "setenv bs_hdraddr 0xe8e00000;" \ "esbc_validate $bs_hdraddr;" \ "source $img_addr;" \ "esbc_halt;" #endif 3. Boot Script can contain esbc_validate commands and bootm command. Uboot source command used in default secure boot command will run the bootscript. 4. Command esbc_halt added to ensure either bootm executes after validation of images or core should just spin. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* ls102xa: ddr4: Use LPUART as console output to verify DCU driverAlison Wang2015-04-21-0/+4
| | | | | | | | | On QDS board with DDR4 DIMM, LPUART is used as console output to verify DCU driver. This patch adds ls1021aqds_ddr4_nor_lpuart_defconfig for this support. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* ls1021atwr: add hwconfig setting to do pin muxYao Yuan2015-04-21-0/+78
| | | | | | | | | Freescale LS1021ATWR share some pins. Hwconfig option is used to allows users to choose the pin functions. Signed-off-by: Yuan Yao <yao.yuan@freescale.com> [York Sun: revised commit message] Reviewed-by: York Sun <yorksun@freescale.com>
* arm/ls102xa:Add support of conditional workaround implementation as per SoC verAlison Wang2015-04-21-26/+72
| | | | | | | | For LS102xA, some workarounds are only used in VER1.0, so silicon version detection are added for QDS and TWR boards. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* serial: pl01x: fix PL010 regressionLinus Walleij2015-04-21-2/+11
| | | | | | | | | | | | | | | | | | | | commit aed2fbef5e9a0ab5a7cd01e742039a962f0b24ef "dm: serial: Tidy up the pl01x driver" caused a regression on (real hardware) PL010 by omitting to update the line control register when switching baudrate. Fix this by inlining the missing write to the baud control register. Also renaming the set_line_control() function to pl011_set_line_control() since this function is clearly PL011-specific, and it won't suffice to call that to set up line control. Tested on the Integrator/AP hardware. Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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