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| * | | | | | sparc: leon3: Added memory controller initialization using new AMBA PnP ↵Daniel Hellstrom2015-11-13-43/+688
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | routines. Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
| * | | | | | sparc: Kconfig: Move the CMD_AMBAPP command to KconfigFrancois Retief2015-11-13-17/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add an initr function in the board_r.c file for the AMBA Plug&Play command. Add a Kconfig entry for the ambapp command and remove all CONFIG_CMD_AMBAPP defines from the board configuration headers. Add a Kconfig entry to display the AMBA Plug&Play information on startup. This option is off by default. Remove relevent define from board configuration headers. Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>
| * | | | | | sparc: leon3: Reimplemented AMBA Plug&Play scanning routines.Daniel Hellstrom2015-11-13-731/+2070
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
| * | | | | | sparc: Update startup code to take PIC mode into accountFrancois Retief2015-11-13-38/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>
| * | | | | | sparc: Update GRSIM board with memory settings for TSIM evalFrancois Retief2015-11-13-12/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the GRSIM board with the memory settings for the evaluation version of TSIM. This free version of TSIM is used for testing. Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>
| * | | | | | sparc: Update LEON serial drivers to use readl/writel macrosFrancois Retief2015-11-13-158/+157
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the LEON2/3 serial driver to make use of the readl and writel macros as well as the WATCHDOG_RESET() macro. Add readl/writel and friends to the asm/io.h file. Introduce the gd->arch.uart variable to store register address. Lastly, remove baudrate scaler macro variables from board config. It is now calculated in the serial driver using the global data variable. Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>
| * | | | | | sparc: Add -mcpu= compiler flags for LEON2/LEON3Francois Retief2015-11-13-4/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>
| * | | | | | sparc: Update the maintainer for SPARC architectureFrancois Retief2015-11-13-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>
| * | | | | | sparc: Fix broken files during license changesFrancois Retief2015-11-13-130/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes broken search and replaced license changes in files cpu/leon3/start.S and include/asm/winmacro.h from commit 1a4596601fd395f3afb8f82f3f840c5e00bdd57a Signed-off-by: Francois Retief <fgretief@spaceteq.co.za> Series-to: u-boot Series-cc: Tom Rini <trini@konsulko.com> Series-version: 2 Cover-letter: sparc: Updates to SPARC architecture in preperation for generic board This patch series is a backlog of preparation work for upcomming generic board changes. I first want to get these reviewed and submitted to mainline before sending out more patches. END
* | | | | | | Merge branch 'master' of git://git.denx.de/u-boot-x86Tom Rini2015-11-13-381/+229
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| * | | | | | | x86: Remove CONFIG_SYS_EARLY_PCI_INITBin Meng2015-11-13-7/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_SYS_EARLY_PCI_INIT is not needed any more since with driver model, PCI enumeration is automatically triggered. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | | | | | | x86: Remove legacy pci codesBin Meng2015-11-13-71/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that we have converted all x86 boards to use driver model pci, remove these legacy pci codes. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | | | | | | x86: crownbay: Remove unused PCI region address macrosBin Meng2015-11-13-12/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These are leftover when converted to use driver model pci. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | | | | | | x86: qemu: Convert to use driver model ethBin Meng2015-11-13-15/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move to driver model for ETH (e1000) on QEMU. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | | | | | | x86: qemu: Convert to use driver model usbBin Meng2015-11-13-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move to driver model for USB on QEMU. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | | | | | | x86: qemu: Convert to use driver model pciBin Meng2015-11-13-62/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move to driver model for pci on QEMU. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | | | | | | x86: qemu: Move chipset-specific codes from pci.c to qemu.cBin Meng2015-11-13-72/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move chipset-specific codes such as PAM init, PCIe ECAM and MP table from pci.c to qemu.c, to prepare for DM PCI conversion. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | | | | | | x86: qemu: Remove call to vgabios executionBin Meng2015-11-13-18/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The call to pci_run_vga_bios() is not needed as this is handled in the vesa_fb driver. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | | | | | | x86: Move timer_init() call a bit earlierBin Meng2015-11-13-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently timer_init() is called in board_r.c which is quite late. Some vgabios execution requires we set up the i8254 timer correctly, but video initialization comes before timer_init(). Move the call to board_f.c. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | | | | | | x86: queensbay: Really disable IGDBin Meng2015-11-13-10/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to Atom E6xx datasheet, setting VGA Disable (bit17) of Graphics Controller register (offset 0x50) prevents IGD (D2:F0) from reporting itself as a VGA display controller class in the PCI configuration space, and should also prevent it from responding to VGA legacy memory range and I/O addresses. However test result shows that with just VGA Disable bit set and a PCIe graphics card connected to one of the PCIe controllers on the E6xx, accessing the VGA legacy space still causes system hang. After a number of attempts, it turns out besides VGA Disable bit, the SDVO (D3:F0) device should be disabled to make it work. To simplify, use the Function Disable register (offset 0xc4) to disable both IGD (D2:F0) and SDVO (D3:F0) devices. Now these two devices will be completely disabled (invisible in the PCI configuration space) unless a system reset is performed. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | | | | | | x86: Move CONFIG_8259_PIC and CONFIG_8254_TIMER to KconfigBin Meng2015-11-13-2/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Kconfig options for 8259 and 8254. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | | | | | | x86: Rename pcat_ to i8254 and i8259 accordinglyBin Meng2015-11-13-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename pcat_timer.c to i8254.c and pcat_interrupts.c to i8259.c, to match their header file names (i8254.h and i8259.h). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | | | | | | x86: Initialize i8254 timer counter 1Bin Meng2015-11-13-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Initialize counter 1, used to refresh request signal. This is required for legacy purpose as some codes like vgabios utilizes counter 1 to provide delay functionality. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | | | | | | x86: Fix cosmetic issues in the i8254 and i8259 codesBin Meng2015-11-13-53/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This cleans up i8254 and i8259 codes to fix several cosmetic issues, like coding convention and some comments improvement. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | | | | | | x86: Remove dead codes wrapped by PARANOID_IRQ_TRIGGERSBin Meng2015-11-13-16/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PARANOID_IRQ_TRIGGERS is not referenced anywhere in U-Boot. Remove these dead codes wrapped by it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | | | | | | x86: Rename CONFIG_SYS_NUM_IRQS to SYS_NUM_IRQSBin Meng2015-11-13-13/+10
| |/ / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_SYS_NUM_IRQS is actually not something we can configure, but an architecture defined number of ISA IRQs. Move it from x86-common.h to asm/interrupt.h and rename it to SYS_NUM_IRQS. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | | | | | sf: Fix NULL pointer exception for flashes without lock methodsBin Meng2015-11-13-7/+13
|/ / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit c3c016c "sf: Add SPI NOR protection mechanism" introduced flash_lock()/flash_unlock()/flash_is_locked() methods for SPI flash, but not every flash driver supplies these. We should test these methods against NULL before actually calling them. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* | | | | | board_init: Change the logic to setup malloc_baseFabio Estevam2015-11-12-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Prior to commit 5ba534d247d418 ("arm: Switch 32-bit ARM to using generic global_data setup") we used to have assembly code that configured the malloc_base address. Since this commit we use the board_init_f_mem() function in C to setup malloc_base address. In board_init_f_mem() there was a deliberate choice to support only early malloc() or full malloc() in SPL, but not both. Adapt this logic to allow both to be used, one after the other, in SPL. This issue has been observed in a Congatec board, where we need to retrieve the manufacturing information from the SPI NOR (the SPI API calls malloc) prior to configuring the DRAM. In this case as malloc_base was not configured we always see malloc to fail. With this change we are able to use malloc in SPL prior to DRAM gets initialized. Also update the CONFIG_SYS_SPL_MALLOC_START entry in the README file. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | | | | Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2015-11-12-669/+1353
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| * | | | | | ARM: tegra: note that p2371-2180 is Jetson TX1Stephen Warren2015-11-12-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | p2371-2180 is the engineering board name for the Jetson TX1 developer kit. Update Kconfig description and help text to make this obvious to everyone. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | | | | Tegra: T210: Add QSPI driverTom Warren2015-11-12-0/+425
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is the normal Tegra SPI driver modified to work with the QSPI controller in Tegra210. It does not do 2x/4x transfers or any other QSPI protocol. Signed-off-by: Yen Lin <yelin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * | | | | | ARM: tegra: rename GPU functionsAlexandre Courbot2015-11-12-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename GPU functions to less generic names to avoid potential name collisions. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | | | | ARM: tegra: simplify GPU setupAlexandre Courbot2015-11-12-29/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable the GPU node in the system-wide ft_system_setup() hook instead of the board-specific ft_board_hook(). This allows us to enable GPU per SoC generation instead of per-board as we did initially. Reported-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | | | | ARM: tegra: remove vpr_configured() functionAlexandre Courbot2015-11-12-12/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no justification for this function, especially in exported form. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | | | | ARM: tegra: error check Tegra210 XUSB padctl waitsStephen Warren2015-11-12-5/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add code to detect timeouts when waiting for HW events such as PLL lock done. Any errors are logged and trigger an error return code. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | | | | ARM: tegra: add lane tables to Tegra210 XUSB padctlStephen Warren2015-11-12-6/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the tables defining which pads and mux options exist in the Tegra210 XUSB padctl hardware. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | | | | ARM: tegra: switch Tegra210 to common XUSB padctlStephen Warren2015-11-12-158/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change simply deletes code from the Tegra210 XUSB padctl driver that is already present in the common XUSB padctl code. Since all the arrays in tegra210_socdata are empty, this update may leave the Tegra210 XUSB padctl driver non-functional at run-time. However, (a) this driver is not used yet so no regression can be observed and (b) the next commit will immediately fix this up. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | | | | ARM: tegra: parameterize common XUSB codeStephen Warren2015-11-12-82/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are some differences between the Tegra124 and Tegra210 XUSB padctl code. So far, the common XUSB padctl code only supports Tegra124. Add some parameters etc. so that it can work for both chips. This also allows moving Tegra124's process_nodes() into the common file; something that would have requires edits during the move if done in the previous commit. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | | | | ARM: tegra: create common XUSB padctl driver fileStephen Warren2015-11-12-341/+414
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A fair amount of the XUSB padctl driver will be common between Tegra124 and Tegra210. To avoid cut/paste between the two chips, create a new file that will contain the common code, and convert the Tegra124 code to use it. This change doesn't move every last piece of code that can/will be shared, but rather concentrates on moving code that can be moved with zero changes, so there are no other diffs mixed in. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | | | | ARM: tegra: clean up XUSB padctl error() callsStephen Warren2015-11-12-19/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This file defines pr_fmt(), so the individual error() calls don't need to include the prefix in their format strings. Doing so results in duplicate text in any error messages. Remove the duplication. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | | | | ARM: tegra: rename dummy XUSB padctl implementationStephen Warren2015-11-12-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A future patch will soon move some of the XUSB padctl code into a common file in arch/arm/mach-tegra. Rename the existing dummy XUSB padctl file to avoid conflicting with that, or being confusing. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | | | | ARM: tegra: enable PCI support of p2371-2180Stephen Warren2015-11-12-0/+90
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | p2371-2180 has two PCI ports; a regular x4 slot and a x1 M.2 slot. This patch adds the relevant DT to enable the PCI controller and configure the XUSB padctl pin muxing, and code to turn on the PCI power and enable PCI features in U-Boot. I have only tested the x4 slot. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | | | | ARM: tegra: add PCI to Tegra210 SoC DTStephen Warren2015-11-12-0/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra210's PCI controller is largely identical to Tegra124, and hence shares the same binding. However, it has a unique compatible value due to the existence of at least one new HW bug that would prevent any driver for a previous HW version from operating correctly. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | | | | pci: tegra: add/enable support for Tegra210Stephen Warren2015-11-12-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This needs a separate compatible value from Tegra124 since the new HW version has bugs that would prevent a driver for previous HW versions from operating at all. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | | | | pci: tegra: call tegra_pcie_board_init() earlierStephen Warren2015-11-12-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The board PCI setup code may control regulators that are required simply to bring up the PCI controller itself (or PLLs, IOs, ... it uses). Move the call to this function earlier so that all board-provided resources are ready early enough for everything to work. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | | | | pci: tegra: implement PCA enable workaroundStephen Warren2015-11-12-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra210's PCIe controller has a bug that requires the PCA (performance counter) feature to be enabled. If this isn't done, accesses to device configuration space will hang the chip for tens of seconds. Implement the workaround. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | | | | pci: tegra: use #address-/size-cells from DTStephen Warren2015-11-12-3/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The number of cells used by each entry in the DT ranges property is determined by the #address-cells/#size-cells properties. Fix the code to respect this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | | | | pci: tegra: clip RAM size to 32-bitsStephen Warren2015-11-12-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra peripherals can generally access a 32-bit physical address space, and I believe this applies to PCIe. Clip the PCI region that refers to DRAM so it fits into 32-bits to avoid issues. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | | | | ARM: tegra210: implement PLLE init procedure from TRMStephen Warren2015-11-12-47/+132
| | |_|_|_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement the procedure that the TRM mandates to initialize PLLREFE and PLLE. This makes the PLL actually lock. Note that this section of the TRM is being cleaned up to remove some confusion. The set of register accesses in this patch should be final, although the step numbers/descriptions might still change. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | | | | am43xx_evm: Add DFU support for qspi flashVignesh R2015-11-12-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support to update firmware on qspi flash present on am437x-sk-evm and am43xx-epos-evm via DFU. On device: => setenv dfu_alt_info ${dfu_alt_info_qspi} => dfu 0 sf 0:0 On host: $ sudo dfu-util -l $ sudo dfu-util -D u-boot.bin -a u-boot.bin Signed-off-by: Vignesh R <vigneshr@ti.com>
generated by cgit v1.1 at 2024-10-26 00:32:11 +0000