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* armv8/fsl-layerscape: fdt: fixup LS1043A rev1 MSI nodeWenbin Song2017-01-18-0/+157
| | | | | | | | | | The default MSI node in kernel tree is for LS1043A rev1.0 silicon, if rev1.1 silicon used, need to fixup the MSI node to match it. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8/ls1043a: fixup GIC offset for ls1043a rev1Wenbin Song2017-01-18-6/+150
| | | | | | | | | | | | | | | | | | | | | | | The LS1043A rev1.1 silicon supports two types of GIC offset: 4K alignment and 64K alignment. The bit SCFG_GIC400_ALIGN[GIC_ADDR_BIT] is used to choose which offset will be used. The LS1043A rev1.0 silicon only supports the CIG offset with 4K alignment. If GIC_ADDR_BIT bit is set, 4K alignment is used, or else 64K alignment is used. 64K alignment is the default setting. Overriding the weak smp_kick_all_cpus, the new impletment is able to detect GIC offset. The default GIC offset in kernel device tree is using 4K alignment, it need to be fixed if 64K alignment is detected. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: fsl-lsch3: enable snoopable sata read and writeTang Yuantian2017-01-18-0/+2
| | | | | | | | | By default the SATA IP on the ls208Xa SoCs does not generating coherent/snoopable transactions. This patch enable it in the sata axicc register. Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* ls1046ardb: Add support power initializationHou Zhiqiang2017-01-18-0/+41
| | | | | | | | | Add the chip power supply voltage initialization on LS1046ARDB. Add function power_init_board(), and it will initialize the PMIC and call the chip power initialization function. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8/fsl_lsch2: Add chip power supply voltage setupHou Zhiqiang2017-01-18-0/+373
| | | | | | | | | | | | | | | Set up chip power supply voltage according to voltage ID. The fuse status register provides the values from on-chip voltage ID fuses programmed at the factory. These values define the voltage requirements for the chip. Main operations: 1. Set up the core voltage 2. Set up the SERDES voltage and reset SERDES lanes 3. Enable/disable DDR controller support 0.9V if needed Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* ls1046ardb: cpld: add API for selecting core voltHou Zhiqiang2017-01-18-0/+10
| | | | | Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* pmic: pmic_mc34vr500: Add APIs to set/get SWx voltHou Zhiqiang2017-01-18-0/+105
| | | | | | Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: York Sun <york.sun@nxp.com>
* pmic: pmic_mc34vr500: Add a driver for the mc34vr500 pmicHou Zhiqiang2017-01-18-0/+206
| | | | | | | | | This patch adds a simple pmic driver for the mc34vr500 pmic which is used in conjunction with the fsl T1 and LS1 series SoC. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: fsl-layerscape: Fix SECURE_BOOT configYork Sun2017-01-18-1/+4
| | | | | | | | | | | Without a prompt in Kconfig, SECURE_BOOT cannot be selected by defconfig. The option was dropped unintentionally when defconfig files were cleaned up. Three targets were impacted ls1043ardb_SECURE_BOOT, ls2080ardb_SECURE_BOOT, ls2080aqds_SECURE_BOOT. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* LS2080A: Add validation of MC & DPC images.Udit Agarwal2017-01-18-3/+48
| | | | | | | | | Add secure boot validation of MC, DPC images using esbc_validate command. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* SECURE_BOOT: Update bootscript and its hdr addressesUdit Agarwal2017-01-18-6/+6
| | | | | | | | | Update bootscript and its hdr addresses for Layerscape Chasis 3 based platforms instead of individual SoCs. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* configs: ls1012a: enable driver model for eSDHCYangbo Lu2017-01-18-0/+6
| | | | | | | Enable driver model for eSDHC on ls1012a rdb and qds boards. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: ls1012a: add eSDHC nodesYangbo Lu2017-01-18-0/+16
| | | | | | | This patch is to add eSDHC nodes for ls1012a. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* mmc: fsl_esdhc: add 'fsl, esdhc' into of_match tableYangbo Lu2017-01-18-0/+1
| | | | | | | | This patch is to add 'fsl,esdhc' into of_match table to support driver model for QorIQ eSDHC. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* mmc: fsl_esdhc: make GPIO support optionalYangbo Lu2017-01-18-2/+8
| | | | | | | | | | | | | There would be compiling error as below when enable driver model for esdhc. undefined reference to `dm_gpio_get_value' undefined reference to `gpio_request_by_name_nodev' This patch is to make GPIO support optional with CONFIG_DM_GPIO. Because all boards of QorIQ platform don't need it and they just check register for CD/WP status, only some boards of i.MX platform require this. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8/fsl-lsch3: consolidate the clock system initializationHou Zhiqiang2017-01-18-8/+23
| | | | | | | | This patch binds the sys_info->freq_systembus to Platform PLL, and implements the IPs' clock function individually. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8/fsl-lsch2: refactor the clock system initializationHou Zhiqiang2017-01-18-29/+136
| | | | | | | | | | | | | | | | | | | Up to now, there are 3 kind of SoCs under Layerscape Chassis 2, like LS1043A, LS1046A and LS1012A. But the clocks tree has a lot of differences, for instance, the IP modules have different dividers to derive its clock from Platform PLL. And the core cluster PLL and platform PLL maybe have different reference clocks, such as LS1012A. Another problem is which clock/PLL should be described by sys_info->freq_systembus, it is confused in Layerscape Chissis 2. This patch is to bind the sys_info->freq_systembus to the Platform PLL, and handle the different divider of IP modules separately between different SoCs, and separate reference clocks of core cluster PLL and platform PLL. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* ARMv8/fsl-layerscape: Enable data coherency between cores in clusterHou Zhiqiang2017-01-18-0/+4
| | | | | Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: Enable CPUECTLR.SMPEN for coherencyMingkai Hu2017-01-18-0/+29
| | | | | | | | | | | | | | | | | | For A53, data coherency is enabled only when the CPUECTLR.SMPEN bit is set. The SMPEN bit should be set before enabling the data cache. If not enabled, the cache is not coherent with other cores and data corruption could occur. For A57/A72, SMPEN bit enables the processor to receive instruction cache and TLB maintenance operations broadcast from other processors in the cluster. This bit should be set before enabling the caches and MMU, or performing any cache and TLB maintenance operations. Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* arm: layerscape: Enable UUID & GPT partition for NXP's ARM SoCPrabhakar Kushwaha2017-01-18-0/+44
| | | | | | | | | | Enable UUID and GPT partition support for NXP's ARM based SoCs i.e. LS1012A, LS1021A, LS1043A, LS1046A and LS2080A. Also enable DOS partition for LS1012AFRDM boards. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: ls1012: Enable CONFIG_DM_USB in defconfigsTang Yuantian2017-01-18-0/+3
| | | | | | | | Enables driver model flag CONFIG_DM_USB for LS1012A platform in defconfigs. Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: ls1012: added usb nodes in dtsTang Yuantian2017-01-18-0/+15
| | | | | | | | | | The LS1012A processor has two integrated USB controllers. One is USB2.0 controller, the other is USB3.0 controller that allow direct connection to the USB ports with appropriate protection circuitry and power supplies. Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8/fsl_lsch2: Add the OCRAM initializationHou Zhiqiang2017-01-18-0/+40
| | | | | | | | | | | | | | Clear the content to zero and the ECC error bit of OCRAM1/2. The OCRAM must be initialized to ZERO by the unit of 8-Byte before accessing it, or else it will generate ECC error. And the IBR has accessed the OCRAM before this initialization, so the ECC error status bit should to be cleared. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Pratiyush Srivastava <pratiyush.srivastava@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* ARMv8/fsl-layerscape: Correct the OCRAM sizeHou Zhiqiang2017-01-18-7/+9
| | | | | | | | | The real size of OCRAM is 128KiB, so correct the size of OCRAM. And OCRAM reserved 2MiB space, then add a new macro to describe it, which is used for MMU setup. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* kconfig: move FSL_PCIE_COMPAT to platform KconfigHou Zhiqiang2017-01-18-12/+23
| | | | | | Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
* pci: layerscape: remove unnecessary legacy codeMinghuan Lian2017-01-18-716/+1
| | | | | | | | | | All Layerscape SoCs have supported new PCIe driver based on DM. The lagecy PCIe driver code is unused and can be removed. Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: ls2080a: Enable PCIe in defconfigsMinghuan Lian2017-01-18-39/+28
| | | | | | | | | The patch enables PCIe in ls2080a defconfigs and removes unused PCIe related macro defines. Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: ls1046a: Enable PCIe and E1000 in defconfigsMinghuan Lian2017-01-18-0/+48
| | | | | | | | The patch enables PCIe and E1000 in ls1046a related defconfigs. Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: ls1043a: Enable PCIe and E1000 in defconfigsMinghuan Lian2017-01-18-28/+66
| | | | | | | | | The patch enables PCIe and E1000 in ls1043a defconfigs and removes unused PCIe related macro defines. Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* arm: ls1012a: Enable PCIe and E1000 in defconfigsMinghuan Lian2017-01-18-34/+13
| | | | | | | | | The patch enables PCIe and E1000 in ls1012a defconfigs and removes unused PCIe related macro defines Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* arm: ls1021a: Enable PCIe in defconfigsMinghuan Lian2017-01-18-67/+72
| | | | | | | | | The patch enables PCIe in ls1021a defconfigs and removes unused PCIe related macro defines. Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* pci: layerscape: add pci driver based on DMMinghuan Lian2017-01-18-0/+754
| | | | | | | | | | | | | There are more than five kinds of Layerscape SoCs. unfortunately, PCIe controller of each SoC is a little bit different. In order to avoid too many macro definitions, the patch addes a new implementation of PCIe driver based on DM. PCIe dts node is used to describe the difference. Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
* pci: layerscape: move kernel DT fixup to a separate fileHou Zhiqiang2017-01-18-311/+343
| | | | | | | | | To make the layerscape pcie driver clear, move the kernel DT fixup code from pcie_layerscape.c to pcie_layerscape_fixup.c. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: ls2080a: add PCIe dts nodeMinghuan Lian2017-01-18-0/+60
| | | | | | Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: ls1046a: add PCIe dts nodeMinghuan Lian2017-01-18-0/+49
| | | | | | Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: ls1043a: add PCIe dts nodeMinghuan Lian2017-01-18-0/+46
| | | | | | Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* arm: ls1012a: add PCIe dts nodeMinghuan Lian2017-01-18-0/+15
| | | | | | Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* arm: ls1021a: add PCIe dts nodeMinghuan Lian2017-01-18-0/+31
| | | | | | Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* dm: pci: remove pci_bus_to_hose(0) callingMinghuan Lian2017-01-18-10/+7
| | | | | | | | | | | | | | There may be multiple PCIe controllers in a SoC. It is not correct that always calling pci_bus_to_hose(0) to get the first PCIe controller for the PCIe device connected other controllers. We just remove this calling because hose always point the correct PCIe controller. Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: York Sun <york.sun@nxp.com>
* dm: pci: return the real controller in pci_bus_to_hose()Minghuan Lian2017-01-18-1/+1
| | | | | | | | | | | | | for the legacy PCI driver, the function pci_bus_to_hose() returns the real PCIe controller. To keep consistency, this function is changed to return the PCIe controller pointer of the root bus instead of the current PCIe bus. Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: York Sun <york.sun@nxp.com>
* configs: ls1021a: enable DT and DM supportHou Zhiqiang2017-01-18-0/+12
| | | | | | | | Enable DT to support Driver Model. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8/layerscape: remove unnecessary function declaresMinghuan Lian2017-01-18-4/+0
| | | | | | | | | For the function alloc_stream_ids() append_mmu_masters() and fdt_fixup_smmu_pcie() there are no related definitions and they are never called. So the patch removes the unnecessary declares. Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: fsl-layerscape, ccn504: Set forced-order mode in RNI-6, RNI-20Priyanka Jain2017-01-18-0/+20
| | | | | | | | | | | | It is recommended to set forced-order mode in RNI-6, RNI-20 for performance optimization in LS2088A. Both LS2080A, LS2088A families has CONFIG_LS2080A define. As above update is required only for LS2088A, skip this for LS2080A SoC family. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* fsl/usb: enable usb feature for ls1046ardbjerry.huang@nxp.com2017-01-18-1/+13
| | | | | | | Enable usb feature for ls1046ardb Signed-off-by: Changming Huang <jerry.huang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* Prepare v2017.01Tom Rini2017-01-09-1/+1
| | | | Signed-off-by: Tom Rini <trini@konsulko.com>
* lib: gitignore *.elf and *.so generated by efi_loaderLadislav Michl2017-01-09-0/+2
| | | | Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
* scripts/config_whitelist.txt: ResyncTom Rini2017-01-08-125/+0
| | | | Signed-off-by: Tom Rini <trini@konsulko.com>
* mx6ullevk: Add missing MAINTAINERS for mx6ull_14x14_evk_plugin_defconfigJagan Teki2017-01-08-0/+1
| | | | | | | | | | | Add 'Peng Fan' as MAINTAINERS of configs/mx6ull_14x14_evk_plugin_defconfig which is missing in below commit "imx: mx6ull_14x14_evk: add plugin defconfig" (sha1: b90ebf49bb8f74afe68f696f59a0e24cc79f2031) Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jagan Teki <jagan@openedev.com>
* am335x: configs: Use ISW_ENTRY_ADDR to set SPL_TEXT_BASEAndrew F. Davis2017-01-08-2/+3
| | | | | | | | | | | | The SPL load address changes based on boot type in HS devices, ISW_ENTRY_ADDR is used to set this address for AM43xx based SoCs for similar reasons. Add this same logic for AM33xx devices. Also make the default value for ISW_ENTRY_ADDR correct for GP devices based on SoC, HS devices already pick the correct value in their defconfig. Signed-off-by: Andrew F. Davis <afd@ti.com>
* arm: mach-omap2: Fix secure file generationAndrew F. Davis2017-01-08-19/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | When TI_SECURE_DEV_PKG is not defined we warn that the file '*_HS' was not generated but generate an unsigned one anyway, first fix this warning to say that it was generated but not secured. When the user then exports TI_SECURE_DEV_PKG after getting this warning, and tries to re-build, 'make' will detect the build artifacts as unchanged and so assume they do not need to be re-generated. This causes it to fail to sign the files and it will pack unsigned files into the final image, even though TI_SECURE_DEV_PKG is now correctly defined and working. Fix this by using FORCE on the targets causes them to be re-run even if the dependent files have not changed. This then causes another issue. We currently rename the signed dtb files to overwrite the non-signed ones. We do this so the 'mkimage' tool gives the packaged dtb sections the correct name. If we do not rename the files then SPL will not find them during boot. Fix this by renaming the dtb files by appending _HS to the end of the filename, after the ".dtb", this causes them to still be named correctly in the FIT blob. Signed-off-by: Andrew F. Davis <afd@ti.com>
generated by cgit v1.1 at 2024-11-20 09:57:41 +0000