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| * | mpc83xx: enable the SATA interface on mpc8315 rdb and mpc837x rdb boardsKim Phillips2008-03-28-0/+46
| | | | | | | | | | | | Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * | mpc83xx: enable the SATA interface on mpc837xemds boardDave Liu2008-03-28-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | Enable the first two SATA interfaces on MPC837xEMDS board, The two SATA ports are on LYNX1. (SATA0/1 on J4/5) Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * | mpc83xx: initialize serdes for MPC837xEMDS boardsDave Liu2008-03-28-0/+38
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is stolen from Anton Vorontsov's patch for mpc837xerdb boards. The reference clk and xcorevdd voltage of serdes1/2 is same between mpc837xemds and mpc837xerdb. 8377E: LYNX1- 2 SATA LYNX2- 2 PCIE 8378E: LYNX1- 2 SGMII LYNX2- 2 PCIE 8379E: LYNX1- 2 SATA LYNX2- 2 SATA Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-cfi-flashWolfgang Denk2008-04-07-10/+57
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| * | MTD/CFI: flash_read64 is defined a weak function (for SPARC)Daniel Hellstrom2008-03-29-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SPARC has implemented __raw_readq, it reads 64-bit from any 32-bit address. SPARC CPUs implement flash_read64 which calls __raw_readq. For current SPARC architectures (LEON2 and LEON3) each read from the FLASH must lead to a cache miss. This is because FLASH can not be set non-cacheable since program code resides there, and alternatively disabling cache is poor from performance view, or doing a cache flush between each read is even poorer. Forcing a cache miss on a SPARC is done by a special instruction "lda" - load alternative space, the alternative space number (ASI) is processor implementation spcific and can be found by including <asm/processor.h>. Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
| * | MTD/CFI: Add support for 16bit legacy AMD flashTor Krill2008-03-28-9/+54
| |/ | | | | | | | | | | | | | | Add entry for 512Kx16 AMD flash to jedec_table. Read out 16bit device id if chipwidth is 16bit. Fixed coding style after Stefans feedback Signed-off-by: Tor Krill <tor@excito.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-ppc4xxWolfgang Denk2008-04-07-412/+1174
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| * ppc4xx: Fix 4xx enet driver to support 460GT EMAC2+3Stefan Roese2008-04-03-3/+13
| | | | | | | | | | | | | | | | This patch fixes a problem with the RGMII setup of the 460GT. The 460GT has 2 RGMII instances and we need to configure the 2nd RGMII instance for the EMAC2+3 channels. Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Canyonlands: Init SATA/PCIe port correctlyStefan Roese2008-04-02-12/+34
| | | | | | | | | | | | | | | | | | Canyonlands (460EX) shares the first PCIe interface with the SoC SATA interface. This usage can be configured with the jumper J6. This patch correctly configures the SATA/PCIe PHY for SATA usage when this jumper is installed. Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Add CFG_MEM_TOP_HIDE to Denali SPD-based SDRAM setupLarry Johnson2008-03-31-13/+14
| | | | | | | | Signed-off-by: Larry Johnson <lrj@acm.org>
| * ppc4xx: Small whitespace fix of esd patchesStefan Roese2008-03-31-7/+7
| | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Cleanup PMC440 board supportMatthias Fuchs2008-03-31-148/+132
| | | | | | | | Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
| * ppc4xx: Add ptm configuration variables for PMC440Matthias Fuchs2008-03-31-32/+54
| | | | | | | | | | | | | | | | | | Add support for the ptm1la, ptm1ms, ptm2la and ptm2ms environment variables. Cleanup pci_target_init. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
| * ppc4xx: Minor updates for DU440 boardsMatthias Fuchs2008-03-31-12/+10
| | | | | | | | Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
| * ppc4xx: Canyonlands: Print SATA/PCIe configuration and board revisionStefan Roese2008-03-28-3/+40
| | | | | | | | | | | | | | | | | | Canyonlands (460EX) shares the first PCIe interface with the SoC SATA interface. This usage can be configured with the jumper J6. This patch displays the current configuration upon bootup and changes the PCIe init loop, to only initialize the availabel PCIe slots. Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc: Small change to CFG_MEM_TOP_HIDE descriptionStefan Roese2008-03-28-2/+2
| | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Enable ECC on LWMON5Stefan Roese2008-03-27-75/+21
| | | | | | | | | | | | | | | | | | | | | | Since all ECC related problems seem to be resolved on LWMON5, this patch now enables ECC support. We have to write the ECC bytes by zeroing and flushing in smaller steps, since the whole 256MByte takes too long for the external watchdog. Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Updates to Korat-specific codeLarry Johnson2008-03-27-75/+463
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch contains updates for changes for the Korat PPC440EPx board. These changes include: (1) Support for "permanent" and "upgradable" copies of U-Boot, as described in the new "doc/README.korat" file; (2) a new memory map for the registers in the board's CPLD; (3) a revised format for manufacturer's data in serial EEPROM; and (4) changes to track updates to U-Boot for the Sequoia board. Signed-off-by: Larry Johnson <lrj@acm.org>
| * ppc4xx: PPC405EP Set EMAC noise filter bitsMarkus Brunner2008-03-27-1/+1
| | | | | | | | | | | | | | | | | | This bug was introduced with commit aee747f19b460a0e9da20ff21e90fdaac1cec359 which enabled CFG_4xx_GPIO_TABLE for PPC405 and unintentionally disabled the setting of the emac noise filter bits for PPC405EP when CFG_4xx_GPIO_TABLE is set. Signed-off-by: Markus Brunner <super.firetwister@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Reconfigure PLL for 667MHz processor for PPC440EPxMike Nuss2008-03-27-1/+99
| | | | | | | | | | | | | | | | | | | | | | | | On PPC440EPx without a bootstrap I2C EEPROM, the PLL can be reconfigured after startup to change the speed of the clocks. This patch adds the option CFG_PLL_RECONFIG. If this option is set to 667, the CPU initialization code will reconfigure the PLL to run the system with a CPU frequency of 667MHz and PLB frequency of 166MHz, without the need for an external EEPROM. Signed-off-by: Mike Nuss <mike@terascala.com> Acked-by: Stefan Roese <sr@denx.de>
| * ppc: Set CFG_MEM_TOP_HIDE to 0 if not already definedStefan Roese2008-03-27-0/+4
| | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Add fdt support to Prodrive alprStefan Roese2008-03-27-2/+36
| | | | | | | | | | | | | | | | Since this board will probably be ported to arch/powerpc in the near future, we add device tree support now. This way we are "ready" for arch/powerpc from now on. Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Enable cache support on the ALPR boardPieter Voorthuijsen2008-03-27-0/+10
| | | | | | | | Signed-off-by: Pieter Voorthuijsen <pv@prodrive.nl>
| * ppc: Add CFG_MEM_TOP_HIDE option to hide memory area that doesn't get "touched"Stefan Roese2008-03-27-1/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If CFG_MEM_TOP_HIDE is defined in the board config header, this specified memory area will get subtracted from the top (end) of ram and won't get "touched" at all by U-Boot. By fixing up gd->ram_size the Linux kernel should gets passed the now "corrected" memory size and won't touch it either. This should work for arch/ppc and arch/powerpc. Only Linux board ports in arch/powerpc with bootwrapper support, which recalculate the memory size from the SDRAM controller setup, will have to get fixed in Linux additionally. This patch enables this config option on some PPC440EPx boards as a workaround for the CHIP 11 errata. Here the description from the AMCC documentation: CHIP_11: End of memory range area restricted access. Category: 3 Overview: The 440EPx DDR controller does not acknowledge any transaction which is determined to be crossing over the end-of-memory-range boundary, even if the starting address is within valid memory space. Any such transaction from any PLB4 master will result in a PLB time-out on PLB4 bus. Impact: In case of such misaligned bursts, PLB4 masters will not retrieve any data at all, just the available data up to the end of memory, especially the 440 CPU. For example, if a CPU instruction required an operand located in memory within the last 7 words of memory, the DCU master would burst read 8 words to update the data cache and cross over the end-of-memory-range boundary. Such a DCU read would not be answered by the DDR controller, resulting in a PLB4 time-out and ultimately in a Machine Check interrupt. The data would be inaccessible to the CPU. Workaround: Forbid any application to access the last 256 bytes of DDR memory. For example, make your operating system believe that the last 256 bytes of DDR memory are absent. AMCC has a patch that does this, available for Linux. This patch sets CFG_MEM_TOP_HIDE for the following 440EPx boards: lwmon5, korat, sequoia The other remaining 440EPx board were intentionally not included since it is not clear to me, if they use the end of ram for some other purpose. This is unclear, since these boards have CONFIG_PRAM defined and even comments like this: PMC440.h: /* esd expects pram at end of physical memory. * So no logbuffer at the moment. */ It is strongly recommended to not use the last 256 bytes on those boards too. Patches from the board maintainers are welcome. Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Fix Canyonlands linker script (remove bogus ASSERT)Stefan Roese2008-03-27-2/+0
| | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Correctly pass phyiscal FLASH base address into dtbStefan Roese2008-03-27-1/+1
| | | | | | | | | | | | | | | | | | The routine ft_board_setup() configures the EBC NOR mappings for the Linux physmap_of driver. Since on 460EX/GT we remap the FLASH from 0x4.fc00.0000 to 0x4.cc00.0000 because of the max. 16MByte boot-CS problem, we need to pass the corrected address here too. Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Fix compilation warning in 4xx_enet.cStefan Roese2008-03-27-7/+6
| | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Add AMCC Glacier 406GT eval board supportStefan Roese2008-03-27-25/+195
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the AMCC Glacier 460GT eval board. The main difference to the Canyonlands board are listed here: - 4 ethernet ports instead of 2 - no SATA port - no USB port Currently EMAC2+3 are not working. This will be fixed in a later release. Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Mask 'vec' with 0x1f in uic_interrupt() for bit set/clearStefan Roese2008-03-27-3/+4
| | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | Fix host tool build breakage, take twoBartlomiej Sieka2008-03-27-7/+4
| | | | | | | | | | | | | | Revert commit 87c8431f and fix build breakage so that the build continues to work on FC systems. Signed-off-by: Bartlomiej Sieka <tur@semihalf.com>
* | new-image: Fix host tool build breakageHaavard Skinnemoen2008-03-27-0/+4
|/ | | | Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
* Merge branch 'master' of git+ssh://10.10.0.7/home/wd/git/u-boot/masterWolfgang Denk2008-03-27-7/+13
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| * Fix out of tree building issueAnatolij Gustschin2008-03-27-7/+13
| | | | | | | | | | | | | | Currently U-Boot building in some external directory doesn't work. This patch tries to fix the problem. Signed-off-by: Anatolij Gustschin <agust@denx.de>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xxWolfgang Denk2008-03-27-141/+794
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| * | 85xx: Add cpu_mp_lmb_reserve helper to reserve boot pageKumar Gala2008-03-26-0/+15
| | | | | | | | | | | | | | | | | | | | | Provide a board_lmb_reserve helper function to ensure we reserve the page of memory we are using for the boot page translation code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | 85xx: Update multicore boot mechanism to ePAPR v0.81 specKumar Gala2008-03-26-74/+122
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following changes are needed to be inline with ePAPR v0.81: * r4, r5 and now always set to 0 on boot release * r7 is used to pass the size of the initial map area (IMA) * EPAPR_MAGIC value changed for book-e processors * changes in the spin table layout * spin table supports a 64-bit physical release address Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | FSL: Clean up board/freescale/common/MakefileJon Loeliger2008-03-26-42/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Each file that can be built here now follows some CONFIG_ option so that they are appropriately built or not, as needed. And CONFIG_ defines were added to various board config files to make sure that happens. The other board/freescale/*/Makefiles no longer need to reach up and over into ../common to build their individually needed files any more. Boards that are CDS specific were renamed with cds_ prefix. Signed-off-by: Jon Loeliger <jdl@freescale.com>
| * | 85xx: Fix merge duplicationKumar Gala2008-03-26-49/+0
| | | | | | | | | | | | | | | | | | ft_fixup_cpu() got duplicated in some merge snafu. Remove the duplicate. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | 85xx: Expand CCSR space with more DDR controller registers.James Yang2008-03-26-4/+21
| | | | | | | | | | | | | | | | | | Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | 85xx: Speed up get_ddr_freq() and get_bus_freq()James Yang2008-03-26-18/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | get_ddr_freq() and get_bus_freq() used get_sys_info() each time they were called. However, get_sys_info() recalculates extraneous information when called each time. Have get_ddr_freq() and get_bus_freq() return memoized values from global_data instead. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | 85xx: Show DDR memory data rate in addition to the memory clock frequency.James Yang2008-03-26-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | Show the DDR memory data rate in addition to the memory clock frequency. For DDR/DDR2 memories the memory data rate is 2x the memory clock. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | 85xx: get_tbclk() speed up and rounding fixJames Yang2008-03-26-5/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Speed up get_tbclk() by referencing pre-computed bus clock frequency value from global data instead of sys_info_t. Fix rounding of result to nearest; previously it was rounding upwards. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | Update SVR numbers to expand supportAndy Fleming2008-03-26-50/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | FSL has taken to using SVR[16:23] as an SOC sub-version field. This is used to distinguish certain variants within an SOC family. To account for this, we add the SVR_SOC_VER() macro, and update the SVR_* constants to reflect the larger value. We also add SVR numbers for all of the current variants. Finally, to make things neater, rather than use an enormous switch statement to print out the CPU type, we create and array of SVR/name pairs (using a macro), and print out the CPU name that matches the SVR SOC version. Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | Add the Freescale PCI device IDsAndy Fleming2008-03-26-0/+23
| | | | | | | | | | | | Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | 85xx: Added support for multicore boot mechanismKumar Gala2008-03-26-0/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added the cpu command that provides a generic mechanism to get status, reset, and release secondary cores in multicore processors. Added support for using the ePAPR defined spin-table mechanism on 85xx. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | 85xx: Added support for multicore boot mechanismKumar Gala2008-03-26-0/+513
| | | | | | | | | | | | | | | | | | | | | | | | | | | Added the cpu command that provides a generic mechanism to get status, reset, and release secondary cores in multicore processors. Added support for using the ePAPR defined spin-table mechanism on 85xx. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | 85xx: Add the concept of CFG_CCSRBAR_PHYSKumar Gala2008-03-26-19/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | When we go to 36-bit physical addresses we need to keep the concept of the physical CCSRBAR address seperate from the virtual one. For the majority of boards CFG_CCSBAR_PHYS == CFG_CCSRBAR Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | | Merge branch 'master' of git://www.denx.de/git/u-boot-usbWolfgang Denk2008-03-27-4/+4
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| * | USB, Storage: fix a bug introduced in commitMarkus Klotzbuecher2008-03-26-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | f6b44e0e4d18fe507833a0f76d24a9aa72c123f1 that will cause usb_stor_info to only print only information on one storage device, but not for multiple. Signed-off-by: Markus Klotzbuecher <mk@denx.de>
| * | Fix compilation error in cmd_usb.cAnatolij Gustschin2008-03-26-1/+1
| |/ | | | | | | | | | | | | | | | | This patch fixes compilation error cmd_usb.c: In function 'do_usb': cmd_usb.c:552: error: void value not ignored as it ought to be Signed-off-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Markus Klotzbuecher <mk@denx.de>
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