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* Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2014-12-11-221/+1904
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| * ARM: HYP/non-sec: Fix the ARCH Timer frequency setting for sun7iXiubo Li2014-12-11-1/+1
| | | | | | | | | | | | | | | | | | Earlier commit 73a1cb27 mistakenly used CONFIG_SYS_TIMER_CLK_FREQ. It should be CONFIG_TIMER_CLK_FREQ. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> [York Sun: This is the difference between two patch versions] Reviewed-by: York Sun <yorksun@freescale.com>
| * kconfig: ls102xa: Change the prompt messagesAlison Wang2014-12-11-2/+2
| | | | | | | | | | | | | | | | | | | | As NOR/NAND/SD boot are all supported on LS1021AQDS/TWR boards, the prompt message "Support ls1021aqds_nor" in Kconfig is not clear. This patch changes it to "Support ls1021aqds". Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * driver/mtd: Fix IFC compilation warningsJaiprakash Singh2014-12-11-1/+1
| | | | | | | | | | | | | | 'eccstat' array elements might be used uninitialized Signed-off-by: Jaiprakash Singh <b44839@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * ARM: ls102xa: Setting device's stream id for SMMUs.Xiubo Li2014-12-11-0/+83
| | | | | | | | | | | | | | | | | | | | | | | | LS1 has 4 SMMUs for address translation of the masters. All the SMMUs' stream IDs are 8-bit. The address translation depends on the stream ID of the incoming transaction. Each master has unique stream ID assigned to it and is configurable through SCFG registers. The stream ID for the masters is identical and share the same register field of STREAM ID registers. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * ARM: ls102xa: allow all the peripheral access permission as R/W.Xiubo Li2014-12-11-0/+335
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Central Security Unit (CSU) allows secure world software to change the default access control policies of peripherals/bus slaves, determining which bus masters may access them. This allows peripherals to be separated into distinct security domains. Combined with SMMU configuration of the system masters privileges, these features provide protection against indirect unauthorized access to data. For now we configure all the peripheral access permissions as R/W. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * ls102xa: changing a few targets' configurations.Xiubo Li2014-12-11-0/+19
| | | | | | | | | | | | | | | | | | Enable hypervisors utilizing the ARMv7 virtualization extension on the LS1021A-QDS/TWR boards with the A7 core tile, we add the required configuration variable. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * ls1021a: adding a secondary core boot address and kick functionsXiubo Li2014-12-11-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define the board specific smp_set_cpu_boot_addr() function to set the start address for secondary cores in the LS1021A specific manner. Define the board specific smp_kick_all_cpus() functioin to boot a secondary core. Here the BRR contains control bits for enabling boot for each core. On exiting HRESET or PORESET, the RCW BOOT_HO field optionally allows for logical core 0 to be released for booting or to remain in boot holdoff. All other cores remain in boot holdoff until their corresponding bit is set. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * ARM: HYP/non-sec: Fix the ARCH Timer frequency setting.Xiubo Li2014-12-11-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | For some SoCs, the system clock frequency may not equal to the ARCH Timer's frequency. This patch uses the CONFIG_TIMER_CLK_FREQ instead of CONFIG_SYS_CLK_FREQ, then the system clock macro and arch timer macor could be set separately and without interfering each other. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * ARM: HYP/non-sec: add the pen address BE mode support.Xiubo Li2014-12-11-0/+3
| | | | | | | | | | | | | | | | | | | | For some SoCs, the pen address register maybe in BE mode and the CPUs are in LE mode. This patch adds BE mode support for smp pen address. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * fsl/sleep: updated the deep sleep framework for QorIQ platformsTang Yuantian2014-12-11-56/+322
| | | | | | | | | | | | | | | | | | | | | | | | | | With the introducing of generic board and ARM-based cores, current deep sleep framework doesn't work anymore. This patch will convert the current framework to adapt this change. Basically it does: 1. Converts all the Freescale's DDR driver to support deep sleep. 2. Added basic framework support for ARM-based and PPC-based cores separately. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * drivers: usb: fsl: Check USB Erratum A007792 applicabilityNikhil Badola2014-12-11-0/+32
| | | | | | | | | | | | | | | | Check USB Erratum A007792 applicability. If applicable, add corresponding property in the device tree via device tree fixup Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * drivers: usb: fsl: Add USB device-tree errata frameworkNikhil Badola2014-12-11-0/+64
| | | | | | | | | | | | | | | | | | | | | | Add a new framework for fsl usb erratum handling to standardize erratum checking only inside Uboot. Information to kernel is passed via a boolean property corresponding to erratum, hence eliminating need for code duplication inside kernel Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * drivers: usb: Make usb device-tree fixup code architecture independentNikhil Badola2014-12-11-104/+113
| | | | | | | | | | | | | | | | | | move usb device tree fixup code from "arch/powerpc/" to "drivers/usb/" so that it works independent of architecture it is running on Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * ls1021aqds: add hwconfig setting to do pin muxYao Yuan2014-12-11-3/+70
| | | | | | | | | | | | | | | | | | | | | | The Freescale LS1021AQDS share some pins, so Add the hwconfig option that allows the user to choose which the function he wants. The main pin mux IP is: eSDHC, SAI, IIC2, RGMII, CAN, SAI. Signed-off-by: Yuan Yao <yao.yuan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * arm: ls102xa: Add NAND boot support for LS1021AQDS boardAlison Wang2014-12-11-0/+117
| | | | | | | | | | | | | | | | | | | | | | This patch adds NAND boot support for LS1021AQDS board. SPL framework is used. PBL initialize the internal RAM and copy SPL to it, then SPL initialize DDR using SPD and copy u-boot from NAND flash to DDR, finally SPL transfer control to u-boot. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * arm: ls102xa: Add QSPI boot support for LS1021AQDS/TWR boardAlison Wang2014-12-11-0/+93
| | | | | | | | | | | | | | | | | | This patch adds QSPI boot support for LS1021AQDS/TWR board. The QSPI boot image need to be programmed into the QSPI flash first. Then the booting will start from QSPI memory space. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * arm: ls102xa: Fix SD/NAND/QSPI boot defination error for QE supportAlison Wang2014-12-11-2/+4
| | | | | | | | | | | | | | | | The SD/NAND/QSPI boot definations are wrong for QE support, this patch is to fix this error. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * arm: ls1021a: Add CONFIG_DOS_PARTITION and CONFIG_CMD_FAT supportAlison Wang2014-12-11-0/+6
| | | | | | | | | | | | | | | | This patch will fix the bug that the partitions on the SD card could not be accessed and add the support for the FAT fs. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * arm: ls102xa: Add SD boot support for LS1021ATWR boardAlison Wang2014-12-11-0/+95
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds SD boot support for LS1021ATWR board. SPL framework is used. PBL initialize the internal RAM and copy SPL to it, then SPL initialize DDR using SPD and copy u-boot from SD card to DDR, finally SPL transfer control to u-boot. Signed-off-by: Chen Lu <chen.lu@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: Jason Jin <jason.jin@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * arm: ls102xa: Add SD boot support for LS1021AQDS boardAlison Wang2014-12-11-1/+173
| | | | | | | | | | | | | | | | | | | | | | This patch adds SD boot support for LS1021AQDS board. SPL framework is used. PBL initialize the internal RAM and copy SPL to it, then SPL initialize DDR using SPD and copy u-boot from SD card to DDR, finally SPL transfer control to u-boot. Signed-off-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: Jason Jin <jason.jin@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * ls102xa: qixis: Add CONFIG_QIXIS_I2C_ACCESS macroAlison Wang2014-12-11-0/+7
| | | | | | | | | | | | | | | | | | | | | | Through adding CONFIG_QIXIS_I2C_ACCESS macro, QIXIS_READ(reg)/QIXIS_WRITE(reg, value) can be used for both i2c and ifc access to QIXIS FPGA. This is more convenient for coding. Signed-off-by: Jason Jin <jason.jin@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * kconfig: ls1021a: add SUPPORT_SPLAlison Wang2014-12-11-0/+2
| | | | | | | | | | | | | | | | Add SUPPORT_SPL feature for SD and NAND boot on LS1021AQDS and LS1021ATWR. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * arm: spl: Add I2C linker list in generic .ldsAlison Wang2014-12-11-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | On LS1, DDR is initialized by reading SPD through I2C interface in SPL code. For I2C, ll_entry_count() is called, and it returns the number of elements of a linker-generated array placed into subsection of .u_boot_list section specified by _list argument. So add I2C linker list in the generic .lds to fix the issue about using I2C in SPL. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * spl: Use u-boot.img instead of u-boot.binAlison Wang2014-12-11-1/+7
| | | | | | | | | | | | | | | | | | | | In SD boot, the magic number of u-boot image will be checked. For LS102xA, u-boot.bin doesn't have the magic number. So use u-boot.img which includes the magic number instead of u-boot.bin when producing u-boot-with-spl-pbl.bin. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * ls102xa: pblimage: Add pblimage tool support for LS102xAAlison Wang2014-12-11-36/+77
| | | | | | | | | | | | | | | | | | | | | | | | | | | | For LS102xA, the size of spl/u-boot-spl.bin is variable. This patch adds the support to deal with the variable u-boot size in pblimage tool. It will be padded to 64 byte boundary. Use pblimage_check_params() to add the specific operations for ARM, such as PBI CRC and END command and the calculation of pbl_cmd_initaddr. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * ls1021aqds: set the default I2C channel before DDR initChenhui Zhao2014-12-11-13/+19
| | | | | | | | | | | | | | | | | | When resuming from deep sleep, the I2C channel may not be in the default channel. So, switch to the default channel before accessing DDR SPD. Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * arm: ls102xa: Update PCIe dts node statusMinghuan Lian2014-12-11-0/+93
| | | | | | | | | | | | | | | | The patch changes PCIe dts node status to 'disabled' if the corresponding controller is disabled according to serdes protocol. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * arm: ls102xa: clear EPU registers for deep sleepchenhui zhao2014-12-11-0/+143
| | | | | | | | | | | | | | | | After wakeup from deep sleep, Clear EPU registers as early as possible to prevent from possible issue. It's also safe to clear at normal boot. Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * arm: ls102xa: fixed a bus frequency setting errorTang Yuantian2014-12-11-1/+1
| | | | | | | | | | | | | | | | The bus frequency in SOC node should be clock frequency of platform. That is not true if it is devided by 2. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2014-12-10-45/+66
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| * | arm: vf610: improve evaluation of reset sourceStefan Agner2014-12-01-10/+19
| | | | | | | | | | | | | | | | | | | | | Improve the evaluation of the reset source. Bit description according to latest reference manual rev. 7. Signed-off-by: Stefan Agner <stefan@agner.ch>
| * | mx6sabre_common: Use the default CONFIG_SYS_PBSIZEFabio Estevam2014-12-01-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Entering the maximum number of characters defined by CONFIG_SYS_CBSIZE into the console and hitting enter afterwards, causes a hang in the system because CONFIG_SYS_PBSIZE is not capable of storing the characters of the error message: "Unknown command '' - try 'help'". Use the default CONFIG_SYS_PBSIZE definition from config_fallbacks.h to solve this problem. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | config_fallbacks: Add a default entry for CONFIG_SYS_PBSIZEFabio Estevam2014-12-01-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Entering the maximum number of characters defined by CONFIG_SYS_CBSIZE into the console and hitting enter afterwards, causes a hang in the system because CONFIG_SYS_PBSIZE is not capable of storing the characters of the error message: "Unknown command '' - try 'help'". Provide a default size for CONFIG_SYS_PBSIZE so that it can store the error message and allows the error message to be printed correctly with no hang. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | tbs2910: fix lost characters on serial inputSoeren Moch2014-12-01-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | With enabled console_mux for serial input and usb keyboard sometimes characters get lost when typing too fast at the serial input (pasting strings in serial console window). Fix this by using INT_QUEUE for polling the usb keyboard. Signed-off-by: Soeren Moch <smoch@web.de>
| * | arm: mx6: Change defines ENET_xxMHz to ENET_xxMHZ (no CamelCase)Stefan Roese2014-12-01-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As checkpatch complaines about these camel-case defines, lets change them to only use upper-case characters. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Heiko Schocher <hs@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Jon Nettleton <jon.nettleton@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | sata: fix reset_sata for dwc_ahsataSoeren Moch2014-12-01-6/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - fix crash when sata device is not initialized - remove disable_sata_clock() since it is not clear which clock for which device should be disabled here - call disable_sata_clock() for mx6 in preboot_os instead Signed-off-by: Soeren Moch <smoch@web.de> Acked-by: Nikita Kiryanov <nikita@compulab.co.il> Tested-by: Nikita Kiryanov <nikita@compulab.co.il>
| * | tbs2910: fix KconfigSoeren Moch2014-12-01-8/+1
| | | | | | | | | | | | | | | | | | fix Kconfig for tbs2910 board to prevent crash on relocation Signed-off-by: Soeren Moch <smoch@web.de>
| * | mxc_ocotp: Do not disable the OCOTP clock after every accessFabio Estevam2014-12-01-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Leave the OCOTP turned on, so that we subsequent access do not fail. After enabling the thermal driver on a mx6sxsabresd board: U-Boot 2015.01-rc1-18267-g99d4189-dirty (Nov 24 2014 - 12:59:01) CPU: Freescale i.MX6SX rev1.0 at 792 MHz CPU: Temperature 48 C Reset cause: POR Board: MX6SX SABRE SDB I2C: ready DRAM: 1 GiB PMIC: PFUZE100 ID=0x10 MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2 00:01.0 - 16c3:abcd - Bridge device 01:00.0 - 8086:08b1 - Network controller In: serial Out: serial Err: serial Net: (hang) As the thermal driver accesses the ocotp registers, its clock will be disabled afterwards. Then when the MAC address is read (also from ocotp registers) it will cause a hang. Do not disable the ocotp clock to prevent this problem. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
| * | mx6sxsabresd: Add thermal supportFabio Estevam2014-12-01-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add thermal support so that the temperature of the chip can be displayed on boot: U-Boot 2015.01-rc1-18268-g1366c05-dirty (Nov 25 2014 - 13:02:42) CPU: Freescale i.MX6SX rev1.0 at 792 MHz CPU: Temperature 50 C Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | thermal: imx_thermal: Do not display calibration dataFabio Estevam2014-12-01-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Printing the calibration data on every boot does not provide really useful information: U-Boot 2015.01-rc1-18266-ge7eb277 (Nov 24 2014 - 11:29:51) CPU: Freescale i.MX6Q rev1.2 at 792 MHz CPU: Thermal calibration data: 0x5d85067d CPU: Temperature 33 C Reset cause: POR Board: MX6-SabreSD Do not display the calibration data in order to have a cleaner boot log. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | mxs_ocotp: clear the error flag before initiating write operationHector Palacios2014-12-01-0/+2
| | | | | | | | | | | | | | | | | | | | | A previous operation may have set the error flag, which must be cleared before a new write operation can be issued. Signed-off-by: Hector Palacios <hector.palacios@digi.com>
| * | mxs_ocotp: check for errors from the OTP controller after writingHector Palacios2014-12-01-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | The write operation may fail when trying to write to a locked area. In this case the ERROR bit is set in the CTRL register. Check for that condition and return an error. Signed-off-by: Hector Palacios <hector.palacios@digi.com> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | mxs_ocotp: prevent error path from returning successHector Palacios2014-12-01-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The code may goto 'fail' upon error with 'ret' variable set to an error code, but this variable was being overwritten by a final preparation function to restore the HCLK, so success was (in general) returned even after an error was hit previously. With this change, the function may now return success even if the final preparation function fails, but it's probably enough to print a message because (if successful) the real programming of the fuses has already completed. Signed-off-by: Hector Palacios <hector.palacios@digi.com>
| * | imx: mx53loco: Add raw initrd supportGuillaume GARDET2014-12-01-0/+1
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr> Cc: Stefano Babic <sbabic@denx.de> Cc: Jason Liu <r64343@freescale.com> Acked-by: Jason Liu <r64343@freescale.com>
* | | Merge branch 'rmobile' of git://git.denx.de/u-boot-shTom Rini2014-12-10-103/+391
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| * | | arm: rmobile: alt: Add support MMC and MMC commandNobuhiro Iwamatsu2014-12-10-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Alt board has been connected to eMMC of 8GB to MMC port. This enables MMC port and MMC command. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | | arm: rmobile: lager: Add support MMC and MMC commandNobuhiro Iwamatsu2014-12-10-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Lager board has been connected to eMMC of 8GB to MMC1 port. This enables MMC1 port and MMC command. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | | arm: rmobile: rcar: Add support ext2 and ext4 file systemNobuhiro Iwamatsu2014-12-10-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Board with R-Car SoC has USB and MMC. They might use the EXT2 or EXT4 file system. This adds support ext2 and ext4 file system Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | | arm: rmobile: Add mmc.h for sh_mmcif of rmobileNobuhiro Iwamatsu2014-12-10-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | R-Mobile and R-Car ARM SoCs use sh_mmcif as MMC host driver. This adds arch-rmobile/mmc.h that defines mmcif_mmc_init(). Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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