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* armv8: ls1043a: load Fman ucode from SD/MMC under SD bootQianyu Gong2016-04-06-1/+9
| | | | | Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: ls1043a: load Fman ucode from NAND flash under NAND bootQianyu Gong2016-04-06-1/+5
| | | | | Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8/ls1043aqds: modify CONFIG_SYS_MAX_FLASH_BANKS to 1Wenbin Song2016-04-06-1/+1
| | | | | | | There is only one flash bank for ls1043aqds. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* arm: ls102xa: Fix order of CSU indexes in ns_access.hVincent Siles2016-04-06-3/+3
| | | | | | | | | This patch aims to fix the order of CSU slave index for the LS1021a board. Signed-off-by: Vincent Siles <vincent.siles@provenrun.com> Reviewed-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: LSCH2 early and final mmu needs matching NS attributeEd Swarthout2016-04-06-4/+8
| | | | | | | | | | When switching between the early and final mmu tables, the stack will get corrupted if the Non-Secure attribute is different. For ls1043a, this issue is currently masked because flush_dcache_all is called before the switch when CONFIG_SYS_DPAA_FMAN is defined. Signed-off-by: Ed Swarthout <Ed.Swarthout@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: ls1043aqds: make sure fixed-link property is big endianShaohui Xie2016-04-06-6/+6
| | | | | | | | | When setting fixed-link property to DTS, the values should be converted with using cpu_to_fdt32 so that to have correct value on little endian Soc. Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* drivers: net: vsc9953: Fix bug when PVID is shown for disabled ports onlyCodrin Ciubotariu2016-04-06-1/+1
| | | | | | Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <york.sun@nxp.com>
* drivers: net: vsc9953: Do not configure disabled portsCodrin Ciubotariu2016-04-06-4/+8
| | | | | | | | | | | | Some SerDes protocols might not enable all l2switch ports. In this case, these ports should not be configured to perform Rx/Tx operations. This also fixes an issue when flooded frames were also switched to disabled ports and frames start to accumulate, consuming memory and eventually causing head-of-line blocking for other frames. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <york.sun@nxp.com>
* fsl: esdhc: consolidate fsl_esdhc_cfg structurePeng Fan2016-04-06-5/+1
| | | | | | | | | | | | | | | We can use phys_addr_to for esdhc_base to discard the #ifdef. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: York Sun <york.sun@nxp.com> Cc: Yangbo Lu <yangbo.lu@nxp.com> Cc: Eric Nelson <eric@nelint.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
* fsl: esdhc: support driver modelPeng Fan2016-04-06-40/+213
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support Driver Model for fsl esdhc driver. 1. Introduce a new structure struct fsl_esdhc_priv 2. Refactor fsl_esdhc_initialize which is originally used by board code. - Introduce fsl_esdhc_init to be common usage for DM and non-DM - Introduce fsl_esdhc_cfg_to_priv to build the bridge for non-DM part. - The original API for board code is still there, but we use 'fsl_esdhc_cfg_to_priv' and 'fsl_esdhc_init' to serve it. 3. All the functions are changed to use 'struct fsl_esdhc_priv', except fsl_esdhc_initialize. 4. Since clk driver is not implemented, use mxc_get_clock to geth the clk and fill 'priv->sdhc_clk'. Has been tested on i.MX6UL 14X14 EVK board: " =>dm tree .... simple_bus [ + ] | `-- aips-bus@02100000 mmc [ + ] | |-- usdhc@02190000 mmc [ + ] | |-- usdhc@02194000 .... => mmc list FSL_SDHC: 0 (SD) FSL_SDHC: 1 (SD) " Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: York Sun <york.sun@nxp.com> Cc: Yangbo Lu <yangbo.lu@nxp.com> Cc: Hector Palacios <hector.palacios@digi.com> Cc: Eric Nelson <eric@nelint.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Simon Glass <sjg@chromium.org> Tested-By: Eric Nelson <eric@nelint.com> Reviewed-by: York Sun <york.sun@nxp.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-microblazeTom Rini2016-04-04-318/+1962
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| * ARM64: zynqmp: Enable EFI partition supportMichal Simek2016-04-04-0/+1
| | | | | | | | | | | | Enable EFI partition support for ZynqMP. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * net: zynq_gem: Add SGMII support for zynqMPSiva Durga Prasad Paladugu2016-04-04-2/+11
| | | | | | | | | | | | | | | | | | PCS auto negotaiation bit should be enabled along with SGMII autonegotation enabled in phy. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * net: phy: Add SGMII support for TI phySiva Durga Prasad Paladugu2016-04-04-1/+38
| | | | | | | | | | | | | | | | | | Add support of SGMII to TI phy dp838367 Enable the SGMII and PCS settings in phy control, CFG2 and BIST registers Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * net: zynq_gem: Return error incase of invalid phy addressSiva Durga Prasad Paladugu2016-04-04-3/+1
| | | | | | | | | | | | | | | | Return error from probe in case of invalid phy address. This fixes the issue of uboot crash if phy is not detected. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * ARM: zynq: Add uEnv.txt supportMichal Simek2016-04-04-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | preboot macro load the uEnv.txt from mmc 0 when bootmode is mmc. uenvcmd is executed after load of uEnv.txt if it is defined in the uEnv.txt env text file. The default importbootenv macro reads the uEnv.txt from mmc. Additional to this, usb_loadbootenv is added to support loading uEnv.txt from usb dev 0. Signed-off-by: Jason Wu <jason.wu.misc@gmail.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * ARM: zynq: Enable FLASH_BAR for microzed and zyboMichal Simek2016-04-04-0/+2
| | | | | | | | | | | | Enable FLASH_BAR for these targets to be in sync with all zynq boards. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * block: Add support for Ceva sataMichal Simek2016-04-04-1/+119
| | | | | | | | | | | | | | Initial Ceva Sata init code. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * ARM64: zynqmp: Simplify MAINTAINERS file to support more boardsMichal Simek2016-04-04-4/+3
| | | | | | | | | | | | Handle all Xilinx ZynqMP boards with one fragment. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * ARM64: zynqmp: Read RAM information from DTMichal Simek2016-04-04-8/+127
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Read information about memory from DT. This patch simplify life with synchronization between DT and board files. dram_init() only needs maximum RAM size below 4GB that's why please sort banks in memory node. dram_init_banksize() copies memory setup to bi_dram[]. This will avoid reading information from DT twice. Memory test start/end were changed to DDR location to let memtest still compiled. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * ARM64: Move HUSH enabling from board file to defconfigMichal Simek2016-04-04-1/+1
| | | | | | | | | | | | Simplify board config file. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * ARM64: zynqmp: Select SYS_CONFIG_NAME via KconfigMichal Simek2016-04-04-9/+7
| | | | | | | | | | | | | | | | | | This option enable adding new platform suport just by adding defconfig and DTS file which will target generic configuration for SoC. Make no sense to extend Kconfig just create a pointer between DTS and configuration file. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * ARM64: zynqmp: Enable FAT write and EXT4 write for USB tooMichal Simek2016-04-04-0/+3
| | | | | | | | | | | | Enabling writing files to FAT and EXT4 for USB. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * ARM64: zynqmp: Decrease boot delaySoren Brinkmann2016-04-04-1/+1
| | | | | | | | | | | | | | Synchronize it with zynq platform. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * net: axi_emac: Report phy-node error message permanentlyMichal Simek2016-04-04-1/+1
| | | | | | | | | | | | Do not use debug() when printing error message. Use printf instead. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * microblaze: Remove !OF_CONTROL code for timer and interruptMichal Simek2016-04-04-45/+1
| | | | | | | | | | | | OF_CONTROL is enabled by default that's why this is dead code. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * microblaze: Read information about timer/interrupts from DTMichal Simek2016-04-04-1/+63
| | | | | | | | | | | | | | Read information about timer and interrupts from DT. This is the first small step to move timer and intc to DM. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * ARM: zynq: Fix default ps7_init_gpl.c/h for ZYBOMichal Simek2016-04-04-244/+1342
| | | | | | | | | | | | | | | | | | There is incorrect setting for USB which didn't work with origin ps7_init_gpl.X files. Use default setting for Digilent Zybo projects with HDMI in PL. Signed-off-by: Michal Simek <monstr@monstr.eu> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * ARM: zynq: zybo: Enabling reading MAC address from EEPROMMichal Simek2016-04-04-0/+3
| | | | | | | | | | | | | | Zybo has on board I2C EEPROM which contains preprogrammed MAC address. Signed-off-by: Michal Simek <monstr@monstr.eu> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * net: gem: Allow to set the MAC from an EEPROMJoe Hershberger2016-04-04-0/+33
| | | | | | | | | | | | | | | | | | | | Provide board specific option how to read MAC address from ROM. Do it in generic way to be reusable by differnet boards. If this is not enough board specific functions can be created. Signed-off-by: Joe Hershberger <joe.hershberger@gmail.com> # driver part Signed-off-by: Michal Simek <monstr@monstr.eu> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * ARM: zynq: Enable option to overwrite default variablesMichal Simek2016-04-04-0/+2
| | | | | | | | | | | | Enable overwriting variables out of main config file. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * net: xilinx_axi: Clear Isolate bit if found during phy setupSiva Durga Prasad Paladugu2016-04-04-1/+19
| | | | | | | | | | | | | | | | | | | | In SGMII cases the isolate bit might set after DMA and ethernet resets and hence check and clear during setup_phy if it was set. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * net: xilinx_axi: Use interface type instead of zeroSiva Durga Prasad Paladugu2016-04-04-1/+1
| | | | | | | | | | | | | | | | | | Pass appropriate interface type to phy_connect instead of zero. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * zynq-common: Enable phy driver for Xilinx PCS/PMA coreSiva Durga Prasad Paladugu2016-04-04-0/+1
| | | | | | | | | | | | | | Add support of Xilinx PCS/PMA core phy for Zynq Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * net: zynq_gem: Add support for SGMII interfaceSiva Durga Prasad Paladugu2016-04-04-7/+19
| | | | | | | | | | | | | | | | Add support of SGMII interface for zynq GEM. Read xlnx,emio property from DT. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * phy: Add phy driver support for xilinx PCS/PMA coreSiva Durga Prasad Paladugu2016-04-04-0/+149
| | | | | | | | | | | | | | | | Add phy driver support for xilinx PCS/PMA core Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | Merge git://www.denx.de/git/u-boot-marvellTom Rini2016-04-04-9/+5473
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| * | arm: mvebu: Don't enable d-cache on A375Stefan Roese2016-04-04-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | Armada 375 still has some problems with d-cache enabled in the ethernet driver (mvpp2). So lets keep the d-cache disabled until this is solved. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
| * | arm: mvebu: Add basic support for Armada 375 eval board db-88f6720Stefan Roese2016-04-04-2/+1151
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds basic support for the Marvell A375 eval board. Tested are the following interfaces: - I2C - SPI - SPI NOR - Ethernet (mvpp2), port 0 & 1 Currently the A375 SerDes and DDR3 init code is not intergrated. So the SPL U-Boot is not fully functional. Right now, this A375 mainline U-Boot can only be used by chainloading it via the original Marvell U-Boot. This can be done via this command: => tftpboot 00800000 a375/u-boot-dtb.bin;go 00800000 Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
| * | arm: mvebu: Add basic support for the Marvell Armada 375 SoCStefan Roese2016-04-04-5/+92
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds basic support for the Armada 375. Please note that currently the SerDes and DDR3 init code for the A375 is not included / enabled. This will be done in a later, follow-up patch. Right now, this A375 mainline U-Boot can only be used by chainloading it via the original Marvell U-Boot. This can be done via this command: => tftpboot 00800000 a375/u-boot-dtb.bin;go 00800000 Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
| * | dt-bindings: Add include/dt-bindings/phy/phy.h from Linux v4.4Stefan Roese2016-04-04-0/+19
| | | | | | | | | | | | | | | | | | | | | This will be needed by the upcoming Marvell Armada 375 dts files. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
| * | net: mvpp2.c: Add Marvell mvpp2 network driver for Armada 375Stefan Roese2016-04-04-0/+4201
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the mvpp2 ethernet controller which is integrated in the Marvell Armada 375 SoC. This port is based on the Linux driver (v4.4), which has been stripped of the in U-Boot unused portions. Tested on the Marvell Armada 375 eval board db-88f6720. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Acked-by: Joe Hershberger <joe.hershberger@gmail.com>
| * | spi: kirkwood_spi.c: Add compatible match ID for Armada 375Stefan Roese2016-04-04-0/+1
| |/ | | | | | | | | | | | | | | This enables this driver for the Marvell Armada 375 SoC. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Reviwer-by: Jagan Teki <jteki@openedev.com>
* | common: cli: Fix typo CONFIG_CMDINE -> CONFIG_CMDLINEStefan Roese2016-04-04-1/+1
|/ | | | | | | | | | Patch f8bb6964 (Drop command-processing code when CONFIG_CMDLINE is disabled) introduced a small typo. This patch fixes it and unbreaks all boards again that don't have the Hush parser enabled. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com>
* net: phy: Realtek RTL8211B/C PHY ID fixKarsten Merker2016-04-02-1/+2
| | | | | | | | | | | | | | | | | | | | | | | The RTL8211B_driver structure in drivers/net/phy/realtek.c contains a wrong PHY ID (0x1cc910 instead of 0x1cc912) in the uid field. The lowest four bits of the PHY ID encode the chip revision (B+C/D/E/F) of the RTL8211 and the code originally applied a mask of 0xfffff0 to the PHY ID, so that matching the PHY ID to the appropriate driver code was only done on the chip type (RTL8211), but not on a specific revision. After introduction of support for the RTL8211E, which needed another startup function than the older chip revisions, commit 42205047674d7fc9e0aa747273fbc7dcfbac3183 changed the mask to 0xffffff to make the chip revision relevant for the match, but didn't provide the now-relevant lower bits of the uid field for the RTL8211B/C. Fix this by setting the full PHY ID in the RTL8211B_driver uid field. Fixes: 42205047674d ("net/phy: realtek: Fix the PHY ID mask to ensure the correct Realtek PHY is detected") Signed-off-by: Karsten Merker <merker@debian.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* MAINTAINERS: Update Scott Wood's email addressScott Wood2016-04-01-1/+1
| | | | | | | Freescale is now NXP. I still work there, but I won't be using their mail system for U-Boot development. Signed-off-by: Scott Wood <oss@buserror.net>
* sata: use block layer for sata commandEric Nelson2016-04-01-2/+4
| | | | | | | | Call blk_dread, blk_dwrite, blk_derase to ensure that the block cache is used if enabled and to remove build breakage when CONFIG_BLK is enabled. Signed-off-by: Eric Nelson <eric@nelint.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* mmc: use block layer in mmc commandEric Nelson2016-04-01-3/+4
| | | | | | | | Call blk_dread, blk_dwrite, blk_derase to ensure that the block cache is used if enabled and to remove build breakage when CONFIG_BLK is enabled. Signed-off-by: Eric Nelson <eric@nelint.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* drivers: block: add block device cacheEric Nelson2016-04-01-2/+402
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a block device cache to speed up repeated reads of block devices by various filesystems. This small amount of cache can dramatically speed up filesystem operations by skipping repeated reads of common areas of a block device (typically directory structures). This has shown to have some benefit on FAT filesystem operations of loading a kernel and RAM disk, but more dramatic benefits on ext4 filesystems when the kernel and/or RAM disk are spread across multiple extent header structures as described in commit fc0fc50. The cache is implemented through a minimal list (block_cache) maintained in most-recently-used order and count of the current number of entries (cache_count). It uses a maximum block count setting to prevent copies of large block reads and an upper bound on the number of cached areas. The maximum number of entries in the cache defaults to 32 and the maximum number of blocks per cache entry has a default of 2, which has shown to produce the best results on testing of ext4 and FAT filesystems. The 'blkcache' command (enabled through CONFIG_CMD_BLOCK_CACHE) allows changing these values and can be used to tune for a particular filesystem layout. Signed-off-by: Eric Nelson <eric@nelint.com>
* Add myself as Snapdragon and SPMI maintainerMateusz Kulikowski2016-04-01-0/+14
| | | | | | | | - Update MAINTAINERS - Update git-mailrc Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-11-02 02:21:36 +0000