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* powerpc: ppc4xx: dts: Bring in canyonlands device tree filesSimon Glass2015-02-12-0/+1484
| | | | | | | The canyonlands.h config file works with canyonlands, glacier and arches boards. Bring in the device tree files for these from Linux 3.17. Signed-off-by: Simon Glass <sjg@chromium.org>
* powerpc: ppc4xx: canyonlands: Move to generic boardSimon Glass2015-02-12-0/+4
| | | | | | Switch to generic board so that this board will not be broken/removed. Signed-off-by: Simon Glass <sjg@chromium.org>
* powerpc: ppc4xx: Add ramboot config for glacierSimon Glass2015-02-12-0/+93
| | | | | | | Add a new ramboot config for glacier so that it is possible to test U-Boot loaded over Ethernet instead of using JTAG. Signed-off-by: Simon Glass <sjg@chromium.org>
* powerpc: ppc4xx: Move CANYONLANDS/GLACIER/ARCHES to KconfigSimon Glass2015-02-12-3/+25
| | | | | | Move these options to Kconfig and remove them from the CONFIG files. Signed-off-by: Simon Glass <sjg@chromium.org>
* powerpc: ppc4xx: canyonlands: config: Tidy up CONFIGs and config.mkSimon Glass2015-02-12-23/+18
| | | | | | | | Many CONFIG options have an unnecessary value of 1. CONFIG_440 is set in the various board config files. Also simplify the CONFIG_440 check in config.mk Signed-off-by: Simon Glass <sjg@chromium.org>
* powerpc: Permit device tree control of U-Boot (CONFIG_OF_CONTROL)Simon Glass2015-02-12-0/+1
| | | | | | | Enable this in the Kconfig so that PowerPC boards can use device tree to configure U-Boot. Signed-off-by: Simon Glass <sjg@chromium.org>
* Introduce board_init_f_mem() to handle early memory layoutSimon Glass2015-02-12-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present on some architectures we set up the following before calling board_init_f(): - global_data - stack - early malloc memory Adding the code to support early malloc and global data setup to every arch's assembler start-up is a pain. Also this code is not actually architecture-specific. We can use common code for all architectures and with a bit of care we can write this code in C. Add a new function to deal with this. It should be called after memory is available, with a pointer to the top of the area that should be used before relocation. The function will set things up and return the lowest memory address that it allocated/used. That can then be set as the top of the stack. Note that on some archs this function will use the stack, so the stack pointer should be set to same value as is pased to board_init_f_mem(). A margin of 128 bytes will be left for this stack, so that it is not overwritten. This means that 64 bytes is wasted by this early call. This is not strictly necessary on several more modern archs, so we could remove this at the cost of some arch-dependent code. With this function there is no-longer any need for the assembler code to zero global_data or set up the early malloc pointers. Signed-off-by: Simon Glass <sjg@chromium.org>
* malloc_simple: Return NULL on malloc failure rather then calling panic()Hans de Goede2015-02-12-1/+1
| | | | | | | | | | | | | | | All callers of malloc should already do error checking, and may even be able to continue without the alloc succeeding. Moreover, common/malloc_simple.c is the only user of .rodata.str1.1 in common/built-in.o when building the SPL, triggering this gcc bug: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=54303 Causing .rodata to grow with e.g. 0xc21 bytes, nullifying all benefits of using malloc_simple in the first place. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Simon Glass <sjg@chromium.org>
* i2c: s3c24x0: reduce transmission status timeoutPrzemyslaw Marczak2015-02-12-2/+2
| | | | | | | | | | | | | | If no device is connected to I2C bus, the i2c probe command can take a lot of time for probe each address. This commit reduces the busy timeout to 10ms for standard and high speed modes. This doesn't break the transmission an also allow for properly probe the devices. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Changes v3: - new commit, after split the next one Tested-by: Simon Glass <sjg@chromium.org>
* gpio: omap: Pass correct argument to _get_gpio_direction()Axel Lin2015-02-12-1/+1
| | | | | | | Pass bank rather than bank->base to _get_gpio_direction(). Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Simon Glass <sjg@chromium.org>
* gpio: at91: Fix getting address of private dataAxel Lin2015-02-12-5/+5
| | | | | | | | Use dev_get_priv() rather than dev_get_platdata() to get correct address of private data. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Simon Glass <sjg@chromium.org>
* dm: Prevent "demo hello" and "demo status" segfaultsPeter Tyser2015-02-12-1/+3
| | | | | | | | | | | | | Segfaults can occur when a mandatory argument is not provided to "demo hello" and "demo status". Eg: => demo hello Segmentation fault (core dumped) Add a check to ensure all required arguments are provided. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Acked-by: Simon Glass <sjg@chromium.org>
* RSA depends on DMChris Kuethe2015-02-12-0/+1
| | | | | | Discovered while experimenting with signature checking on vexpress which doesn't typically use DM. Acked-by: Simon Glass <sjg@chromium.org>
* sunxi: configs/sunxi-common.h: Enable CONFIG_CMD_PARTHans de Goede2015-02-11-0/+3
| | | | | | | | | The recent changes to config_distro_bootcmd.h require CONFIG_CMD_PART to be defined, as the default bootcmd not uses the "part" command. This fixes sunxi boards not booting with v2015.04-rc1. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* Add linux/compiler-gcc5.h to fix builds with gcc5Hans de Goede2015-02-11-0/+65
| | | | | | | | | | | | Add linux/compiler-gcc5/h from the kernel sources at: commit 5631b8fba640a4ab2f8a954f63a603fa34eda96b Author: Steven Noonan <steven@uplinklabs.net> Date: Sat Oct 25 15:09:42 2014 -0700 compiler/gcc4+: Remove inaccurate comment about 'asm goto' miscompiles Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* Merge branch 'master' of git://git.denx.de/u-boot-x86Tom Rini2015-02-10-272/+11497
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| * x86: Use tab instead of space to indent in PCIE_ECAM_BASEBin Meng2015-02-06-1/+1
| | | | | | | | | | | | | | | | Space is used before 'default' in PCIE_ECAM_BASE in arch/x86/Kconfig so it looks misaligned. Replace the space with tab to indent. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * bootstage: Fix typos in the commentBin Meng2015-02-06-2/+2
| | | | | | | | | | | | | | There are two typos in the comment block in bootstage.h, fix them. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Add Intel Galileo instructions in README.x86Bin Meng2015-02-06-4/+20
| | | | | | | | | | | | | | Add some instructions about building U-Boot for Intel Galileo board. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Add SD/MMC support to quark/galileoBin Meng2015-02-06-0/+18
| | | | | | | | | | | | | | | | Intel Galileo board has a microSD slot which is routed from Quark SoC SDIO controller. Enable SD/MMC support so that we can use an SD card. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Add SPI support to quark/galileoBin Meng2015-02-06-1/+32
| | | | | | | | | | | | | | | | | | | | The Quark SoC contains a legacy SPI controller in the legacy bridge which is ICH7 compatible. Like Tunnel Creek and BayTrail, the BIOS control register offset in the ICH SPI driver is wrong for the Quark SoC too, unprotect_spi_flash() is added to enable the flash write. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: pci: Add pci ids for Quark SoCBin Meng2015-02-06-0/+4
| | | | | | | | | | | | | | Add pci ids for Intel Quark SoC. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: galileo: Add GPIO supportBin Meng2015-02-06-0/+14
| | | | | | | | | | | | | | | | | | | | Quark SoC has a legacy GPIO block in the legacy bridge (D0:F31), which is just the same one found in other x86 chipset. Since we programmed the GPIO register block base address, we should be able to enable the GPIO support on Intel Galileo board. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: quark: Initialize non-standard BARsBin Meng2015-02-06-0/+78
| | | | | | | | | | | | | | | | | | Quark SoC has some non-standard BARs (excluding PCI standard BARs) which need be initialized with suggested values. This includes GPIO, WDT, RCBA, PCIe ECAM and some ACPI register block base addresses. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: quark: Call MRC in dram_init()Bin Meng2015-02-06-2/+122
| | | | | | | | | | | | | | | | Now that we have added Quark MRC codes, call MRC in dram_init() so that DRAM can be initialized on a Quark based board. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * dt-bindings: Add Intel Quark MRC bindingsBin Meng2015-02-06-0/+83
| | | | | | | | | | | | | | Add standard dt-bindings macros to be used by Intel Quark MRC node. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * fdtdec: Add compatible id and string for Intel Quark MRCBin Meng2015-02-06-0/+2
| | | | | | | | | | | | | | | | Add COMPAT_INTEL_QRK_MRC and "intel,quark-mrc" so that fdtdec can decode Intel Quark MRC node. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: quark: Enable the Memory Reference Code buildBin Meng2015-02-06-0/+1
| | | | | | | | | | | | | | Turn on the Memory Reference code build in the quark Makefile. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: quark: Add System Memory Controller supportBin Meng2015-02-06-0/+3210
| | | | | | | | | | | | | | The codes are actually doing the memory initialization stuff. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: quark: Add utility codes needed for MRCBin Meng2015-02-06-0/+2068
| | | | | | | | | | | | | | Add various utility codes needed for Quark MRC. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: quark: Add Memory Reference Code (MRC) main routinesBin Meng2015-02-06-0/+391
| | | | | | | | | | | | | | Add the main routines for Quark Memory Reference Code (MRC). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: quark: Bypass TSC calibrationBin Meng2015-02-06-0/+5
| | | | | | | | | | | | | | | | | | For some unknown reason, the TSC calibration via PIT does not work on Quark. Enable bypassing TSC calibration and override TSC_FREQ_IN_MHZ to 400 per Quark datasheet in the Kconfig. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Allow overriding TSC_FREQ_IN_MHZBin Meng2015-02-06-20/+20
| | | | | | | | | | | | | | | | We should allow the value of TSC_FREQ_IN_MHZ to be overridden by the one in arch/cpu/<xxx>/Kconfig. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Enable the Intel quark/galileo buildBin Meng2015-02-06-0/+18
| | | | | | | | | | | | | | | | | | Make the Intel quark/galileo support avaiable in Kconfig and Makefile. With this patch, we can generate u-boot.rom for Intel galileo board. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Add basic Intel Galileo board supportBin Meng2015-02-06-0/+165
| | | | | | | | | | | | | | | | | | New board/intel/galileo board directory with minimum codes, plus board dts, defconfig and configuration files. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Add basic Intel Quark processor supportBin Meng2015-02-06-0/+295
| | | | | | | | | | | | | | | | Add minimum codes to support Intel Quark SoC. DRAM initialization is not ready yet so a hardcoded gd->ram_size is assigned. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: quark: Add Cache-As-RAM initializationBin Meng2015-02-06-0/+105
| | | | | | | | | | | | | | | | | | Quark SoC contains an embedded 512KiB SRAM (eSRAM) that is initialized by hardware. eSRAM is the ideal place to be used for Cache-As-RAM (CAR) before system memory is available. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Define macros for pci configuration space accessBin Meng2015-02-06-7/+13
| | | | | | | | | | | | | | | | | | Move PCI_REG_ADDR and PCI_REG_DATA from arch/x86/lib/pci_type1.c to arch/x86/include/asm/pci.h, also define PCI_CFG_EN so that these macros can be used for pci configuration space access. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: quark: Add routines to access message bus registersBin Meng2015-02-06-0/+183
| | | | | | | | | | | | | | | | | | | | | | In the Quark SoC, some chipset commands are accomplished by utilizing the internal message network within the host bridge (D0:F0). Accesses to this network are accomplished by populating the message control register (MCR), Message Control Register eXtension (MCRX) and the message data register (MDR). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Add header files for Intel Quark SoC definesBin Meng2015-02-06-0/+68
| | | | | | | | | | | | | | | | device.h for integrated pci devices' bdf on Quark SoC and quark.h for various memory-mapped and i/o-mapped base addresses within SoC. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Remove CONFIG_SATA_INTEL from x86-common.hBin Meng2015-02-06-1/+0
| | | | | | | | | | | | | | CONFIG_SATA_INTEL is not referenced anywhere, so remove it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Add support for Intel Minnowboard MaxSimon Glass2015-02-06-7/+4036
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a relatively low-cost x86 board in a small form factor. The main peripherals are uSD, USB, HDMI, Ethernet and SATA. It uses an Atom 3800 series CPU. So far only the dual core 2GB variant is supported. This uses the existing FSP support. Binary blobs are required to make this board work. The microcode update is included as a patch (all 3000 lines of it). Change-Id: I0088c47fe87cf08ae635b343d32c332269062156 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Add some documentation on how to port U-Boot on x86Simon Glass2015-02-06-0/+64
| | | | | | | | | | | | | | | | Some information has been gleaned on tools and procedures for porting U-Boot to different x86 platforms. Add a few notes to start things off. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Enable bootstage featuresSimon Glass2015-02-06-0/+3
| | | | | | | | | | | | | | | | Allow measuring of boot time using bootstage. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * scsi: bootstage: Measure time taken to scan the busSimon Glass2015-02-06-0/+3
| | | | | | | | | | | | | | | | | | On some hardware this time can be significant. Add bootstage support for measuring this. The result can be obtained using 'bootstage report' or passed on to the Linux via the device tree. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: spi: Support ValleyView in ICH SPI driverSimon Glass2015-02-06-20/+47
| | | | | | | | | | | | | | | | The base address is found in a different way and the protection bit is also in a different place. Otherwise it is very similar. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Allow a UART to be set up before the FSP is readySimon Glass2015-02-06-0/+7
| | | | | | | | | | | | | | | | | | Since the FSP is a black box it helps to have some sort of debugging available to check its inputs. If the debug UART is in use, set it up after CAR is available. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Allow FSP Kconfig settings for all x86Simon Glass2015-02-06-38/+38
| | | | | | | | | | | | | | | | While queensbay is the first chip with these settings, others will want to use them too. Make them common. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Remove unnecessary casts and fix comment typosSimon Glass2015-02-06-5/+5
| | | | | | | | | | | | | | Tidy up the FSP support code a little. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: mmc: Move common FSP functions into a common fileSimon Glass2015-02-06-72/+116
| | | | | | | | | | | | | | | | | | | | | | | | Since these board functions seem to be the same for all boards which use FSP, move them into a common file. We can adjust this later if future FSPs need more flexibility. This creates a generic PCI MMC device. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
generated by cgit v1.1 at 2024-11-05 13:35:53 +0000