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* dm: i2c: Provide an offset length parameter where neededSimon Glass2015-01-29-26/+32
| | | | | | | | | | Rather than assuming that the chip offset length is 1, allow it to be provided. This allows chips that don't use the default offset length to be used (at present they are only supported by the command line 'i2c' command which sets the offset length explicitly). Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de>
* dm: i2c: Add a compatbility layerSimon Glass2015-01-29-0/+165
| | | | | | | | | | | | | For boards which use multiple I2C devices, or for SOCs which support multiple boards, we might want to convert these to driver model at different times. At present this is difficult because we need to either use CONFIG_DM_I2C for a board or not. Add a compatibility layer which implements the old API, thus allowing a board to move to driver model for I2C without requiring that everything it uses is moved in the same commit. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: i2c: Rename driver model I2C functions to permit compatibilitySimon Glass2015-01-29-77/+82
| | | | | | | | | | | Add a dm_ prefix to driver model I2C functions so that we can keep the old ones around. This is a little unfortunate, but on reflection it is too difficult to change the API. We can undo this rename when most boards and drivers are converted to use driver model for I2C. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: Drop gpio.h header from fdtdec.cSimon Glass2015-01-29-2/+0
| | | | | | | Since GPIO support has now moved to the driver model uclass, we can drop this include. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: fdt: Remove the old GPIO functionsSimon Glass2015-01-29-172/+0
| | | | | | | Now that we support device tree GPIO bindings directly in the driver model GPIO uclass we can remove these functions. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: exynos: dts: Use GPIO bank phandles for GPIOsSimon Glass2015-01-29-39/+30
| | | | | | | | U-Boot now supports using GPIOs using bank phandles instead of global numbers. Update the exynos device tree files to use this. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Minkyu Kang <mk7.kang@samsung.com>
* dm: tegra: dts: Use TEGRA_GPIO() macro for all GPIOsSimon Glass2015-01-29-85/+109
| | | | | | This new method is much easier and matches the kernel. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: spi: Remove use of fdtdec GPIO supportSimon Glass2015-01-29-34/+28
| | | | | | These functions are going away, so use the new uclass support instead. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: usb: Remove use of fdtdec GPIO supportSimon Glass2015-01-29-30/+28
| | | | | | These functions are going away, so use the new uclass support instead. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: mmc: Remove use of fdtdec GPIO supportSimon Glass2015-01-29-41/+28
| | | | | | These functions are going away, so use the new uclass support instead. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: zynq: Remove inline gpio functionsSimon Glass2015-01-29-15/+0
| | | | | | | These functions serve no useful purpose, and conflict with the generic API. Drop them. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: tegra: nand: Remove use of fdtdec GPIO supportSimon Glass2015-01-29-5/+4
| | | | | | These functions are going away, so use the new uclass support instead. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: tegra: video: Remove use of fdtdec GPIO supportSimon Glass2015-01-29-38/+25
| | | | | | These functions are going away, so use the new uclass support instead. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: exynos: Add a GPIO translation functionSimon Glass2015-01-29-1/+12
| | | | | | | | This deals with the polarity bit. It also changes the GPIO devices so that the correct device tree node is linked to each one. This allows us to use the new uclass phandle functionality to implement a proper GPIO binding. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: tegra: Add a GPIO translation functionSimon Glass2015-01-29-0/+18
| | | | | | | This deals with the polarity bit and selecting the correct bank device given a GPIO number. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: cros_ec: Remove use of fdtdec GPIO supportSimon Glass2015-01-29-19/+8
| | | | | | These functions are going away, so use the new uclass support instead. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: demo: Add a simple GPIO demonstrationSimon Glass2015-01-29-2/+133
| | | | | | | | Add a new 'demo light' command which uses GPIOs to control imaginary lights. Each light is assigned a bit number in the overall value. This provides an example driver for using the new GPIO API. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: gpio: Mark the old GPIO API deprecatedSimon Glass2015-01-29-0/+21
| | | | | | | Add a deprecation notice to each function so that it is more obvious that we are moving GPIOs to driver model. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: gpio: Add better functions to request GPIOsSimon Glass2015-01-29-4/+461
| | | | | | | | | | | | | | | | | | | | | | | At present U-Boot sort-of supports the standard way of reading GPIOs from device tree nodes, but the support is incomplete, a bit clunky and only works for GPIO bindings where #gpio-cells is 2. Add new functions to request GPIOs, taking full account of the device tree binding. These permit requesting a GPIO with a simple call like: gpio_request_by_name(dev, "cd-gpios", 0, &desc, GPIOD_IS_IN); This will request the GPIO, looking at the device's node which might be this, for example: cd-gpios = <&gpio TEGRA_GPIO(B, 3) GPIO_ACTIVE_LOW>; The GPIO will be set to input mode in this case and polarity will be honoured by the GPIO calls. It is also possible to request and free a list of GPIOs. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: gpio: Add a driver GPIO translation methodSimon Glass2015-01-29-0/+45
| | | | | | | | | Only the GPIO driver knows about the full GPIO device tree binding used by a device. Add a method to allow the driver to provide this information to the uclass, including the GPIO offset within the device and flags such as the polarity. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: gpio: Add a native driver model APISimon Glass2015-01-29-71/+163
| | | | | | | | | | | | | | | | | | | | | | | So far driver model's GPIO uclass just implements the existing GPIO API. This has some limitations: - it requires manual device tree munging to support GPIOs in device tree (fdtdec_get_gpio() and friends) - it does not understand polarity - it is somewhat slower since we must scan for the GPIO device each time - Global GPIO numbering can change if other GPIO drivers are probed - it requires extra steps to set the GPIO direction and value The new functions have a dm_ prefix where necessary to avoid name conflicts but we can remove that when it is no-longer needed. The new struct gpio_desc holds all required information about the GPIO. For now this is intended to be stored by the client requesting the GPIO, but in future it might be brought into the uclass in some way. With these changes the old GPIO API still works, and uses the driver model API underneath. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: fdt: Add a function to decode phandles with argumentsSimon Glass2015-01-29-0/+177
| | | | | | | | | | | For GPIOs and other functions we want to look up a phandle and then decode a list of arguments for that phandle. Each phandle can have a different number of arguments, specified by a property in the target node. This is the "#gpio-cells" property for GPIOs. Add a function to provide this feature, taken modified from Linux 3.18. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: tegra: Bring in GPIO device tree bindingSimon Glass2015-01-29-0/+40
| | | | | | | At present the tegra GPIO driver does not fully support the existing device tree binding, but add the binding file to cover the existing partial support. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: exynos: Bring in GPIO device tree bindingSimon Glass2015-01-29-0/+41
| | | | | | | At present the exynos GPIO driver does not fully support the existing device tree binding, but add the binding file to cover the existing partial support. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: gpio: Bring in GPIO device tree bindingSimon Glass2015-01-29-0/+211
| | | | | | Add the binding file that we are about to support. Signed-off-by: Simon Glass <sjg@chromium.org>
* generic-board: show model name in board_init_f() tooMasahiro Yamada2015-01-29-24/+46
| | | | | | | | | | | | | The common/board_r.c has show_model_r() to display the model name if the DTB has a "model" property. It sounds useful to have a similar function in common/board_f.c too because most of the boards show their board name before relocation. Instead of implementing the same function in both common/board_f.c and common/board_r.c, let's split it up into common/show_board_info.c. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org>
* cmd_i2c: change variable type for 10bit addressing supportMasahiro Yamada2015-01-29-11/+11
| | | | | | | | | | | To store 10bit chip address, the variable type should not be uchar, but uint. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Heiko Schocher <hs@denx.de> Cc: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher<hs@denx.de>
* ARM: UniPhier: enable CONFIG_I2C_EEPROMMasahiro Yamada2015-01-29-0/+3
| | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org>
* ARM: UniPhier: enable I2C for UniPhier SoCsMasahiro Yamada2015-01-29-0/+6
| | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org>
* i2c: UniPhier: add driver for UniPhier FIFO-builtin i2c controllerMasahiro Yamada2015-01-29-0/+388
| | | | | | | | | | This commit adds on-chip I2C driver used on newer SoCs of Panasonic UniPhier platform. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de>
* i2c: UniPhier: add driver for UniPhier i2c controllerMasahiro Yamada2015-01-29-0/+248
| | | | | | | | | | This commit adds on-chip I2C driver used on some old Panasonic UniPhier SoCs. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de>
* i2c: add CONFIG_DM_I2C to KconfigMasahiro Yamada2015-01-29-0/+6
| | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de>
* lcd: fix console address is not initializedBo Shen2015-01-28-0/+1
| | | | | | | | | | This commit 904672e (lcd: refactor lcd console stuff into its own file), which cause lcd console address is not initialized. This patch initialize the lcd console use the default value, will be update when splash screen is enabled. Signed-off-by: Bo Shen <voice.shen@atmel.com>
* Makefile: clean boot.binBo Shen2015-01-28-1/+1
| | | | | | | | | When build for Atmel related boards which support SPL, it will generate boot.bin, also clean when it when do "make clean" operation. Signed-off-by: Bo Shen <voice.shen@atmel.com> Acked-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* spl: Change printf to puts for "Unsupported boot-device"Stefan Roese2015-01-28-1/+1
| | | | | | | | | | | | | | Microblaze currently doesn't use printf in SPL. So this one line was the only reference to it and resulted in the printf functionality to be pulled in. Exceeding the 4k size limit. Lets change the printf back to puts so that Microblaze is fixed again. The only drawback is that the detected boot-device number will not be printed. But this message alone should be helpful enough to get an idea where the boot process is broken. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Michal Simek <michal.simek@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
* Merge branch 'master' of git://git.denx.de/u-boot-x86Tom Rini2015-01-26-288/+1078
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| * x86: config: chromebook_link: Enable environmentSimon Glass2015-01-24-0/+7
| | | | | | | | | | | | | | Enable an environment area. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: ivybridge: Drop the Kconfig MRC cache informationSimon Glass2015-01-24-28/+0
| | | | | | | | | | | | This is now stored in the device tree. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: config: Enable hook for saving MRC configurationSimon Glass2015-01-24-0/+6
| | | | | | | | | | | | | | Add a hook to ensure that this information is saved. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Implement a cache for Memory Reference Code parametersSimon Glass2015-01-24-0/+464
| | | | | | | | | | | | | | | | | | | | | | The memory reference code takes a very long time to 'train' its SDRAM interface, around half a second. To avoid this delay on every boot we can store the parameters from the last training sessions to speed up the next. Add an implementation of this, storing the training data in CMOS RAM and SPI flash. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: dts: Add SPI flash MRC details for chromebook_linkSimon Glass2015-01-24-1/+14
| | | | | | | | | | | | | | | | Correct the SPI flash compatible string, add an alias and specify the position of the MRC cache, used to store SDRAM training settings for the Memory Reference Code. Signed-off-by: Simon Glass <sjg@chromium.org>
| * Allow architecture-specific memory reservationSimon Glass2015-01-24-0/+7
| | | | | | | | | | | | | | All memory to be reserved for use after relocation by adding a new call to perform this reservation. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: spi: Add device tree supportSimon Glass2015-01-24-0/+8
| | | | | | | | | | | | | | As a temporary measure before the ICH driver moves over to driver model, add device tree support to the driver. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: rtc: mc146818: Add helpers to read/write CMOS RAMSimon Glass2015-01-24-48/+105
| | | | | | | | | | | | | | On x86 we use CMOS RAM to read and write some settings. Add basic support for this, including access to registers 128-255. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: Use ipchecksum from net/Simon Glass2015-01-24-97/+4
| | | | | | | | | | | | | | The existing IP checksum function is only accessible to the 'coreboot' cpu. Drop it in favour of the new code in the network subsystem. Signed-off-by: Simon Glass <sjg@chromium.org>
| * net: Add a separate file for IP checksummingSimon Glass2015-01-23-0/+91
| | | | | | | | | | | | | | | | Move the checksum code out into its own file so it can be used elsewhere. Also use a new version which supports a length which is not a multiple of 2 and add a new function to add two checksums. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: dts: Add compatible string for Intel ICH9 SPI controllerSimon Glass2015-01-23-0/+2
| | | | | | | | | | | | | | Add this to the enum so that we can use the various fdtdec functions. A later commit will move this driver to driver model. Signed-off-by: Simon Glass <sjg@chromium.org>
| * pci: tegra: Fix port information parsingSjoerd Simons2015-01-23-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | commit a62e84d7b1824a202dd incorrectly changed the tegra pci code to the new fdtdec pci helpers. To get the device index of the root port, the "reg" property should be parsed from the dtb (as was previously the case). With this patch i can successfully network boot my jetson tk1 Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com>
| * x86: Fix various code format issues in start16.SBin Meng2015-01-23-10/+10
| | | | | | | | | | | | | | | | | | | | | | Various minor code format issues are fixed in start16.S: - U-boot -> U-Boot - 32bit -> 32-bit - Use TAB instead of SPACE to indent - Move the indention location of the GDT comment block Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Test mtrr support flag before accessing mtrr msrBin Meng2015-01-23-2/+19
| | | | | | | | | | | | | | | | | | | | On some x86 processors (like Intel Quark) the MTRR registers are not supported. This is reflected by the CPUID (EAX 01H) result EDX[12]. Accessing the MTRR registers on such processors will cause #GP so we must test the support flag before accessing MTRR MSRs. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
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