summaryrefslogtreecommitdiff
Commit message (Collapse)AuthorAgeLines
...
* | rockchip: gpio: Implement the get_function() methodSimon Glass2016-01-21-4/+36
| | | | | | | | | | | | | | Provide this method so that 'gpio status' works fully. It now shows whether a pin is used for input, output or some other function. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: gpio: Read the GPIO value correctlySimon Glass2016-01-21-1/+1
| | | | | | | | | | | | This function should return 0 or 1, not a mask. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: pinctrl: Implement the get_gpio_mux() methodSimon Glass2016-01-21-16/+52
| | | | | | | | | | | | | | Implement this so that the GPIO command will be able to report whether a GPIO is used for input or output. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: pinctrl: Reduce the size for SPLSimon Glass2016-01-21-3/+17
| | | | | | | | | | | | | | This file has many features that are not needed by SPL. Use #ifdef to remove the unused features and reduce the code size. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: clk: Make rkclk_get_clk() SoC-specificSimon Glass2016-01-21-29/+30
| | | | | | | | | | | | | | | | | | | | | | | | The current method assumes that clocks are numbered from 0 and we can determine a clock by its number. It is safer to use an ID in the clock's platform data to avoid the situation where another clock is bound before the one we expect. Move the existing code into rk3036 since it still works there. Add a new implementation for rk3288. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: spi: Correct the bus init codeSimon Glass2016-01-21-2/+2
| | | | | | | | | | | | | | Two of the init values are created locally so cannot be out of range. The masking is unnecessary and in one case is incorrect. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: spi: Remember the last speed to avoid re-setting itSimon Glass2016-01-21-1/+4
| | | | | | | | | | | | | | Rather than changing the clock to the same value on every transaction, remember the last value and don't adjust the clock unless it is necessary. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: reset: Use the rk_clr/setreg() interfaceSimon Glass2016-01-21-2/+2
| | | | | | | | | | | | Use this function in preference to the macro. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: sdram: Use the rk_clr/setreg() interfaceSimon Glass2016-01-21-4/+3
| | | | | | | | | | | | Use this function in preference to the macro. Signed-off-by: Simon Glass <sjg@chromium.org>
* | dm: clk: Add a simple version of clk_get_by_index()Simon Glass2016-01-21-1/+17
| | | | | | | | | | | | | | This function adds quite a bit of code to SPL and we probably don't need all the features in SPL. Add a simple version (for SPL only) to save space. Signed-off-by: Simon Glass <sjg@chromium.org>
* | dm: power: Allow regulators to not implement all operationsSimon Glass2016-01-21-0/+2
| | | | | | | | | | | | | | | | Some regulators will not implement any operations (e.g. fixed regulators). This is not an error, so allow the autoset process to continue when one of these regulators is found. Signed-off-by: Simon Glass <sjg@chromium.org>
* | dm: power: Tidy up debugging output and return valuesSimon Glass2016-01-21-8/+19
| | | | | | | | | | | | | | | | The currect PMIC debugging is a little confusing. Adjust it so that it is clear whether the operation succeeded or failed. Also, avoid creating a new error return value when a perfectly good one is already available. Signed-off-by: Simon Glass <sjg@chromium.org>
* | dm: core: Export uclass_find_device_by_of_offset()Simon Glass2016-01-21-2/+18
| | | | | | | | | | | | | | | | It is sometimes useful to be able to find a device before probing it, perhaps to set up some platform data for it. Allow finding by of_offset also. Signed-off-by: Simon Glass <sjg@chromium.org>
* | dm: pinctrl: Add a way for a GPIO driver to obtain a pin functionSimon Glass2016-01-21-0/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | GPIO drivers want to be able to show if a pin is enabled for input, output, or is being used by another function. Some drivers can easily find this and the code is included in the driver. For some SoCs this is more complex. Conceptually this should be handled by pinctrl rather than GPIO. Most pinctrl drivers will have this feature anyway. Add a method by which a GPIO driver can obtain the pin mux value given a GPIO reference. This avoids repeating the code in two places. Signed-off-by: Simon Glass <sjg@chromium.org>
* | dm: power: Allow regulators to be omitted from SPLSimon Glass2016-01-21-2/+34
| | | | | | | | | | | | | | | | For some boards the pmic interface is useful but the regulator interface (which comes with it) is too large. Allow them to be separated such that SPL can decide which it needs. Signed-off-by: Simon Glass <sjg@chromium.org>
* | spi: Correct device tree usage in spi_flash_decode_fdt()Simon Glass2016-01-21-6/+3
| | | | | | | | | | | | | | | | | | | | | | This function currently searches the entire device tree for a node that it thinks is relevant. But the node is known and is passed in. Correct the code and enable it only with driver model, since only driver-model boards will use it. This avoids bringing in a large number of strings from fdtdec. Signed-off-by: Simon Glass <sjg@chromium.org>
* | dm: i2c: Allow muxes to be enabled for SPL separatelySimon Glass2016-01-21-3/+12
| | | | | | | | | | | | | | Since I2C muxes are seldom needed in SPL, and the code for this increases the size somewhat, add a separate option to enable I2C muxes for SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
* | cros_ec: Disable the Chrome OS EC in SPLSimon Glass2016-01-21-0/+2
| | | | | | | | | | | | | | This is not used in SPL so don't allow it to be built there, even if I2C is enabled in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
* | gpio: Allow 's' as an abbreviation for 'status'Simon Glass2016-01-21-1/+1
| | | | | | | | | | | | | | The 'gpio' command allows abbreviations for most subcommands. Allow them for 'status' also. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: jerry: Drop unused optionsSimon Glass2016-01-21-5/+2
| | | | | | | | | | | | | | To reduce the SPL image size, drop the LED features. Jerry does not have an LED and we can leave out GPIO support also. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: Disable simple-bus in SPL for firefly-rk3288, jerrySimon Glass2016-01-21-0/+2
| | | | | | | | | | | | This is not needed for booting, so drop it from SPL to save about 300 bytes. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: jerry: Enable the RK808 PMIC and regulatorSimon Glass2016-01-21-0/+2
| | | | | | | | | | | | Enable this PMIC and regulator, which is used on jerry. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: Move firefly and jerry to use the full pinctrlSimon Glass2016-01-21-2/+0
| | | | | | | | | | | | Use the full pinctrl driver in U-Boot proper. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: pinctrl: Add a full pinctrl driverSimon Glass2016-01-21-1/+229
| | | | | | | | | | | | | | We can make use of the device tree to configure pinctrl settings. Add this support for the driver so we can use it in U-Boot proper. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: mmc: Update the driver to use the new clock IDSimon Glass2016-01-21-1/+1
| | | | | | | | | | | | We can use the new clk_get_by_index() function to get the correct clock. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: spi: Avoid setting the pinctrl twiceSimon Glass2016-01-21-3/+6
| | | | | | | | | | | | | | | | If full pinctrl is enabled we don't need to manually set the pinctrl in the driver. It will happen automatically. Adjust the code to suit - we will still use manual mode in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: spi: Update the driver to use the new clock IDSimon Glass2016-01-21-15/+17
| | | | | | | | | | | | We can use the new clk_get_by_index() function to get the correct clock. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: i2c: Update the driver to use the new clock IDSimon Glass2016-01-21-16/+22
| | | | | | | | | | | | We can use the new clk_get_by_index() function to get the correct clock. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: clock: Add a function to find a clock by IDSimon Glass2016-01-21-2/+34
| | | | | | | | | | | | | | | | The current approach of using uclass_get_device() is error-prone. Another clock (for example a fixed-clock) may cause it to break. Add a function that does a proper search. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: clk: Add a function to get a peripheral clock rateSimon Glass2016-01-21-0/+37
| | | | | | | | | | | | | | It is useful to be able to read the rate of a peripheral clock. Add a handler for that. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: clock: Rename the general clock variable to gclk_rateSimon Glass2016-01-21-12/+12
| | | | | | | | | | | | The current name is confusing and a bit verbose. Rename it. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: Use a separate clock ID for clocksSimon Glass2016-01-21-44/+50
| | | | | | | | | | | | | | | | | | | | At present we use the same peripheral ID for clocks and pinctrl. While this works it is probably better to use the device tree clock binding ID for clocks. We can use the clk_get_by_index() function to find this. Update the clock drivers and the code that uses them. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: jerry: Disable pmic-int-1 setup to avoid a hangSimon Glass2016-01-21-1/+4
| | | | | | | | | | | | | | This hangs when activated (by probing the PMIC). Disable it for now until we understand the root cause. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: Use pwrseq for MMC start-up on jerrySimon Glass2016-01-21-4/+13
| | | | | | | | | | | | | | This is defined in the device tree in Linux. Copy over the settings so that this can be used instead of hard-coding the reset line. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: Correct the defconfig orderSimon Glass2016-01-21-5/+5
| | | | | | | | | | | | This has got out of sequence somehow. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: mmc: Use a pwrseq device if availableSimon Glass2016-01-21-0/+47
| | | | | | | | | | | | | | Use the pwrseq uclass to find a suitable power sequence for the MMC device. If this is enabled in the device tree, we will pick it up automatically. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: Convert the PMU IOMUX registers into an arraySimon Glass2016-01-21-6/+10
| | | | | | | | | | | | | | | | | | This is easier to deal with when using generic code since it allows us to use a register index instead of naming each register. Adjust it, adding an enum to improve readability. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: Avoid using MMC code when not booting from MMCSimon Glass2016-01-21-0/+2
| | | | | | | | | | | | This saves some code space in SPL which is useful on jerry. Signed-off-by: Simon Glass <sjg@chromium.org>
* | dm: Add a power sequencing uclassSimon Glass2016-01-21-0/+62
| | | | | | | | | | | | | | | | Some devices need special sequences to be used when starting up. Add a uclass for this. Drivers can be added to provide specific features as needed. Signed-off-by: Simon Glass <sjg@chromium.org>
* | power: Add support for RK808 regulatorsSimon Glass2016-01-21-0/+311
| | | | | | | | | | | | | | Add regulator support for the RK808 PMIC. It integrated 4 BUCKs and 8 LDOs all of which are supported by this driver. Signed-off-by: Simon Glass <sjg@chromium.org>
* | power: Add base support for the RK808 PMICSimon Glass2016-01-21-0/+183
| | | | | | | | | | | | | | | | | | | | This Rockchip PMIC provides features suitable for battery-powered applications. It is commonly used with Rockchip SoCs. Add a driver which provides register access. The regulator driver will use this. Signed-off-by: Simon Glass <sjg@chromium.org>
* | dts: Bring in pinctrl device tree bindingSimon Glass2016-01-21-0/+236
| | | | | | | | | | | | Add this binding file since we now use it in U-Boot. Signed-off-by: Simon Glass <sjg@chromium.org>
* | dm: pmic: Add 'reg status' to show all regulatorsSimon Glass2016-01-21-10/+56
| | | | | | | | | | | | | | It is convenient to be able to see the status of all regulators in a list. Add this feature to the 'reg status' command. Signed-off-by: Simon Glass <sjg@chromium.org>
* | dm: pinctrl: Add a function to parse PIN_CONFIG flagsSimon Glass2016-01-21-0/+25
| | | | | | | | | | | | | | | | Add a function which produces a flags word from a few common PIN_CONFIG settings. This is useful for simple pinctrl drivers that don't need to worry about drive strength, etc. Signed-off-by: Simon Glass <sjg@chromium.org>
* | dm: core: Don't set pinctrl for pinctrl devicesSimon Glass2016-01-21-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | There is sort-of race condition when a pinctrl device is probed. The pinctrl function is called which may end up using the same device as is being probed. This results in operations being used before the device is actually probed. For now, disallow pinctrl operations on pinctrl devices while probing. An alternative solution would be to move the operation to later in the device_probe() function (for pinctrl devices only) but this needs more thought. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: kylin: Store env in emmcJeffy Chen2016-01-21-0/+12
| | | | | | | | | | | | | | | | There's a 64K reserved area at the end of the first 4M. Store env there, so we can use fastboot to flash it. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | rockchip: kylin: Check fastboot requestJeffy Chen2016-01-21-0/+35
| | | | | | | | | | | | | | | | | | We will save boot mode flag in grf's os_reg[4], if fastboot requested or fastboot key pressed, try to enter fastboot mode at preboot stage. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | rockchip: kylin: Add default gpt partition tableJeffy Chen2016-01-21-0/+29
| | | | | | | | | | | | | | | | | | | | Add default android gpt partition table for kylin board. Use "gpt write mmc 0 $partitions" to apply. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* | rockchip: rk3036: Bind GPIO banksJeffy Chen2016-01-21-0/+8
| | | | | | | | | | | | | | | | Call dm_scan_fdt_node() in rk3036 pinctrl uclass binding. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: bootm: Try to use relocated ramdiskJeffy Chen2016-01-21-1/+11
| | | | | | | | | | | | | | | | | | After boot_ramdisk_high(), ramdisk would be relocated to initrd_start & initrd_end, so use them instead of rd_start & rd_end. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
generated by cgit v1.1 at 2024-11-15 17:36:58 +0000