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* x86: Move CONFIG_8259_PIC and CONFIG_8254_TIMER to KconfigBin Meng2015-11-13-2/+15
| | | | | | | Add Kconfig options for 8259 and 8254. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Rename pcat_ to i8254 and i8259 accordinglyBin Meng2015-11-13-10/+10
| | | | | | | | Rename pcat_timer.c to i8254.c and pcat_interrupts.c to i8259.c, to match their header file names (i8254.h and i8259.h). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Initialize i8254 timer counter 1Bin Meng2015-11-13-0/+10
| | | | | | | | | Initialize counter 1, used to refresh request signal. This is required for legacy purpose as some codes like vgabios utilizes counter 1 to provide delay functionality. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Fix cosmetic issues in the i8254 and i8259 codesBin Meng2015-11-13-53/+52
| | | | | | | | This cleans up i8254 and i8259 codes to fix several cosmetic issues, like coding convention and some comments improvement. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Remove dead codes wrapped by PARANOID_IRQ_TRIGGERSBin Meng2015-11-13-16/+0
| | | | | | | | PARANOID_IRQ_TRIGGERS is not referenced anywhere in U-Boot. Remove these dead codes wrapped by it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Rename CONFIG_SYS_NUM_IRQS to SYS_NUM_IRQSBin Meng2015-11-13-13/+10
| | | | | | | | | CONFIG_SYS_NUM_IRQS is actually not something we can configure, but an architecture defined number of ISA IRQs. Move it from x86-common.h to asm/interrupt.h and rename it to SYS_NUM_IRQS. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* board_init: Change the logic to setup malloc_baseFabio Estevam2015-11-12-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | Prior to commit 5ba534d247d418 ("arm: Switch 32-bit ARM to using generic global_data setup") we used to have assembly code that configured the malloc_base address. Since this commit we use the board_init_f_mem() function in C to setup malloc_base address. In board_init_f_mem() there was a deliberate choice to support only early malloc() or full malloc() in SPL, but not both. Adapt this logic to allow both to be used, one after the other, in SPL. This issue has been observed in a Congatec board, where we need to retrieve the manufacturing information from the SPI NOR (the SPI API calls malloc) prior to configuring the DRAM. In this case as malloc_base was not configured we always see malloc to fail. With this change we are able to use malloc in SPL prior to DRAM gets initialized. Also update the CONFIG_SYS_SPL_MALLOC_START entry in the README file. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2015-11-12-669/+1353
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| * ARM: tegra: note that p2371-2180 is Jetson TX1Stephen Warren2015-11-12-5/+5
| | | | | | | | | | | | | | | | | | | | p2371-2180 is the engineering board name for the Jetson TX1 developer kit. Update Kconfig description and help text to make this obvious to everyone. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * Tegra: T210: Add QSPI driverTom Warren2015-11-12-0/+425
| | | | | | | | | | | | | | | | | | | | This is the normal Tegra SPI driver modified to work with the QSPI controller in Tegra210. It does not do 2x/4x transfers or any other QSPI protocol. Signed-off-by: Yen Lin <yelin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * ARM: tegra: rename GPU functionsAlexandre Courbot2015-11-12-8/+8
| | | | | | | | | | | | | | | | | | Rename GPU functions to less generic names to avoid potential name collisions. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: simplify GPU setupAlexandre Courbot2015-11-12-29/+22
| | | | | | | | | | | | | | | | | | | | Enable the GPU node in the system-wide ft_system_setup() hook instead of the board-specific ft_board_hook(). This allows us to enable GPU per SoC generation instead of per-board as we did initially. Reported-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: remove vpr_configured() functionAlexandre Courbot2015-11-12-12/+1
| | | | | | | | | | | | | | | | There is no justification for this function, especially in exported form. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: error check Tegra210 XUSB padctl waitsStephen Warren2015-11-12-5/+20
| | | | | | | | | | | | | | | | | | Add code to detect timeouts when waiting for HW events such as PLL lock done. Any errors are logged and trigger an error return code. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: add lane tables to Tegra210 XUSB padctlStephen Warren2015-11-12-6/+76
| | | | | | | | | | | | | | | | | | Add the tables defining which pads and mux options exist in the Tegra210 XUSB padctl hardware. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: switch Tegra210 to common XUSB padctlStephen Warren2015-11-12-158/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | This change simply deletes code from the Tegra210 XUSB padctl driver that is already present in the common XUSB padctl code. Since all the arrays in tegra210_socdata are empty, this update may leave the Tegra210 XUSB padctl driver non-functional at run-time. However, (a) this driver is not used yet so no regression can be observed and (b) the next commit will immediately fix this up. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: parameterize common XUSB codeStephen Warren2015-11-12-82/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | There are some differences between the Tegra124 and Tegra210 XUSB padctl code. So far, the common XUSB padctl code only supports Tegra124. Add some parameters etc. so that it can work for both chips. This also allows moving Tegra124's process_nodes() into the common file; something that would have requires edits during the move if done in the previous commit. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: create common XUSB padctl driver fileStephen Warren2015-11-12-341/+414
| | | | | | | | | | | | | | | | | | | | | | | | | | A fair amount of the XUSB padctl driver will be common between Tegra124 and Tegra210. To avoid cut/paste between the two chips, create a new file that will contain the common code, and convert the Tegra124 code to use it. This change doesn't move every last piece of code that can/will be shared, but rather concentrates on moving code that can be moved with zero changes, so there are no other diffs mixed in. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: clean up XUSB padctl error() callsStephen Warren2015-11-12-19/+14
| | | | | | | | | | | | | | | | | | | | This file defines pr_fmt(), so the individual error() calls don't need to include the prefix in their format strings. Doing so results in duplicate text in any error messages. Remove the duplication. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: rename dummy XUSB padctl implementationStephen Warren2015-11-12-1/+1
| | | | | | | | | | | | | | | | | | | | A future patch will soon move some of the XUSB padctl code into a common file in arch/arm/mach-tegra. Rename the existing dummy XUSB padctl file to avoid conflicting with that, or being confusing. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: enable PCI support of p2371-2180Stephen Warren2015-11-12-0/+90
| | | | | | | | | | | | | | | | | | | | p2371-2180 has two PCI ports; a regular x4 slot and a x1 M.2 slot. This patch adds the relevant DT to enable the PCI controller and configure the XUSB padctl pin muxing, and code to turn on the PCI power and enable PCI features in U-Boot. I have only tested the x4 slot. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: add PCI to Tegra210 SoC DTStephen Warren2015-11-12-0/+66
| | | | | | | | | | | | | | | | | | | | Tegra210's PCI controller is largely identical to Tegra124, and hence shares the same binding. However, it has a unique compatible value due to the existence of at least one new HW bug that would prevent any driver for a previous HW version from operating correctly. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * pci: tegra: add/enable support for Tegra210Stephen Warren2015-11-12-0/+24
| | | | | | | | | | | | | | | | | | This needs a separate compatible value from Tegra124 since the new HW version has bugs that would prevent a driver for previous HW versions from operating at all. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * pci: tegra: call tegra_pcie_board_init() earlierStephen Warren2015-11-12-2/+2
| | | | | | | | | | | | | | | | | | | | The board PCI setup code may control regulators that are required simply to bring up the PCI controller itself (or PLLs, IOs, ... it uses). Move the call to this function earlier so that all board-provided resources are ready early enough for everything to work. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * pci: tegra: implement PCA enable workaroundStephen Warren2015-11-12-0/+14
| | | | | | | | | | | | | | | | | | | | Tegra210's PCIe controller has a bug that requires the PCA (performance counter) feature to be enabled. If this isn't done, accesses to device configuration space will hang the chip for tens of seconds. Implement the workaround. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * pci: tegra: use #address-/size-cells from DTStephen Warren2015-11-12-3/+30
| | | | | | | | | | | | | | | | | | The number of cells used by each entry in the DT ranges property is determined by the #address-cells/#size-cells properties. Fix the code to respect this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * pci: tegra: clip RAM size to 32-bitsStephen Warren2015-11-12-1/+9
| | | | | | | | | | | | | | | | | | Tegra peripherals can generally access a 32-bit physical address space, and I believe this applies to PCIe. Clip the PCI region that refers to DRAM so it fits into 32-bits to avoid issues. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra210: implement PLLE init procedure from TRMStephen Warren2015-11-12-47/+132
| | | | | | | | | | | | | | | | | | | | | | | | Implement the procedure that the TRM mandates to initialize PLLREFE and PLLE. This makes the PLL actually lock. Note that this section of the TRM is being cleaned up to remove some confusion. The set of register accesses in this patch should be final, although the step numbers/descriptions might still change. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | am43xx_evm: Add DFU support for qspi flashVignesh R2015-11-12-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support to update firmware on qspi flash present on am437x-sk-evm and am43xx-epos-evm via DFU. On device: => setenv dfu_alt_info ${dfu_alt_info_qspi} => dfu 0 sf 0:0 On host: $ sudo dfu-util -l $ sudo dfu-util -D u-boot.bin -a u-boot.bin Signed-off-by: Vignesh R <vigneshr@ti.com>
* | spl: Add support for CONFIG_OF_EMBED=yMichal Simek2015-11-12-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_OF_EMBED=y is the option which is here only for testing purpose and shouldn't be enabled by default as is describe at: "dts: Add a comment about CONFIG_OF_EMBED being for local use" (sha1: 3d3f60cb7a6bb6c338e00a9769fa918a8536096c) But still enabling this option locally shouldn't end up with compilation error when you build SPL. This patch fix it. Compilation error: lib/built-in.o: In function `fdtdec_setup': /mnt/disk/u-boot/lib/fdtdec.c:1246: undefined reference to `__dtb_dt_begin' Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reported-by: Tom Rini <trini@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | openrisc: updating build tools naming conventionGuillaume REMBERT2015-11-12-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Dear u-boot community, I just made a small change on the openrisc-generic platform configuration to take in account the new naming convention (or1k instead of or32, so the build process gets fine). Could you take care to review and approve the following patch, please? Kind regards,
* | Fix trini email in the get_maintainer.pl scriptAndy Fleming2015-11-12-1/+1
| | | | | | | | | | | | Looks like one spot got missed. Probably due to the backslash. Signed-off-by: Andy Fleming <afleming@gmail.com>
* | pengwyn: nand and ethernet fixesVincent BENOIT2015-11-12-28/+90
| | | | | | | | | | | | -> Add National instrument ethernet transceiver configuration used (DP83848) -> Change cpsw slave phy address -> modify nand configuration to use the correct ECC and correct nand features
* | block: ahci: Remove dead codeFabio Estevam2015-11-12-36/+0
| | | | | | | | | | | | | | | | | | CONFIG_AHCI_SETFEATURES_XFER is not selected by any user, so delete the dead code. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | common: Simplify get_clocks() #ifdefPeng Fan2015-11-12-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | get_clocks is wrapped by CONFIG_FSL_CLK and CONFIG_M68K in seperate piece code. They can be merged into one snippet. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Alexey Brodkin <abrodkin@synopsys.com> Cc: "angelo@sysam.it" <angelo@sysam.it> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Stephen Warren <swarren@nvidia.com> Cc: "Andreas Bießmann" <andreas.devel@googlemail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Angelo Dureghello <angelo@sysam.it>
* | configs: Use config_distro_defaults.h in ti_armv7_common.hMatwey V. Kornilov2015-11-12-14/+2
| | | | | | | | | | | | | | | | | | CONFIG_BOOTDELAY is defined in config_distro_defaults.h Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com> [trini: Drop omap3_logic.h settings which were a warning and no longer correct usage]. Signed-off-by: Tom Rini <trini@konsulko.com>
* | i2c: Fix pca953x endianess issueDirk Eibach2015-11-12-1/+3
| | | | | | | | | | | | | | By reading 2 consecutive bytes from i2c to an u16 value we have an endianess issue. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
* | i2c: soft_i2c: Fix bus indizesDirk Eibach2015-11-12-10/+10
| | | | | | | | | | | | | | Since busses are sorted in alphabetical order, introducing more than nine busses led to unexpected behaviour. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
* | board: gdsys: Enable osd on output onlyDirk Eibach2015-11-12-2/+4
| | | | | | | | Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
* | board: gdsys: Add osdsize commandDirk Eibach2015-11-12-0/+38
| | | | | | | | | | | | osdsize adjusts the gdsys IHS osd dimensions in characters. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
* | hrcon: Add fan controllersDirk Eibach2015-11-12-36/+119
| | | | | | | | Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
* | hrcon: Add support for the DH variantDirk Eibach2015-11-12-37/+225
| | | | | | | | | | | | hrcon DH(dual head) has two video outputs per FPGA. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
* | hrcon: Fix videoboard i2c setupDirk Eibach2015-11-12-2/+8
| | | | | | | | | | | | | | | | - i2c addresses for the videoboard port expanders were wrong. - the fpga reset signal was not initialized. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
* | hrcon: Use generic ioep-fpga supportDirk Eibach2015-11-12-239/+9
| | | | | | | | | | | | | | The strider platform moved some generic code into ioep-fpga.c. Make use of that on hrcon platform. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
* | mpc83xx: Add strider boardDirk Eibach2015-11-12-41/+1764
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The gdsys strider board is based on a Freescale MPC8308 SOC. It boots from NOR-Flash, kernel and rootfs are stored on SD-Card. On board peripherals include: - 1x 10/100 Mbit/s Ethernet (optional) - Lattice ECP3 FPGA connected via eLBC Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> [trini: Drop setting CONFIG_SYS_GENERIC_BOARD, this is always true now] Signed-off-by: Tom Rini <trini@konsulko.com>
* | hrcon: Remove CH7301 configurationDirk Eibach2015-11-12-1/+0
| | | | | | | | | | | | | | hrcon has no CH7301 DVI-transmitter. Probably not removed when copying from iocon. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
* | iocon: reset FPGAs in last_stage_init()Reinhard Pfau2015-11-12-1/+7
| | | | | | | | | | | | | | - Reset FPGAs in last_stage_init() Signed-off-by: Reinhard Pfau <pfau@gdsys.de> Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
* | controlcenterd: Disable sideband clocksDirk Eibach2015-11-12-0/+5
| | | | | | | | Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
* | dlvision-10g: Support displayportDirk Eibach2015-11-12-36/+51
| | | | | | | | | | | | Support dlvision-10g hardware with displayport output. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
* | board: gdsys: Consider DP501 limits on link trainingDirk Eibach2015-11-12-2/+20
| | | | | | | | | | | | | | | | DP501 only supports DP 1.1a. Limit settings for link bandwidth and lane count to values allowed by DP 1.1a. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
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